CN104347692B - Suppress tunneling field-effect transistor that output nonlinear is opened and preparation method thereof - Google Patents

一种抑制输出非线性开启的隧穿场效应晶体管，包括隧穿源区，沟道区，漏区，半导体衬底区，位于沟道区上方的栅介质层，以及位于栅介质层之上的控制栅；所述的沟道区位于隧穿源区上方且位置与隧穿源区部分重叠，在沟道区与隧穿源区界面处形成隧穿结；所述漏区与沟道区平行，位于沟道区的另一侧；所述控制栅位于沟道区与隧穿源区重叠部分的上方，而在靠近漏区附近的沟道区存在一个没有控制栅覆盖的区域；并且，所述沟道区选用能态密度低于1E18cm^‑3的半导体材料。该隧穿场效应晶体管可以有效抑制器件输出特性中的非线性开启现象，并保持了较陡直的亚阈值斜率。

A tunneling field effect transistor that suppresses output nonlinear turn-on, comprising a tunneling source region, a channel region, a drain region, a semiconductor substrate region, a gate dielectric layer above the channel region, and a gate dielectric layer above the gate dielectric layer Control gate; the channel region is located above the tunneling source region and partially overlaps with the tunneling source region, forming a tunneling junction at the interface between the channel region and the tunneling source region; the drain region is parallel to the channel region , located on the other side of the channel region; the control gate is located above the overlapping portion of the channel region and the tunneling source region, and there is an area not covered by the control gate in the channel region near the drain region; and, the The channel region is selected from a semiconductor material with an energy state density lower than 1E18cm ^-3 . The tunneling field effect transistor can effectively suppress the nonlinear turn-on phenomenon in the output characteristics of the device, and maintain a relatively steep subthreshold slope.

抑制输出非线性开启的隧穿场效应晶体管及其制备方法Tunneling Field Effect Transistor with Suppressed Output Nonlinear Turn-on and Preparation Method thereof

技术领域technical field

本发明属于CMOS超大规模集成电路(ULSI)中场效应晶体管逻辑器件领域，具体涉及一种抑制输出非线性开启的隧穿场效应晶体管及其制备方法。The invention belongs to the field of field-effect transistor logic devices of CMOS ultra-large-scale integrated circuits (ULSI), and in particular relates to a tunneling field-effect transistor capable of suppressing output nonlinear turn-on and a preparation method thereof.

背景技术Background technique

自集成电路诞生以来，微电子集成技术一直按照“摩尔定律”不断发展，半导体器件尺寸不断缩小。随着半导体器件进入深亚微米范围，传统MOSFET器件由于受到自身扩散漂流的导通机制所限，亚阈值斜率受到热电势kT/q的限制而无法随着器件尺寸的缩小而同步减小。这就导致MOSFET器件泄漏电流缩小无法达到器件尺寸缩小的要求，整个芯片的能耗不断上升，芯片功耗密度急剧增大，严重阻碍了芯片系统集成的发展。为了适应集成电路的发展趋势，新型超低功耗器件的开发和研究工作就显得特别重要。隧穿场效应晶体管(TFET，Tunneling Field-Effect Transistor)采用带带隧穿(BTBT)新导通机制，是一种非常有发展潜力的适于系统集成应用发展的新型低功耗器件。TFET通过栅电极控制源端与沟道交界面处隧穿结的隧穿宽度，使得源端价带电子隧穿到沟道导带(或沟道价带电子隧穿到源端导带)形成隧穿电流。这种新型导通机制突破传统MOSFET亚阈值斜率理论极限中热电势kT/q的限制，可以实现低于60mV/dec的超陡亚阈值斜率，降低器件静态漏泄电流进而降低器件静态功耗。Since the birth of integrated circuits, microelectronics integration technology has been developing continuously in accordance with "Moore's Law", and the size of semiconductor devices has been continuously reduced. As semiconductor devices enter the deep submicron range, traditional MOSFET devices are limited by the conduction mechanism of self-diffusion drift, and the subthreshold slope is limited by the thermoelectric potential kT/q, which cannot be reduced synchronously with the reduction of device size. As a result, the reduction of leakage current of MOSFET devices cannot meet the requirements of device size reduction, the energy consumption of the entire chip continues to rise, and the power consumption density of the chip increases sharply, which seriously hinders the development of chip system integration. In order to adapt to the development trend of integrated circuits, the development and research work of new ultra-low power consumption devices is particularly important. Tunneling Field-Effect Transistor (TFET, Tunneling Field-Effect Transistor) adopts a new conduction mechanism of band-band tunneling (BTBT), and is a new type of low-power device with great development potential suitable for the development of system integration applications. The TFET controls the tunneling width of the tunneling junction at the interface between the source and the channel through the gate electrode, so that the source valence band electrons tunnel to the channel conduction band (or the channel valence band electrons tunnel to the source conduction band) to form tunneling current. This new conduction mechanism breaks through the limitation of thermoelectric potential kT/q in the theoretical limit of the traditional MOSFET subthreshold slope, and can achieve an ultra-steep subthreshold slope lower than 60mV/dec, reducing the static leakage current of the device and thereby reducing the static power consumption of the device.

但是，由于半导体带带隧穿效率偏低，TFET的开态电流与传统MOSFET相比比较低，不能满足系统集成应用中的要求。因此，保持较陡直的亚阈值斜率的同时，提高TFET开态电流是TFET器件应用中需要解决的一个非常重要的问题。However, due to the low tunneling efficiency of semiconductor bands, the on-state current of TFETs is lower than that of traditional MOSFETs, which cannot meet the requirements of system integration applications. Therefore, it is a very important problem to be solved in the application of TFET devices to improve the on-state current of TFET while maintaining a relatively steep sub-threshold slope.

另外，TFET输出特性与传统MOSFET完全不同，输出电流随漏端电压增大而增大，是通过漏端电压降在源端隧穿结处，有效地改变隧穿结隧穿宽度从而使输出隧穿电流增大实现的。由于输出隧穿电流值与隧穿宽度λ成e指数关系，漏端电压与输出隧穿电流呈现一种超e指数关系。因而TFET输出特性曲线前段是一种超e指数的非线性曲线，即输出特性的非线性开启现象，导致器件沟道电导非常小，在电路应用中的输出电阻相当大。TFET的这种输出特性非常不利于器件的电路应用，因此改善TFET输出特性也是TFET电路应用中一个非常重要的问题。In addition, the output characteristics of TFET are completely different from those of traditional MOSFETs. The output current increases with the increase of the drain voltage. It is through the drain voltage drop at the source tunneling junction, effectively changing the tunneling width of the tunneling junction so that the output tunneling The increase in the through current is achieved. Since the output tunneling current value has an e-exponential relationship with the tunneling width λ, the drain terminal voltage and the output tunneling current exhibit a super-e-exponential relationship. Therefore, the front part of the TFET output characteristic curve is a nonlinear curve exceeding the e-exponent, that is, the nonlinear turn-on phenomenon of the output characteristic, resulting in a very small device channel conductance, and a relatively large output resistance in circuit applications. This output characteristic of TFET is very unfavorable to the circuit application of the device, so improving the output characteristic of TFET is also a very important issue in the circuit application of TFET.

发明内容Contents of the invention

本发明的目的在于提供一种抑制输出非线性开启的隧穿场效应晶体管及制备方法。该隧穿场效应晶体管可以有效抑制器件输出特性中的非线性开启现象，并保持了较陡直的亚阈值斜率。The object of the present invention is to provide a tunneling field effect transistor capable of suppressing output nonlinear turn-on and a preparation method thereof. The tunneling field effect transistor can effectively suppress the nonlinear turn-on phenomenon in the output characteristics of the device, and maintain a relatively steep subthreshold slope.

本发明提供的技术方案如下：The technical scheme provided by the invention is as follows:

一种抑制输出非线性开启的隧穿场效应晶体管，如图1所示，包括隧穿源区5，沟道区6，漏区9，半导体衬底区1，位于沟道区上方的栅介质层7，以及位于栅介质层之上的控制栅8，其特征是，所述的沟道区6位于隧穿源区5上方且位置与隧穿源区5部分重叠，在沟道区6与隧穿源区5界面处形成隧穿结；所述漏区9与沟道区6平行，位于沟道区6的另一侧(非隧穿源区一侧)；所述控制栅8位于沟道区6与隧穿源区5重叠部分的上方，而在靠近漏区9附近的沟道区6存在一个没有控制栅覆盖的区域；并且，所述沟道区6选用能态密度低于1E18cm^-3的半导体材料。A tunneling field effect transistor that suppresses output nonlinear turn-on, as shown in Figure 1, includes a tunneling source region 5, a channel region 6, a drain region 9, a semiconductor substrate region 1, and a gate dielectric located above the channel region Layer 7, and the control gate 8 located on the gate dielectric layer, characterized in that the channel region 6 is located above the tunneling source region 5 and partially overlaps with the tunneling source region 5, between the channel region 6 and A tunnel junction is formed at the interface of the tunneling source region 5; the drain region 9 is parallel to the channel region 6 and is located on the other side of the channel region 6 (the side of the non-tunneling source region); the control gate 8 is located in the channel region 6 Above the overlapping part of the channel region 6 and the tunneling source region 5, there is an area not covered by the control gate in the channel region 6 near the drain region 9; and, the energy state density of the channel region 6 is selected to be lower than 1E18cm ^-3 semiconductor materials.

对于N型器件来说，隧穿源区为P型重掺杂，其掺杂浓度约为1E20cm^-3-1E21cm^-3，漏区为N型重掺杂，其掺杂浓度约为1E18cm^-3-1E19cm^-3，沟道区为P型轻掺杂，其掺杂浓度约为1E13cm^-3-1E15cm^-3；而对于P型器件来说，隧穿源区为N型重掺杂，其掺杂浓度约为1E20cm^-3-1E21cm^-3，漏区为P型重掺杂，其掺杂浓度约为1E18cm^-3-1E19cm^-3，沟道区为N型轻掺杂，其掺杂浓度约为1E13cm^-3-1E15cm^-3。For N-type devices, the tunneling source region is heavily doped with P type, and its doping concentration is about 1E20cm ^-3 -1E21cm ^-3 , and the drain region is heavily doped with N type, and its doping concentration is about 1E18cm ^-3 -1E19cm ^-3 , the channel region is P-type lightly doped, and its doping concentration is about 1E13cm ^-3 -1E15cm ^-3 ; for P-type devices, the tunneling source region is N-type heavily doped, its doping The impurity concentration is about 1E20cm ^-3 -1E21cm ^-3 , the drain region is P-type heavily doped, its doping concentration is about 1E18cm ^-3 -1E19cm ^-3 , the channel region is N-type lightly doped, its doping concentration is about 1E13cm ^-3 -1E15cm ^-3 .

所述的隧穿场效应晶体管可以应用于Si，或Ge，也可以应用于其他II-VI，III-V和IV-IV族的二元或三元化合物半导体材料、或绝缘体上的硅(SOI)或绝缘体上的锗(GOI)。The tunneling field effect transistor can be applied to Si, or Ge, and can also be applied to other binary or ternary compound semiconductor materials of II-VI, III-V and IV-IV groups, or silicon on insulator (SOI ) or germanium on insulator (GOI).

本发明同时提供所述的抑制输出非线性开启的隧穿场效应晶体管的制备方法，包括以下步骤：The present invention also provides the preparation method of the tunneling field effect transistor that suppresses output nonlinear turn-on, comprising the following steps:

1)衬底准备：轻掺杂或未掺杂的半导体衬底；1) Substrate preparation: lightly doped or undoped semiconductor substrate;

2)在衬底上初始热氧化并淀积一层氮化物；2) initial thermal oxidation and deposition of a layer of nitride on the substrate;

3)光刻后进行浅沟槽隔离(Shallow Trench Isolation，STI)，并淀积隔离材料填充深孔后进行化学机械平坦化(Chemical Mechanical Polishing，CMP)；3) Perform shallow trench isolation (Shallow Trench Isolation, STI) after photolithography, and deposit isolation material to fill the deep hole, then perform chemical mechanical polishing (CMP);

4)光刻暴露出隧穿源区，以光刻胶为掩膜，进行离子注入形成隧穿源区，浓度约为1E20cm^-3-1E21cm^-3；4) Expose the tunneling source region by photolithography, and use the photoresist as a mask to perform ion implantation to form the tunneling source region, with a concentration of about 1E20cm ^- 3-1E21cm ^-3 ;

5)淀积具有低能态密度(能态密度低于1E18cm^-3)的异质半导体层；5) Depositing a heterogeneous semiconductor layer with a low energy state density (energy state density lower than 1E18cm ^-3 );

6)淀积栅介质材料和栅材料，进行光刻和刻蚀，形成栅图形；6) Deposit gate dielectric material and gate material, perform photolithography and etching, and form a gate pattern;

7)再次进行光刻，刻蚀沟道区图形；7) Perform photolithography again to etch the pattern of the channel region;

8)光刻暴露出漏区，以光刻胶为掩膜，进行离子注入形成漏区，浓度约为1E18cm^-3-1E19cm^-3；8) Exposing the drain region by photolithography, using the photoresist as a mask, performing ion implantation to form the drain region, the concentration is about 1E18cm ^- 3-1E19cm ^-3 ;

9)快速高温退火激活杂质；9) Rapid high-temperature annealing to activate impurities;

10)最后进入同CMOS一致的后道工序，包括淀积钝化层、开接触孔以及金属化等，即可制得抑制输出非线性开启的隧穿场效应晶体管。10) Finally, enter the post-processing process consistent with CMOS, including depositing a passivation layer, opening a contact hole, and metallization, etc., to produce a tunneling field effect transistor that suppresses the nonlinear turn-on of the output.

所述的制备方法，其特征是，步骤1)中所述的轻掺杂，其掺杂浓度约为1E13cm^-3-1E15cm^-3。The preparation method is characterized in that the light doping described in step 1) has a doping concentration of about 1E13cm ^-3 -1E15cm ^-3 .

所述的制备方法，其特征是，步骤1)中所述的半导体衬底材料选自Si、或Ge，或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅(SOI)或绝缘体上的锗(GOI)。The preparation method is characterized in that the semiconductor substrate material described in step 1) is selected from Si or Ge, or other binary or ternary compound semiconductors of II-VI, III-V and IV-IV groups , silicon on insulator (SOI) or germanium on insulator (GOI).

所述的制备方法，其特征是，步骤5)中所述的异质半导体层材料选自具有低能态密度的II-VI，III-V和IV-IV族的二元或三元化合物半导体。The preparation method is characterized in that the material of the heterogeneous semiconductor layer in step 5) is selected from binary or ternary compound semiconductors of groups II-VI, III-V and IV-IV with low energy state density.

所述的制备方法，其特征是，步骤6)中所述的栅介质材料选自SiO₂、Si₃N₄或高K栅(介电常数K>3.9)介质材料。The preparation method is characterized in that the gate dielectric material in step 6) is selected from SiO ₂ , Si ₃ N ₄ or high-K gate (dielectric constant K>3.9) dielectric materials.

所述的制备方法，其特征是，步骤6)中所述的淀积栅介质材料的方法选自下列方法之一：化学气相淀积或物理气相淀积。The preparation method is characterized in that the method for depositing the gate dielectric material in step 6) is selected from one of the following methods: chemical vapor deposition or physical vapor deposition.

所述的制备方法，其特征是，步骤6)中所述的栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。The preparation method is characterized in that the gate material in step 6) is selected from doped polysilicon, metal cobalt, nickel and other metals or metal silicides.

本发明的技术效果(以N型器件为例)：Technical effect of the present invention (taking N-type device as example):

1、控制栅位于沟道区及源区上方，栅电极加正电压，沟道区能带下拉，当沟道区导带下拉至隧穿源区价带以下时形成隧穿窗口，在隧穿结处发生垂直于控制栅的带带隧穿，器件开启，从而获得较陡直的亚阈值斜率。1. The control gate is located above the channel region and the source region. A positive voltage is applied to the gate electrode, and the energy band of the channel region is pulled down. When the conduction band of the channel region is pulled down below the valence band of the tunneling source region, a tunneling window is formed. Band-to-band tunneling perpendicular to the control gate occurs at the junction, and the device turns on, resulting in a steeper subthreshold slope.

2、在栅电压足够大的开态条件下，由于沟道区采用的是具有低能态密度的半导体材料，沟道表面能带弯曲达到饱和时，可以使沟道区导带弯曲至沟道区费米能级下方。2. Under the open condition with a sufficiently large gate voltage, since the channel region is made of a semiconductor material with a low energy state density, when the channel surface energy band bending reaches saturation, the conduction band of the channel region can be bent to the channel region below the Fermi level.

3、进一步的，在栅电压较大漏电压为零时，由于沟道区导带位于沟道区费米能级下方，即沟道区导带位于隧穿源区价带下方(隧穿源区重掺杂，源区价带位于费米能级上方)，使得漏电压为零时，在隧穿结处即形成隧穿窗口，显著增大了漏电压较小时的沟道电导，从而有效抑制了器件输出特性中的非线性开启现象。3. Furthermore, when the gate voltage is relatively large and the drain voltage is zero, since the conduction band of the channel region is located below the Fermi level of the channel region, that is, the conduction band of the channel region is located below the valence band of the tunneling source region (tunneling source region is heavily doped, and the valence band of the source region is located above the Fermi level), so that when the drain voltage is zero, a tunneling window is formed at the tunnel junction, which significantly increases the channel conductance when the drain voltage is small, thus effectively The non-linear turn-on phenomenon in the output characteristics of the device is suppressed.

与现有的TFET相比，抑制输出非线性开启的隧穿场效应晶体管通过器件结构设计，显著改善了器件输出特性，同时保持了陡直的亚阈值斜率。Compared with the existing TFET, the tunneling field-effect transistor that suppresses the output nonlinear turn-on can significantly improve the output characteristics of the device through the design of the device structure, while maintaining a steep subthreshold slope.

本发明的抑制输出非线性开启的隧穿场效应晶体管制备工艺简单，制备方法与标准的CMOS IC工艺兼容，能有效地在CMOS集成电路中集成TFET器件，还可以利用标准工艺制备由TFET组成的低功耗集成电路，极大地降低了生产成本，简化了工艺流程。The preparation process of the tunneling field-effect transistor that suppresses output nonlinear turn-on of the present invention is simple, the preparation method is compatible with the standard CMOS IC process, can effectively integrate TFET devices in the CMOS integrated circuit, and can also use standard processes to prepare TFETs. Low-power integrated circuits greatly reduce production costs and simplify the process flow.

附图说明Description of drawings

图1为本发明抑制输出非线性开启的隧穿场效应晶体管的结构示意图。FIG. 1 is a schematic structural diagram of a tunneling field effect transistor for suppressing output nonlinear turn-on according to the present invention.

图2为在半导体衬底上形成STI隔离后去除氮化物后的器件剖面图；2 is a cross-sectional view of the device after the nitride is removed after the STI isolation is formed on the semiconductor substrate;

图3为光刻暴露出TFET器件的隧穿源区并离子注入形成隧穿源区后的器件剖面图；Fig. 3 is a cross-sectional view of the device after photolithography exposes the tunneling source region of the TFET device and forms the tunneling source region by ion implantation;

图4为淀积一层具有低能带密度的异质半导体层后的器件剖面图；Figure 4 is a cross-sectional view of the device after depositing a heterogeneous semiconductor layer with a low energy band density;

图5为光刻并刻蚀形成控制栅后的器件剖面图；5 is a cross-sectional view of the device after photolithography and etching to form the control gate;

图6为光刻并刻蚀沟道区图形后的器件剖面图；Figure 6 is a cross-sectional view of the device after photolithography and etching of the channel region pattern;

图7为光刻暴露出TFET器件的漏区并离子注入形成漏区后的器件剖面图。FIG. 7 is a cross-sectional view of the device after photolithography exposes the drain region of the TFET device and forms the drain region by ion implantation.

图中，In the figure,

1-半导体衬底；2-STI隔离；3-氧化层；4-光刻胶；5-隧穿源区；6-沟道区；1-semiconductor substrate; 2-STI isolation; 3-oxide layer; 4-photoresist; 5-tunneling source region; 6-channel region;

7-高k介质层；8-控制栅；9-漏区；10-后道工序的钝化层；11-后道工序的金属。7-high-k dielectric layer; 8-control gate; 9-drain region; 10-passivation layer of subsequent process; 11-metal of subsequent process.

具体实施方式detailed description

以下结合附图，通过具体的实施例对本发明所述的抑制输出非线性开启的隧穿场效应晶体管的实施方法做进一步的说明。The implementation method of the tunneling field effect transistor for suppressing output nonlinear turn-on according to the present invention will be further described through specific embodiments below in conjunction with the accompanying drawings.

具体实施步骤如图1-图7所示：(本例以N型器件为例，P型器件可以以此类推)The specific implementation steps are shown in Figure 1-Figure 7: (This example takes N-type devices as an example, and P-type devices can be deduced by analogy)

1、在衬底掺杂浓度为轻掺杂(约1E13cm^-3-1E15cm^-3)的，晶向为<001>的Si衬底1上初始热氧化一层二氧化硅3，厚度约10nm，并淀积一层氮化硅(Si₃N₄)，厚度约100nm，之后采用浅槽隔离技术制作有源区STI隔离2，然后进行CMP，如图2所示；1. Initially thermally oxidize a layer of silicon dioxide 3 on a Si substrate 1 with a substrate doping concentration of lightly doped (about 1E13cm ^-3 -1E15cm ^-3 ) and a crystal orientation of <001>, with a thickness of about 10nm, And deposit a layer of silicon nitride (Si ₃ N ₄ ) with a thickness of about 100nm, and then use shallow trench isolation technology to make STI isolation 2 in the active area, and then perform CMP, as shown in Figure 2;

2、光刻暴露出隧穿源区5，以光刻胶4为掩膜，进行隧穿源区8离子注入(BF₂，1E16/cm^-2，20keV)，如图3所示；2. The tunneling source region 5 is exposed by photolithography, and the tunneling source region 8 is implanted with ions (BF ₂ , 1E16/cm ⁻² , 20keV) using the photoresist 4 as a mask, as shown in FIG. 3 ;

3、漂去表面初始生长的二氧化硅，采用LPCVD淀积一层具有低能态密度的异质半导体层6为InAs，厚度为6-15nm，如图4所示；3. Float away the silicon dioxide initially grown on the surface, and deposit a layer of heterogeneous semiconductor layer 6 with low energy state density by LPCVD, which is InAs with a thickness of 6-15nm, as shown in Figure 4;

4、然后淀积一层高k栅介质层7，栅介质层为Al₂O₃，厚度为1～5nm；采用LPCVD淀积控制栅8，栅材料为掺杂多晶硅层，厚度为50～200nm。光刻出栅图形，刻蚀控制栅图形，如图5所示；4. Then deposit a layer of high-k gate dielectric layer 7, the gate dielectric layer is Al ₂ O ₃ , with a thickness of 1-5 nm; use LPCVD to deposit the control gate 8, and the gate material is a doped polysilicon layer, with a thickness of 50-200 nm . Lithographically etching out the gate pattern, etching the control gate pattern, as shown in Figure 5;

5、光刻并刻蚀沟道区6图形，如图6所示；5. Photolithography and etching of the channel region 6 pattern, as shown in Figure 6;

6、光刻暴露出漏区9，以光刻胶4为掩膜，进行漏区9离子注入(As，1E14/cm^-2，30keV)，如图7所示。进行一次快速高温退火，对注入杂质进行激活(1050℃，10s)6. The drain region 9 is exposed by photolithography, and the drain region 9 is implanted with ions (As, 1E14/cm ⁻² , 30keV) using the photoresist 4 as a mask, as shown in FIG. 7 . Perform a rapid high-temperature annealing to activate the implanted impurities (1050°C, 10s)

7、最后进入常规后道工序，包括淀积钝化层10、开接触孔、以及金属化11等，图1所示为制得的所述基于标准CMOS IC工艺制备的N型的抑制输出非线性开启的隧穿场效应晶体管结构示意图。7. Finally, enter the conventional subsequent process, including depositing a passivation layer 10, opening a contact hole, and metallization 11, etc. FIG. 1 shows the N-type suppressed output non- Schematic diagram of the structure of a linearly turned-on tunneling field-effect transistor.

虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.