CN104752497B - A kind of super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor and preparation method - Google Patents

本发明提供了一种超陡平均亚阈摆幅隧穿场效应晶体管及制备方法，属于CMOS超大规模集成电路(ULSI)中场效应晶体管逻辑器件领域。该隧穿场效应晶体管的隧穿源区为多层结构，不同层为禁带宽度连续变化的半导体，且禁带宽度沿垂直器件表面方向逐渐增大，其中最下层禁带宽度最小，最上层禁带宽度最大，中间各层禁带宽度连续变化。本发明可以有效抑制器件转移特性中亚阈斜率退化现象，同时显著降低隧穿场效应晶体管的平均亚阈斜率，并保持了较陡直的最小亚阈斜率。

The invention provides an ultra-steep average subthreshold swing tunneling field-effect transistor and a preparation method thereof, which belong to the field of CMOS ultra-large-scale integrated circuit (ULSI) field-effect transistor logic devices. The tunneling source region of the tunneling field effect transistor is a multi-layer structure, and different layers are semiconductors with continuously changing bandgap widths, and the bandgap widths gradually increase along the direction perpendicular to the device surface, wherein the lowest layer has the smallest bandgap width, and the uppermost layer The band gap is the largest, and the band gap of each layer in the middle changes continuously. The invention can effectively suppress the degradation phenomenon of the subthreshold slope in the transfer characteristic of the device, and at the same time significantly reduce the average subthreshold slope of the tunneling field effect transistor, and maintain a relatively steep minimum subthreshold slope.

一种超陡平均亚阈摆幅隧穿场效应晶体管及制备方法An ultra-steep average subthreshold swing tunneling field effect transistor and its preparation method

技术领域technical field

本发明属于CMOS超大规模集成电路(ULSI)中场效应晶体管逻辑器件领域，具体涉及一种多层源结构超陡平均亚阈摆幅隧穿场效应晶体管及其制备方法。The invention belongs to the field of CMOS ultra-large scale integrated circuit (ULSI) field-effect transistor logic devices, and in particular relates to a multi-layer source structure ultra-steep average sub-threshold swing tunneling field-effect transistor and a preparation method thereof.

背景技术Background technique

自集成电路诞生以来，微电子集成技术一直按照“摩尔定律”不断发展，半导体器件尺寸不断缩小。随着半导体器件进入深亚微米范围，传统MOSFET器件由于受到自身扩散漂流的导通机制所限，亚阈值斜率受到热电势kT/q的限制而无法随着器件尺寸的缩小而同步减小。这就导致MOSFET器件泄漏电流缩小无法达到器件尺寸缩小的要求，整个芯片的能耗不断上升，芯片功耗密度急剧增大，严重阻碍了芯片系统集成的发展。为了适应集成电路的发展趋势，新型超低功耗器件的开发和研究工作就显得特别重要。隧穿场效应晶体管(TFET，Tunneling Field-Effect Transistor)采用带带隧穿(BTBT)新导通机制，是一种非常有发展潜力的适于系统集成应用发展的新型低功耗器件。TFET通过栅电极控制源端与沟道交界面处隧穿结的隧穿宽度，使得源端价带电子隧穿到沟道导带(或沟道价带电子隧穿到源端导带)形成隧穿电流。这种新型导通机制突破传统MOSFET亚阈值斜率理论极限中热电势kT/q的限制，可以实现低于60mV/dec的具有超陡亚阈值斜率，降低器件静态漏泄电流进而降低器件静态功耗。Since the birth of integrated circuits, microelectronics integration technology has been developing continuously in accordance with "Moore's Law", and the size of semiconductor devices has been continuously reduced. As semiconductor devices enter the deep submicron range, traditional MOSFET devices are limited by the conduction mechanism of self-diffusion drift, and the subthreshold slope is limited by the thermoelectric potential kT/q, which cannot be reduced synchronously with the reduction of device size. As a result, the reduction of leakage current of MOSFET devices cannot meet the requirements of device size reduction, the energy consumption of the entire chip continues to rise, and the power consumption density of the chip increases sharply, which seriously hinders the development of chip system integration. In order to adapt to the development trend of integrated circuits, the development and research work of new ultra-low power consumption devices is particularly important. Tunneling Field-Effect Transistor (TFET, Tunneling Field-Effect Transistor) adopts a new conduction mechanism of band-band tunneling (BTBT), and is a new type of low-power device with great development potential suitable for the development of system integration applications. The TFET controls the tunneling width of the tunneling junction at the interface between the source and the channel through the gate electrode, so that the source valence band electrons tunnel to the channel conduction band (or the channel valence band electrons tunnel to the source conduction band) to form tunneling current. This new conduction mechanism breaks through the limitation of thermoelectric potential kT/q in the theoretical limit of the traditional MOSFET subthreshold slope, and can achieve an ultra-steep subthreshold slope lower than 60mV/dec, reducing the static leakage current of the device and thereby reducing the static power consumption of the device.

但是，与传统MOSFET不同的是，TFET转移曲线的亚阈区内亚阈斜率是变化的，且随着栅电压增大而逐渐增大，这就导致TFET转移特性中，低于60mV/dec的亚阈斜率对应范围较小，器件的平均亚阈斜率较高，不利于TFET器件在超低功耗领域的应用。因此，保持较陡直的最小亚阈值斜率的同时，抑制亚阈斜率退化，实现超陡平均亚阈斜率是TFET器件应用中需要解决的一个非常重要的问题。However, unlike traditional MOSFETs, the subthreshold slope in the subthreshold region of the TFET transfer curve changes and gradually increases with the increase of the gate voltage, which leads to a TFET transfer characteristic lower than 60mV/dec The corresponding range of the subthreshold slope is small, and the average subthreshold slope of the device is relatively high, which is not conducive to the application of TFET devices in the field of ultra-low power consumption. Therefore, while maintaining a relatively steep minimum subthreshold slope, suppressing the degradation of the subthreshold slope and realizing an ultra-steep average subthreshold slope is a very important problem to be solved in the application of TFET devices.

发明内容Contents of the invention

本发明的目的在于提供一种多层源结构超陡平均亚阈摆幅隧穿场效应晶体管及制备方法。该隧穿场效应晶体管可以有效抑制器件转移特性中亚阈斜率退化现象，同时显著降低隧穿场效应晶体管的平均亚阈斜率，并保持了较陡直的最小亚阈斜率。The object of the present invention is to provide a multi-layer source structure ultra-steep average sub-threshold swing tunneling field effect transistor and a preparation method. The tunneling field effect transistor can effectively suppress the subthreshold slope degradation phenomenon in the transfer characteristics of the device, and at the same time significantly reduce the average subthreshold slope of the tunneling field effect transistor, and maintain a relatively steep minimum subthreshold slope.

本发明提供的技术方案如下：The technical scheme provided by the invention is as follows:

一种多层源结构超陡平均亚阈摆幅隧穿场效应晶体管，如图1所示，包括隧穿源区6，沟道区1，漏区7以及位于沟道上方的控制栅4，其特征是，所述的隧穿源区为多层结构(6-1、6-2、…6-n)，不同层为禁带宽度连续变化的半导体，且禁带宽度沿垂直器件(器件指的是所述的隧穿场效应晶体管)表面方向逐渐增大，其中最下层6-1禁带宽度最小，最上层6-2禁带宽度最大，中间各层禁带宽度连续变化。对于N型器件来说，隧穿源区为P型重掺杂，漏区为N型重掺杂，沟道区为P型轻掺杂；而对于P型器件来说，隧穿源区为N型重掺杂，漏区为P型重掺杂，沟道区为N型轻掺杂。A multi-layer source structure ultra-steep average subthreshold swing tunneling field effect transistor, as shown in Figure 1, includes a tunneling source region 6, a channel region 1, a drain region 7 and a control gate 4 located above the channel, It is characterized in that the tunneling source region is a multi-layer structure (6-1, 6-2, ... 6-n), and different layers are semiconductors with continuously changing bandgap width, and the bandgap width is along the vertical device (device Refers to the direction of the surface of the tunneling field effect transistor) gradually increasing, wherein the lowest layer 6-1 has the smallest band gap, the uppermost layer 6-2 has the largest band gap, and the band gaps of the middle layers change continuously. For N-type devices, the tunneling source region is heavily doped P-type, the drain region is heavily doped N-type, and the channel region is lightly doped P-type; while for P-type devices, the tunneling source region is N-type heavily doped, the drain region is P-type heavily doped, and the channel region is N-type lightly doped.

所述的隧穿场效应晶体管，其特征是，对于N型器件来说，隧穿源区为P型重掺杂，其掺杂浓度约为1E18cm^-3-1E20cm^-3，漏区为N型重掺杂，其掺杂浓度约为1E18cm^-3-1E19cm^-3，沟道区为P型轻掺杂，其掺杂浓度约为1E13cm^-3-1E15cm^-3；而对于P型器件来说，隧穿源区为N型重掺杂，其掺杂浓度约为1E18cm^-3-1E20cm^-3，漏区为P型重掺杂，其掺杂浓度约为1E18cm^-3-1E19cm^-3，沟道区为N型轻掺杂，其掺杂浓度约为1E13cm^-3-1E15cm^-3。The tunneling field effect transistor is characterized in that, for an N-type device, the tunneling source region is heavily doped with a P-type, and its doping concentration is about 1E18cm ^- 3-1E20cm ^-3 , and the drain region is an N-type Heavy doping, its doping concentration is about 1E18cm ^-3 -1E19cm ^-3 , the channel region is P-type lightly doped, its doping concentration is about 1E13cm ^-3 -1E15cm ^-3 ; and for P-type devices, The tunnel source region is N-type heavily doped, its doping concentration is about 1E18cm ^-3 -1E20cm ^-3 , the drain region is P-type heavily doped, its doping concentration is about 1E18cm ^-3 -1E19cm ^-3 , the channel The region is N-type lightly doped, and its doping concentration is about 1E13cm ^-3 -1E15cm ^-3 .

所述隧穿场效应晶体管中多层隧穿源区的禁带宽度沿垂直器件表面方向的变化梯度是器件设计的重要参数。禁带宽度变化梯度过小，导致最表面层材料禁带宽度过窄，将引起器件关态电流增大，最小亚阈值斜率增大。而禁带宽度变化梯度过大，导致最表面材料禁带宽度过大，导致开启带带隧穿所需栅电压过大。一般保证最表面层材料禁带宽度较最下层材料禁带宽度大0.3eV-0.7eV。且隧穿源区具有较宽禁带宽度部分(大于最下层禁带宽度约0.3eV以上的源区部分)结深度优化在5nm-20nm之间。The variation gradient of the forbidden band width of the multilayer tunneling source region in the tunneling field effect transistor along the direction perpendicular to the surface of the device is an important parameter for device design. If the change gradient of the forbidden band width is too small, the band gap of the material of the most surface layer will be too narrow, which will cause the off-state current of the device to increase and the slope of the minimum subthreshold value to increase. However, the change gradient of the bandgap width is too large, resulting in the excessively large bandgap of the material on the outermost surface, resulting in an excessively large gate voltage required to enable band-band tunneling. It is generally guaranteed that the band gap of the material on the outermost layer is 0.3eV-0.7eV larger than that of the material on the bottom layer. And the tunneling source region has a wider forbidden band width part (a source region part greater than the lowermost forbidden band width by about 0.3eV), and the junction depth is optimized between 5nm-20nm.

所述的隧穿场效应晶体管可以应用于SiGe半导体材料，也可以应用于其他II-VI，III-V和IV-IV族的二元或三元化合物半导体材料。The tunneling field effect transistor can be applied to SiGe semiconductor materials, and can also be applied to other binary or ternary compound semiconductor materials of II-VI, III-V and IV-IV groups.

本发明同时提供所述的多层源结构超陡平均亚阈摆幅隧穿场效应晶体管的制备方法，包括以下步骤：The present invention also provides a method for preparing the multi-layer source structure ultra-steep average subthreshold swing tunneling field-effect transistor, comprising the following steps:

1)衬底准备：轻掺杂(约1E13cm^-3-1E15cm^-3)或未掺杂的半导体衬底；1) Substrate preparation: lightly doped (about 1E13cm ^-3 -1E15cm ^-3 ) or undoped semiconductor substrate;

2)在衬底上初始热氧化并淀积一层氮化物，STI刻蚀，并淀积隔离材料填充深孔后CMP；2) Initial thermal oxidation and deposition of a layer of nitride on the substrate, STI etching, and deposition of isolation materials to fill the deep holes and then CMP;

3)重新生长栅介质材料，淀积栅材料，进行光刻和刻蚀，形成栅图形；3) Re-grow the gate dielectric material, deposit the gate material, perform photolithography and etching, and form the gate pattern;

4)淀积一层氧化物阻挡层，光刻暴露出源区并选择刻蚀出源区；4) Depositing an oxide barrier layer, exposing the source region by photolithography and selectively etching the source region;

5)采用分子束外延法选择生长原子数比沿垂直方向连续变化的源区化合物半导体，得到禁带宽度沿垂直方向连续变化的多层隧穿源区结构，同时对源区进行原位掺杂，浓度约为1E18cm^-3-1E20cm^-3，祛除氧化物阻挡层；5) Using molecular beam epitaxy to selectively grow source region compound semiconductors whose atomic number ratio continuously changes along the vertical direction to obtain a multi-layer tunneling source region structure with continuously changing bandgap width along the vertical direction, and at the same time perform in-situ doping on the source region , the concentration is about 1E18cm ^-3 -1E20cm ^-3 , to remove the oxide barrier layer;

6)光刻暴露出漏区，以光刻胶和栅为掩膜，进行离子注入形成漏区，浓度约为1E18cm^-3-1E19cm^-3；6) Exposing the drain region by photolithography, using the photoresist and the gate as a mask, performing ion implantation to form the drain region, the concentration is about 1E18cm ^- 3-1E19cm ^-3 ;

7)快速高温退火激活杂质；7) Rapid high-temperature annealing to activate impurities;

8)最后进入同CMOS一致的后道工序，包括淀积钝化层、开接触孔以及金属化等，即可制得多层源结构超陡平均亚阈摆幅隧穿场效应晶体管。8) Finally, it enters the subsequent process consistent with CMOS, including depositing a passivation layer, opening a contact hole, and metallization, etc., to manufacture a multi-layer source structure ultra-steep average sub-threshold swing tunneling field-effect transistor.

所述的制备方法，其特征是，步骤1)中所述的轻掺杂，其掺杂浓度约为1E13cm^-3-1E15cm^-3。The preparation method is characterized in that the light doping described in step 1) has a doping concentration of about 1E13cm ^-3 -1E15cm ^-3 .

所述的制备方法，其特征是，步骤1)中所述的半导体衬底材料选自Si、Ge或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅(SOI)或绝缘体上的锗(GOI)。The preparation method is characterized in that the semiconductor substrate material described in step 1) is selected from Si, Ge or other binary or ternary compound semiconductors and insulators of II-VI, III-V and IV-IV groups silicon-on-insulator (SOI) or germanium-on-insulator (GOI).

所述的制备方法，其特征是，步骤3)中所述的栅介质层材料选自SiO₂、Si₃N₄或高K栅介质材料。The preparation method is characterized in that the material of the gate dielectric layer in step 3) is selected from SiO ₂ , Si ₃ N ₄ or high-K gate dielectric materials.

所述的制备方法，其特征是，步骤3)中所述的生长栅介质材料的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积或物理气相淀积。The preparation method is characterized in that the method for growing the gate dielectric material in step 3) is selected from one of the following methods: conventional thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor deposition or physical vapor deposition.

所述的制备方法，其特征是，步骤3)中所述的栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。The preparation method is characterized in that the gate material in step 3) is selected from doped polysilicon, metal cobalt, nickel and other metals or metal silicides.

所述的制备方法，其特征是，步骤5)中所述的多层源区材料可选自原子数比不同的SiGe或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体。The preparation method is characterized in that the multi-layer source region materials described in step 5) can be selected from SiGe with different atomic number ratios or other binary or tertiary materials of II-VI, III-V and IV-IV groups. Elemental compound semiconductors.

本发明的技术效果(以N型器件为例)：Technical effect of the present invention (taking N-type device as example):

1、隧穿源区为多层结构，不同层为禁带宽度连续变化的半导体，且在沟道表面处具有较宽禁带宽度，在距离沟道表面一定距离处具有较窄禁带宽度。1. The tunneling source region has a multi-layer structure, and different layers are semiconductors with continuously changing bandgap widths, and have a wider bandgap width at the channel surface and a narrower bandgap width at a certain distance from the channel surface.

2、栅电极加正电压，沟道能带下拉，在隧穿结处发生带带隧穿，器件开启。在栅压较小时，主要是沟道表面处具有较宽禁带宽度的源区部分发生带带隧穿，从而可以获得较陡直的最小亚阈值摆幅。2. When a positive voltage is applied to the gate electrode, the energy band of the channel is pulled down, and band-band tunneling occurs at the tunneling junction, and the device is turned on. When the gate voltage is small, band tunneling mainly occurs in the source region with a wider forbidden band width at the channel surface, so that a steeper minimum subthreshold swing can be obtained.

3、随着栅压增大，距离沟道表面一定距离处的具有较窄禁带宽度的源区部分发生带带隧穿。且对于带带隧穿来说，窄禁带材料相对于宽禁带材料具有更大的隧穿几率，在相同栅电压增量条件下可以获得更大的带带隧穿电流增量，从而可以获得更陡直的平均亚阈斜率，有效抑制了器件亚阈斜率随栅电压增大而退化的现象。3. As the gate voltage increases, band tunneling occurs in the part of the source region with a narrower forbidden band width at a certain distance from the channel surface. And for bandgap tunneling, the narrow bandgap material has a greater tunneling probability than the wide bandgap material, and a larger bandgap tunneling current increment can be obtained under the same gate voltage increment condition, so that A steeper average subthreshold slope is obtained, which effectively suppresses the degradation of the subthreshold slope of the device as the gate voltage increases.

4、同时，由于在器件刚开启情况下具有较宽禁带宽度的源区部分起主导作用，有利于降低最小亚阈斜率，并且有效避免了窄禁带材料会导致的关态电流增大，最小亚阈斜率增大的现象。4. At the same time, since the source region with a wider bandgap width plays a dominant role when the device is just turned on, it is beneficial to reduce the minimum subthreshold slope and effectively avoid the increase in off-state current caused by narrow bandgap materials. The phenomenon of increased minimum subthreshold slope.

与现有的TFET相比，多层源结构超陡平均亚阈摆幅隧穿场效应晶体管通过器件结构设计，显著改善了器件转移特性，有效降低了器件的平均亚阈斜率，同时保持了陡直的最小亚阈斜率。Compared with the existing TFET, the multi-layer source structure ultra-steep average subthreshold swing tunneling field effect transistor has significantly improved the device transfer characteristics through the design of the device structure, effectively reducing the average subthreshold slope of the device while maintaining a steep Straight minimum subthreshold slope.

本发明的多层源结构超陡平均亚阈摆幅隧穿场效应晶体管制备工艺简单，制备方法完全基于标准的CMOS IC工艺，能有效地在CMOS集成电路中集成TFET器件，还可以利用标准工艺制备由TFET组成的低功耗集成电路，极大地降低了生产成本，简化了工艺流程。The multi-layer source structure ultra-steep average sub-threshold swing tunneling field-effect transistor of the present invention has a simple preparation process, and the preparation method is completely based on the standard CMOS IC process, which can effectively integrate TFET devices in the CMOS integrated circuit, and can also use the standard process The preparation of low-power integrated circuits composed of TFETs greatly reduces production costs and simplifies the process flow.

附图说明Description of drawings

图1为本发明多层源结构超陡平均亚阈摆幅隧穿场效应晶体管的结构示意图。FIG. 1 is a schematic structural diagram of a tunneling field effect transistor with a multi-layer source structure and an ultra-steep average subthreshold swing of the present invention.

图2在半导体衬底上形成STI隔离后去除氮化物后的器件剖面图；Figure 2 is a cross-sectional view of the device after the nitride is removed after the STI isolation is formed on the semiconductor substrate;

图3为光刻并刻蚀形成栅后的器件剖面图；3 is a cross-sectional view of the device after photolithography and etching to form the gate;

图4为光刻暴露出TFET器件的源区并刻蚀出源区后器件剖面图；4 is a cross-sectional view of the device after photolithography exposes the source region of the TFET device and etches the source region;

图5为外延选择生长原子数比渐变的多层隧穿源区，且对隧穿源区进行原位掺杂后的器件剖面图；Fig. 5 is a cross-sectional view of a device after epitaxially selectively growing a multilayer tunneling source region with a gradual atomic number ratio and performing in-situ doping on the tunneling source region;

图6光刻暴露出TFET器件的漏区并离子注入形成漏区后的器件剖面图。FIG. 6 is a cross-sectional view of the device after photolithography exposes the drain region of the TFET device and ion implantation forms the drain region.

图中，1-半导体衬底(沟道区)；2-STI隔离；3-介质层；4-栅；5-光刻胶；6-多层隧穿源区(包括-最下层6-1，最上层6-n及中间各层)；7-漏区；8-后道工序的钝化层；9-后道工序的金属。Among the figure, 1-semiconductor substrate (channel region); 2-STI isolation; 3-dielectric layer; 4-gate; 5-photoresist; , the uppermost layer 6-n and the middle layers); 7-the drain region; 8-the passivation layer of the subsequent process; 9-the metal of the subsequent process.

具体实施方式Detailed ways

以下结合附图，通过具体的实施例对本发明所述的多层源结构超陡平均亚阈摆幅隧穿场效应晶体管的实施方法做进一步的说明。The implementation method of the ultra-steep average sub-threshold swing tunneling field-effect transistor with multi-layer source structure of the present invention will be further described through specific embodiments below in conjunction with the accompanying drawings.

具体实施步骤如图2-图7所示：(本例以N型器件为例，P型器件可以以此类推)The specific implementation steps are shown in Figure 2-Figure 7: (This example takes N-type devices as an example, and P-type devices can be deduced by analogy)

1、在衬底掺杂浓度为轻掺杂(约1E13cm^-3-1E15cm^-3)的，晶向为<001>的Si衬底1上初始热氧化一层二氧化硅，厚度约10nm，并淀积一层氮化硅(Si₃N₄)，厚度约100nm，之后采用浅槽隔离技术，淀积隔离材料填充深孔制作有源区STI隔离2，然后进行CMP，如图2所示。1. Initially thermally oxidize a layer of silicon dioxide on a Si substrate 1 with a substrate doping concentration of lightly doped (about 1E13cm ^-3 -1E15cm ^-3 ) and a crystal orientation of <001>, with a thickness of about 10nm, and Deposit a layer of silicon nitride (Si ₃ N ₄ ) with a thickness of about 100nm, and then use shallow trench isolation technology to deposit isolation materials to fill deep holes to make active region STI isolation 2, and then perform CMP, as shown in Figure 2.

2、漂去表面初始生长的二氧化硅，然后热生长一层栅介质层3，栅介质层为SiO₂，厚度为1～5nm；采用LPCVD淀积栅材料4，栅材料为掺杂多晶硅层，厚度为50～200nm。光刻出栅图形，刻蚀栅材料4直到栅介质层3，如图3所示。2. Float away the silicon dioxide initially grown on the surface, and then thermally grow a gate dielectric layer 3, the gate dielectric layer is SiO ₂ , with a thickness of 1-5nm; use LPCVD to deposit the gate material 4, and the gate material is a doped polysilicon layer , the thickness is 50-200nm. The gate pattern is photolithographically etched, and the gate material 4 is etched until the gate dielectric layer 3 , as shown in FIG. 3 .

3、淀积一层SiO₂阻挡层，厚度约10nm，光刻暴露出源区，采用高选择比干法刻蚀出隧穿源区，结深约50nm，如图-4所示。3. Deposit a layer of SiO ₂ barrier layer with a thickness of about 10nm. The source region is exposed by photolithography, and the tunnel source region is etched by a high selective dry method. The junction depth is about 50nm, as shown in Figure-4.

4、采用分子束外延法选择生长沿垂直器件表面方向原子数比连续变化的Si_1-xGe_x化合物半导体形成多层源区6(其中6-1层中x＝1，6-n层中原子数比0<x<0.5，中间各层越接近器件表面原子数比x值越小)，同时对源区进行原位掺杂(杂质浓度约1E20cm^-3)，如图5所示。4. Using molecular beam epitaxy to selectively grow Si _1-x Ge _x compound semiconductors whose atomic number ratio continuously changes along the direction vertical to the device surface to form a multilayer source region 6 (where x=1 in the 6-1 layer, and x=1 in the 6-n layer Atomic number ratio 0<x<0.5, the closer the middle layers are to the surface of the device, the smaller the atomic number ratio x value), and in-situ doping is performed on the source region (the impurity concentration is about 1E20cm ^-3 ), as shown in Figure 5.

5、祛除氧化物阻挡层，光刻暴露出漏区，以光刻胶5和栅4为掩膜，进行漏区7离子注入(杂质浓度约1E18cm^-3)，如图6所示。5. Remove the oxide barrier layer, expose the drain region by photolithography, and use the photoresist 5 and the gate 4 as a mask to perform ion implantation in the drain region 7 (the impurity concentration is about 1E18cm ⁻³ ), as shown in FIG. 6 .

6、进行一次快速高温退火，并对注入杂质进行激活(1050℃,10s)。最后进入常规后道工序，包括淀积钝化层8、开接触孔、以及金属化9等。6. Perform a rapid high-temperature annealing and activate the implanted impurities (1050°C, 10s). Finally, it enters the conventional subsequent process, including depositing a passivation layer 8, opening a contact hole, and metallization 9, etc.

图1所示为制得的所述基于标准CMOS IC工艺制备的N型的多层源结构超陡平均亚阈摆幅隧穿场效应晶体管结构示意图。FIG. 1 is a schematic diagram showing the structure of the N-type multi-layer source structure ultra-steep average subthreshold swing tunneling field effect transistor prepared based on the standard CMOS IC process.

虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.