CN105575440B - error processing method, memory storage device and memory control circuit unit - Google Patents

本发明涉及一种用于可复写式非挥发性存储器模块的错误处理方法、存储器储存装置及存储器控制电路单元，此可复写式非挥发性存储器模块包括多个存储元，此错误处理方法包括：发送第一读取指令序列以从所述存储元中读取多个位元；对所述位元执行第一解码；如果所述位元具有至少一个错误，则判断每一所述错误是属于第一类错误或第二类错误；如果所述错误中的第一错误是属于第一类错误，则记录下第一错误的相关信息；以及如果第一错误是属于第二类错误，则不记录第一错误的相关信息。由此，可针对特定类型的错误进行适当的处理。

The present invention relates to an error handling method for a rewritable non-volatile memory module, a memory storage device and a memory control circuit unit. The rewritable non-volatile memory module includes a plurality of memory cells. The error handling method includes: sending a first read instruction sequence to read a plurality of bits from the memory cells; performing a first decoding on the bits; if the bits have at least one error, determining whether each of the errors belongs to a first type of error or a second type of error; if the first error among the errors belongs to a first type of error, recording relevant information of the first error; and if the first error belongs to a second type of error, not recording relevant information of the first error. Thus, appropriate handling can be performed for specific types of errors.

错误处理方法、存储器储存装置及存储器控制电路单元Error handling method, memory storage device and memory control circuit unit

技术领域technical field

本发明涉及一种错误处理方法，且特别是涉及一种用于可复写式非挥发性存储器模块的错误处理方法、存储器储存装置及存储器控制电路单元。The invention relates to an error handling method, and in particular to an error handling method for a rewritable non-volatile memory module, a memory storage device and a memory control circuit unit.

背景技术Background technique

数码相机、移动电话与MP3播放器在这几年来的发展十分迅速，使得消费者对储存媒体的需求也急速增加。由于可复写式非挥发性存储器模块(例如，闪存)具有数据非挥发性、省电、体积小，以及无机械结构等特性，所以非常适合内建于上述所举例的各种可携式多媒体装置中。The rapid development of digital cameras, mobile phones and MP3 players in recent years has led to a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in various portable multimedia devices listed above middle.

一般来说，错误检查与校正电路会被配置在存储器控制器中。此错误检查与校正电路用以对从可复写式非挥发性存储器模块中读取出的数据进行错误检查与更正。然而，基于现有的错误检查与校正机制，某些特定类型的错误(例如，数据在总线上传输引起的错误)不容易被找到。Generally, the error checking and correction circuit will be configured in the memory controller. The error checking and correcting circuit is used for error checking and correcting the data read from the rewritable non-volatile memory module. However, certain types of errors (eg, errors caused by data transmission on the bus) are not easy to find based on existing error checking and correction mechanisms.

发明内容Contents of the invention

本发明提供一种错误处理方法、存储器储存装置及存储器控制电路单元，可辨识出特定类型的错误，并记录下相关信息供进一步使用。The invention provides an error handling method, a memory storage device and a memory control circuit unit, which can identify specific types of errors and record related information for further use.

本发明的一实施例提供一种错误处理方法，其用于可复写式非挥发性存储器模块，此可复写式非挥发性存储器模块包括多个存储元，所述错误处理方法包括：发送第一读取指令序列，其中第一读取指令序列用以从所述存储元中读取多个位元；对所述位元执行第一解码；如果所述位元具有至少一个错误，则更正所述错误，并判断每一所述错误是属于第一类错误或第二类错误；如果所述错误中的第一错误是属于第一类错误，则记录下第一错误的相关信息；以及如果第一错误是属于第二类错误，则不记录第一错误的相关信息。An embodiment of the present invention provides an error handling method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of storage elements. The error handling method includes: sending a first A sequence of read instructions, wherein a first sequence of read instructions is used to read a plurality of bits from the storage element; perform a first decode on the bits; and correct the bits if the bits have at least one error the above errors, and judge whether each of the errors belongs to the first type of error or the second type of error; if the first error in the errors belongs to the first type of error, then record the relevant information of the first error; and if If the first error belongs to the second type of error, the relevant information of the first error will not be recorded.

在本发明的一实施例中，所述判断每一所述错误是属于第一类错误或第二类错误的步骤包括：取得第一错误在所述位元中对应的错误位元的通道可靠度信息；判断通道可靠度信息的值是否大于可靠度阈值；如果通道可靠度信息的值大于可靠度阈值，则判定第一错误是属于第一类错误；以及如果通道可靠度信息的值没有大于可靠度阈值，则判定第一错误是属于第二类错误。In an embodiment of the present invention, the step of judging whether each error belongs to the first type of error or the second type of error includes: obtaining the channel reliability of the error bit corresponding to the first error in the bit degree information; determine whether the value of the channel reliability information is greater than the reliability threshold; if the value of the channel reliability information is greater than the reliability threshold, then determine that the first error belongs to the first type of error; and if the value of the channel reliability information is not greater than reliability threshold, it is determined that the first error belongs to the second type of error.

在本发明的一实施例中，所述判断每一所述错误是属于第一类错误或第二类错误的步骤包括：辨识出第一错误在所述存储元中对应的第一存储元；判断从第一存储元中读取的参考位元是否是第一值，其中第一错误在所述位元中对应的错误位元不是参考位元；如果参考位元是第一值，则判定第一错误是属于第一类错误；以及如果参考位元不是第一值，则判定第一错误是属于第二类错误。In an embodiment of the present invention, the step of judging whether each error belongs to the first type of error or the second type of error includes: identifying the first storage element corresponding to the first error among the storage elements; Judging whether the reference bit read from the first storage element is the first value, wherein the error bit corresponding to the first error in the bit is not the reference bit; if the reference bit is the first value, then determine The first error belongs to the first type of error; and if the reference bit is not the first value, it is determined that the first error belongs to the second type of error.

在本发明的一实施例中，所述存储元属于下实体程序化单元且属于上实体程序化单元，错误位元是对应至下实体程序化单元，并且参考位元是对应至上实体程序化单元。In an embodiment of the present invention, the storage element belongs to the lower physical programming unit and belongs to the upper physical programming unit, the error bit corresponds to the lower physical programming unit, and the reference bit corresponds to the upper physical programming unit .

在本发明的一实施例中，所述错误处理方法还包括：发送第二读取指令序列，其中第二读取指令序列用以从所述存储元中读取所述位元；根据所记录的相关信息，更正所述位元；以及对更正后的所述位元执行第二解码。In an embodiment of the present invention, the error handling method further includes: sending a second read instruction sequence, wherein the second read instruction sequence is used to read the bit from the storage element; according to the recorded correcting the bits; and performing a second decoding on the corrected bits.

在本发明的一实施例中，所述错误处理方法还包括：累计所述位元中属于第一类错误的至少一个错误的总数；判断总数是否大于错误阈值；以及如果总数大于错误阈值，则发送写入指令序列，其中写入指令序列用以将更正后的所述位元写入至所述存储元。In an embodiment of the present invention, the error handling method further includes: accumulating the total number of at least one error belonging to the first type of error in the bit; judging whether the total number is greater than the error threshold; and if the total number is greater than the error threshold, then A write command sequence is sent, wherein the write command sequence is used to write the corrected bit into the storage element.

本发明的一实施例提供一种存储器储存装置，其包括连接接口单元、可复写式非挥发性存储器模块及存储器控制电路单元。连接接口单元用以电性连接至主机系统。可复写式非挥发性存储器模块包括多个存储元。存储器控制电路单元电性连接至连接接口单元与可复写式非挥发性存储器模块。其中存储器控制电路单元用以发送第一读取指令序列，其中第一读取指令序列用以从所述存储元中读取多个位元，存储器控制电路单元还用以对所述位元执行一第一解码，如果所述位元具有至少一个错误，则存储器控制电路单元还用以更正所述错误并判断每一所述错误是属于第一类错误或第二类错误，如果所述错误中的第一错误是属于第一类错误，则存储器控制电路单元还用以记录下第一错误的相关信息，以及如果第一错误是属于第二类错误，则存储器控制电路单元不记录第一错误的相关信息。An embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to electrically connect to the host system. The rewritable non-volatile memory module includes a plurality of storage elements. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. Wherein the memory control circuit unit is used to send the first read instruction sequence, wherein the first read instruction sequence is used to read a plurality of bits from the storage element, and the memory control circuit unit is also used to execute the A first decoding, if the bit has at least one error, the memory control circuit unit is also used to correct the error and judge whether each error belongs to the first type of error or the second type of error, if the error If the first error in the first error belongs to the first type of error, the memory control circuit unit is also used to record the relevant information of the first error, and if the first error belongs to the second type of error, the memory control circuit unit does not record the first error. Information about the error.

在本发明的一实施例中，所述存储器控制电路单元判断每一所述错误是属于第一类错误或第二类错误的操作包括：取得第一错误在所述位元中对应的错误位元的通道可靠度信息；判断通道可靠度信息的值是否大于可靠度阈值；如果通道可靠度信息的值大于可靠度阈值，则判定第一错误是属于第一类错误；以及如果通道可靠度信息的值没有大于可靠度阈值，则判定第一错误是属于第二类错误。In an embodiment of the present invention, the operation of the memory control circuit unit judging whether each error belongs to the first type of error or the second type of error includes: obtaining the error bit corresponding to the first error in the bit element channel reliability information; determine whether the value of the channel reliability information is greater than the reliability threshold; if the value of the channel reliability information is greater than the reliability threshold, then determine that the first error belongs to the first type of error; and if the channel reliability information If the value of is not greater than the reliability threshold, it is determined that the first error belongs to the second type of error.

在本发明的一实施例中，所述存储器控制电路单元判断每一所述错误是属于第一类错误或第二类错误的操作包括：辨识出第一错误在所述存储元中对应的第一存储元；判断从第一存储元中读取的参考位元是否是第一值，其中第一错误在所述位元中对应的错误位元不是参考位元；如果参考位元是第一值，则判定第一错误是属于第一类错误；以及如果参考位元不是第一值，则判定第一错误是属于第二类错误。In an embodiment of the present invention, the operation of the memory control circuit unit judging whether each error belongs to the first type of error or the second type of error includes: identifying the first error corresponding to the first error in the storage element A storage unit; judging whether the reference bit read from the first storage unit is the first value, wherein the error bit corresponding to the first error in the bit is not the reference bit; if the reference bit is the first value, it is determined that the first error belongs to the first type of error; and if the reference bit is not the first value, it is determined that the first error belongs to the second type of error.

在本发明的一实施例中，所述存储器控制电路单元还用以发送第二读取指令序列，其中第二读取指令序列用以从所述存储元中读取所述位元，存储器控制电路单元还用以根据所记录的相关信息更正所述位元，并且对更正后的所述位元执行第二解码。In an embodiment of the present invention, the memory control circuit unit is further configured to send a second read instruction sequence, wherein the second read instruction sequence is used to read the bit from the storage element, and the memory control The circuit unit is further configured to correct the bit according to the recorded relevant information, and perform a second decoding on the corrected bit.

在本发明的一实施例中，所述存储器控制电路单元还用以累计所述位元中属于第一类错误的至少一个错误的总数，并且判断总数是否大于错误阈值，如果总数大于错误阈值，则存储器控制电路单元发送写入指令序列，其中写入指令序列用以将更正后的所述位元写入至所述存储元。In an embodiment of the present invention, the memory control circuit unit is further configured to accumulate the total number of at least one error belonging to the first type of error in the bit, and judge whether the total number is greater than the error threshold, if the total number is greater than the error threshold, Then the memory control circuit unit sends a write command sequence, wherein the write command sequence is used to write the corrected bit into the storage element.

本发明的一实施例提供一种存储器控制电路单元，其用于控制可复写式非挥发性存储器模块，其中可复写式非挥发性存储器模块包括多个存储元，所述存储器控制电路单元包括主机接口、存储器接口、错误检查与校正电路及存储器管理电路。主机接口用以电性连接至主机系统。存储器接口用以电性连接至可复写式非挥发性存储器模块，其中可复写式非挥发性存储器模块包括多个存储元。存储器管理电路电性连接至主机接口、存储器接口及错误检查与校正电路，其中存储器管理电路用以发送第一读取指令序列，其中第一读取指令序列用以从所述存储元中读取多个位元，错误检查与校正电路用以对所述位元执行第一解码，如果所述位元具有至少一错误，则错误检查与校正电路还用以更正所述错误，并且存储器管理电路还用以判断每一所述错误是属于第一类错误或第二类错误，如果所述错误中的第一错误是属于第一类错误，则存储器管理电路还用以记录下第一错误的相关信息，以及如果第一错误是属于第二类错误，则存储器管理电路不记录第一错误的相关信息。An embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of storage elements, and the memory control circuit unit includes a host interface, memory interface, error checking and correction circuitry, and memory management circuitry. The host interface is used to electrically connect to the host system. The memory interface is used for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of storage elements. The memory management circuit is electrically connected to the host interface, the memory interface, and the error checking and correction circuit, wherein the memory management circuit is used to send a first read command sequence, wherein the first read command sequence is used to read from the storage element a plurality of bits, error checking and correction circuitry to perform a first decode on said bits, if said bit has at least one error, error checking and correction circuitry to correct said errors, and memory management circuitry It is also used to judge whether each of the errors belongs to the first type of error or the second type of error. If the first error in the errors belongs to the first type of error, the memory management circuit is also used to record the first error related information, and if the first error belongs to the second type of error, the memory management circuit does not record the related information of the first error.

在本发明的一实施例中，所述存储器管理电路判断每一所述错误是属于第一类错误或第二类错误的操作包括：取得第一错误在所述位元中对应的错误位元的通道可靠度信息；判断通道可靠度信息的值是否大于可靠度阈值；如果通道可靠度信息的值大于可靠度阈值，则判定第一错误是属于第一类错误；以及如果通道可靠度信息的值没有大于可靠度阈值，则判定第一错误是属于第二类错误。In an embodiment of the present invention, the memory management circuit determines that each error belongs to the first type of error or the second type of error includes: obtaining the error bit corresponding to the first error in the bit channel reliability information; determine whether the value of the channel reliability information is greater than the reliability threshold; if the value of the channel reliability information is greater than the reliability threshold, then determine that the first error belongs to the first type of error; and if the value of the channel reliability information If the value is not greater than the reliability threshold, it is determined that the first error belongs to the second type of error.

在本发明的一实施例中，所述存储器管理电路判断每一所述错误是属于第一类错误或第二类错误的操作包括：辨识出第一错误在所述存储元中对应的第一存储元；判断从第一存储元中读取的参考位元是否是第一值，其中第一错误在所述位元中对应的错误位元不是参考位元；如果参考位元是第一值，则判定第一错误是属于第一类错误；以及如果参考位元不是第一值，则判定第一错误是属于第二类错误。In an embodiment of the present invention, the memory management circuit determines whether each error belongs to the first type of error or the second type of error includes: identifying the first error corresponding to the first error in the storage element storage element; judging whether the reference bit read from the first storage element is the first value, wherein the error bit corresponding to the first error in the bit is not the reference bit; if the reference bit is the first value , then it is determined that the first error belongs to the first type of error; and if the reference bit is not the first value, it is determined that the first error belongs to the second type of error.

在本发明的一实施例中，所述存储器管理电路还用以发送第二读取指令序列，其中第二读取指令序列用以从所述存储元中读取所述位元，存储器管理电路还用以根据所记录的相关信息更正所述位元，并且错误检查与校正电路还用以对更正后的所述位元执行第二解码。In an embodiment of the present invention, the memory management circuit is also used to send a second read instruction sequence, wherein the second read instruction sequence is used to read the bit from the storage element, and the memory management circuit The bit is further corrected according to the recorded relevant information, and the error checking and correction circuit is further used for performing a second decoding on the corrected bit.

在本发明的一实施例中，所述存储器管理电路还用以累计所述位元中属于第一类错误的至少一个错误的总数并且判断总数是否大于错误阈值，如果总数大于错误阈值，则存储器管理电路还用以发送写入指令序列，其中写入指令序列用以将更正后的所述位元写入至所述存储元。In an embodiment of the present invention, the memory management circuit is also used to accumulate the total number of at least one error belonging to the first type of error in the bit and determine whether the total number is greater than the error threshold. If the total number is greater than the error threshold, the memory The management circuit is also used for sending a write command sequence, wherein the write command sequence is used for writing the corrected bit into the storage element.

本发明的一实施例提供一种错误处理方法，其用于可复写式非挥发性存储器模块，可复写式非挥发性存储器模块包括多个存储元，所述错误处理方法包括：发送第一读取指令序列，其中第一读取指令序列用以从所述存储元的第一存储元中读取多个位元；对所述位元执行第一解码；如果所述位元具有至少一错误，则更正所述错误，并判断每一所述错误是属于第一类错误或第二类错误；如果所述错误包含第一类错误，则发送写入指令序列，其中写入指令序列用以将更正后的所述位元写入至所述存储元的第二存储元；以及如果每一所述错误都是属于第二类错误，则输出更正后的所述位元，其中，第一存储元不同于第二存储元。An embodiment of the present invention provides an error handling method, which is used in a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of storage elements. The error handling method includes: sending a first read a sequence of fetching instructions, wherein a first sequence of read instructions is used to read a plurality of bits from a first storage element of said storage elements; perform a first decoding on said bits; if said bit has at least one error , then correct the error, and judge whether each error belongs to the first type of error or the second type of error; if the error includes the first type of error, then send the write command sequence, wherein the write command sequence is used to writing the corrected bit into a second storage unit of the storage units; and outputting the corrected bit if each of the errors belongs to the second type of error, wherein the first The storage element is different from the second storage element.

在本发明的一实施例中，所述判断每一所述错误是属于第一类错误或第二类错误的步骤包括：取得所述错误中的第一错误在所述位元中对应的错误位元的通道可靠度信息；判断通道可靠度信息的值是否大于可靠度阈值；以及如果通道可靠度信息的值大于可靠度阈值，则判定第一错误属于第一类错误。In an embodiment of the present invention, the step of judging whether each of the errors belongs to the first type of error or the second type of error includes: obtaining the error corresponding to the first error among the errors in the bit channel reliability information in bits; determine whether the value of the channel reliability information is greater than the reliability threshold; and if the value of the channel reliability information is greater than the reliability threshold, determine that the first error belongs to the first type of error.

在本发明的一实施例中，所述判断每一所述错误是属于第一类错误或第二类错误的步骤包括：判断从第一存储元中读取的参考位元是否是第一值，其中所述错误中的第一错误在所述位元中对应的错误位元不是参考位元；以及如果参考位元是第一值，则判定第一错误是属于第一类错误。In an embodiment of the present invention, the step of judging whether each error belongs to the first type of error or the second type of error includes: judging whether the reference bit read from the first storage element is the first value , wherein the error bit corresponding to the first error among the errors is not a reference bit; and if the reference bit is the first value, it is determined that the first error belongs to the first type of error.

本发明的一实施例提供一种存储器储存装置，其包括连接接口单元、可复写式非挥发性存储器模块及存储器控制电路单元。连接接口单元用以电性连接至主机系统。可复写式非挥发性存储器模块包括多个存储元。存储器控制电路单元电性连接至连接接口单元与可复写式非挥发性存储器模块。其中存储器控制电路单元用以发送第一读取指令序列，其中第一读取指令序列用以从所述存储元的第一存储元读取多个位元，存储器控制电路单元还用以对所述位元执行第一解码，如果所述位元具有至少一错误，则存储器控制电路单元还用以更正所述错误并判断每一所述错误是属于第一类错误或第二类错误，如果所述错误中包括第一类错误，则存储器控制电路单元还用以发送写入指令序列，其中写入指令序列用以将更正后的所述位元写入至所述存储元的第二存储元，以及如果每一所述错误都是属于第二类错误，则存储器控制电路单元还用以输出更正后的所述位元，其中，第一存储元不同于第二存储元。An embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to electrically connect to the host system. The rewritable non-volatile memory module includes a plurality of storage elements. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. Wherein the memory control circuit unit is used to send a first read command sequence, wherein the first read command sequence is used to read a plurality of bits from the first storage unit of the storage units, and the memory control circuit unit is also used to execute the The first decoding is performed on the bit, and if the bit has at least one error, the memory control circuit unit is also used to correct the error and determine whether each error belongs to the first type of error or the second type of error, if If the error includes the first type of error, the memory control circuit unit is also used to send a write instruction sequence, wherein the write instruction sequence is used to write the corrected bit into the second memory of the storage element. and if each of the errors belongs to the second type of error, the memory control circuit unit is further configured to output the corrected bit, wherein the first storage unit is different from the second storage unit.

在本发明的一实施例中，所述存储器控制电路单元判断每一所述错误是属于第一类错误或第二类错误的操作包括：取得所述错误中的第一错误在所述位元中对应的错误位元的通道可靠度信息；判断通道可靠度信息的值是否大于可靠度阈值；以及如果通道可靠度信息的值大于可靠度阈值，则判定第一错误属于第一类错误。In an embodiment of the present invention, the memory control circuit unit determines whether each of the errors belongs to the first type of error or the second type of error includes: obtaining the first error among the errors in the bit The channel reliability information of the corresponding error bit; determine whether the value of the channel reliability information is greater than the reliability threshold; and if the value of the channel reliability information is greater than the reliability threshold, then determine that the first error belongs to the first type of error.

在本发明的一实施例中，所述存储器控制电路单元判断每一所述错误是属于第一类错误或第二类错误的操作包括：判断从第一存储元中读取的参考位元是否是第一值，其中所述错误中的第一错误在所述位元中对应的错误位元不是参考位元；以及如果参考位元是第一值，则判定第一错误是属于第一类错误。In an embodiment of the present invention, the operation of the memory control circuit unit judging whether each error belongs to the first type of error or the second type of error includes: judging whether the reference bit read from the first storage element is is a first value, wherein the error bit corresponding to the first error in the bits is not a reference bit; and if the reference bit is the first value, it is determined that the first error belongs to the first category mistake.

本发明的一实施例提供一种存储器控制电路单元，其用于控制可复写式非挥发性存储器模块，其中可复写式非挥发性存储器模块包括多个存储元，所述存储器控制电路单元包括主机接口、存储器接口、错误检查与校正电路及存储器管理电路。主机接口用以电性连接至主机系统。存储器接口用以电性连接至可复写式非挥发性存储器模块，其中可复写式非挥发性存储器模块包括多个存储元。存储器管理电路电性连接至主机接口、存储器接口及错误检查与校正电路，其中存储器管理电路用以发送第一读取指令序列，其中第一读取指令序列用以从所述存储元的第一存储元中读取多个位元，错误检查与校正电路用以对所述位元执行第一解码，其中如果所述位元具有至少一个错误，则错误检查与校正电路还用以更正所述错误，并且存储器管理电路还用以判断每一所述错误是属于第一类错误或第二类错误，如果所述错误中包括第一类错误，则存储器管理电路还用以发送写入指令序列，其中写入指令序列用以将更正后的所述位元写入至所述存储元的第二存储元，以及如果每一所述错误都是属于第二类错误，则存储器管理电路还用以输出更正后的所述位元，其中，第一存储元不同于第二存储元。An embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of storage elements, and the memory control circuit unit includes a host interface, memory interface, error checking and correction circuitry, and memory management circuitry. The host interface is used to electrically connect to the host system. The memory interface is used for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of storage elements. The memory management circuit is electrically connected to the host interface, the memory interface, and the error checking and correction circuit, wherein the memory management circuit is used to send a first read command sequence, wherein the first read command sequence is used to read from the first memory cell. A plurality of bits are read from the memory cell, and the error checking and correction circuit is used to perform a first decoding on the bits, wherein if the bit has at least one error, the error checking and correction circuit is also used to correct the error, and the memory management circuit is also used to judge whether each error belongs to the first type of error or the second type of error, if the error includes the first type of error, the memory management circuit is also used to send the write instruction sequence , wherein the write instruction sequence is used to write the corrected said bit into the second memory element of said memory element, and if each of said errors belongs to the second type of error, the memory management circuit also uses to output the corrected bit, wherein the first memory element is different from the second memory element.

在本发明的一实施例中，所述存储器管理电路判断每一所述错误是属于第一类错误或第二类错误的操作包括：取得所述错误中的第一错误在所述位元中对应的错误位元的通道可靠度信息；判断通道可靠度信息的值是否大于可靠度阈值；以及如果通道可靠度信息的值大于可靠度阈值，则判定第一错误属于第一类错误。In an embodiment of the present invention, the memory management circuit determines whether each of the errors belongs to the first type of error or the second type of error includes: obtaining the first error among the errors in the bit channel reliability information corresponding to the error bit; judging whether the value of the channel reliability information is greater than the reliability threshold; and if the value of the channel reliability information is greater than the reliability threshold, determining that the first error belongs to the first type of error.

在本发明的一实施例中，所述存储器管理电路判断每一所述错误是属于第一类错误或第二类错误的操作包括：判断从第一存储元中读取的参考位元是否是第一值，其中所述错误中的第一错误在所述位元中对应的错误位元不是参考位元；以及如果参考位元是第一值，则判定第一错误是属于第一类错误。In an embodiment of the present invention, the operation of the memory management circuit judging whether each error belongs to the first type of error or the second type of error includes: judging whether the reference bit read from the first storage element is A first value, wherein the error bit corresponding to the first error among the errors is not a reference bit; and if the reference bit is the first value, then determining that the first error belongs to the first type of error .

基于上述，在对读取出的位元执行第一解码之后，如果这些位元中存在特定类型的错误，则这些错误的相关信息会被记录下来，以供进一步使用。另外，不属于此特定类型的错误的相关信息则不会被记录下来，由此节省存储器空间。Based on the above, after the first decoding is performed on the read bits, if there are certain types of errors in these bits, the relevant information of these errors will be recorded for further use. In addition, information about errors that do not belong to this specific type will not be recorded, thereby saving memory space.

为让本发明的上述特征和优点能更明显易懂，下文借助实施例，并配合附图做如下详细说明。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following detailed description is made with the help of embodiments and accompanying drawings.

附图说明Description of drawings

图1是根据本发明的一实施例所绘示的主机系统与存储器储存装置的示意图。FIG. 1 is a schematic diagram of a host system and a memory storage device according to an embodiment of the present invention.

图2是根据本发明的一实施例所绘示的计算机、输入/输出装置与存储器储存装置的示意图。FIG. 2 is a schematic diagram of a computer, an input/output device and a memory storage device according to an embodiment of the present invention.

图3是根据本发明的一实施例所绘示的主机系统与存储器储存装置的示意图。FIG. 3 is a schematic diagram of a host system and a memory storage device according to an embodiment of the present invention.

图4是图1所示的存储器储存装置的概要方块图。FIG. 4 is a schematic block diagram of the memory storage device shown in FIG. 1 .

图5是根据本发明的一实施例所绘示的可复写式非挥发性存储器模块的概要方块图。FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an embodiment of the present invention.

图6是根据本发明的一实施例所绘示的存储元阵列的示意图。FIG. 6 is a schematic diagram of a memory element array according to an embodiment of the present invention.

图7是根据本发明的一实施例所绘示储存于存储元阵列中的写入数据所对应的栅极电压的统计分布图。FIG. 7 is a statistical distribution diagram of gate voltages corresponding to write data stored in a memory cell array according to an embodiment of the present invention.

图8是根据本发明的一实施例所绘示的从存储元中读取数据的示意图，其是以MLCNAND型闪存为例。FIG. 8 is a schematic diagram of reading data from a storage element according to an embodiment of the present invention, which takes MLCNAND flash memory as an example.

图9是根据本发明的另一实施例所绘示的从存储元中读取数据的示意图。FIG. 9 is a schematic diagram of reading data from a storage element according to another embodiment of the present invention.

图10是根据本发明的一实施例所绘示的管理可复写式非挥发性存储器模块的示意图。FIG. 10 is a schematic diagram of managing a rewritable non-volatile memory module according to an embodiment of the present invention.

图11是根据本发明的一实施例所绘示的存储器控制电路单元的概要方块图。FIG. 11 is a schematic block diagram of a memory control circuit unit according to an embodiment of the present invention.

图12是根据本发明的一实施例绘示的奇偶检查矩阵的示意图。FIG. 12 is a schematic diagram of a parity check matrix according to an embodiment of the present invention.

图13是根据本发明的一实施例绘示的读取验证位元的示意图。FIG. 13 is a schematic diagram of reading verification bits according to an embodiment of the present invention.

图14是根据本发明的一实施例绘示的错误处理方法的流程图。FIG. 14 is a flowchart of an error handling method according to an embodiment of the present invention.

图15是根据本发明的另一实施例绘示的错误处理方法的流程图。FIG. 15 is a flowchart of an error handling method according to another embodiment of the present invention.

附图符号说明Description of reference symbols

11：主机系统11: Host system

12：计算机12: computer

122：微处理器122: Microprocessor

124：随机存储器124: RAM

13：输入/输出装置13: Input/Output Device

126：系统总线126: System bus

128：数据传输接口128: Data transmission interface

21：鼠标21: Mouse

22：键盘22: keyboard

23：显示器23: Display

24：打印机24: Printer

25：U盘25: U disk

26：记忆卡26: memory card

27：固态硬盘27: SSD

31：数码相机31: Digital camera

32：SD卡32: SD card

33：MMC卡33: MMC card

34：记忆棒34: memory stick

35：CF卡35: CF card

36：嵌入式储存装置36: Embedded storage device

10：存储器储存装置10: Memory storage device

402：连接接口单元402: Connect the interface unit

404：存储器控制电路单元404: memory control circuit unit

406：可复写式非挥发性存储器模块406: Rewritable non-volatile memory module

502：存储元阵列502: storage element array

504：字元线控制电路504: word line control circuit

506：位元线控制电路506: Bit line control circuit

508：列解码器508: column decoder

510：数据输入/输出缓冲器510: Data input/output buffer

512：控制电路512: control circuit

602：存储元602: storage element

604：位元线604: bit line

606：字元线606: character line

608：共用源极线608: Shared source line

612、614：晶体管612, 614: Transistors

400(0)～400(N)：实体抹除单元400(0)～400(N): Entity erasing unit

1102：存储器管理电路1102: memory management circuit

1104：主机接口1104: host interface

1106：存储器接口1106: memory interface

1108：错误检查与校正电路1108: Error checking and correction circuit

1110：缓存1110: Cache

1112：电源管理电路1112: power management circuit

1230：二分图1230: bipartite graph

1232(1)～1232(k)：奇偶节点1232(1)～1232(k): odd and even nodes

1234(1)～1234(n)：信息节点1234(1)～1234(n): information node

L_j→i、L_i→j：可靠度信息L _j→i , L _i→j : reliability information

1301～1306：区间1301～1306: Interval

1310、1320：储存状态1310, 1320: storage state

b1、b2、b3、b4、b5：验证位元b1, b2, b3, b4, b5: verification bits

S1401～S1407、S1501～S1503：步骤S1401～S1407, S1501～S1503: steps

具体实施方式Detailed ways

一般而言，存储器储存装置(亦称，存储器储存系统)包括可复写式非挥发性存储器模块与控制器(亦称，控制电路)。通常存储器储存装置是与主机系统一起使用，以使主机系统可将数据写入至存储器储存装置或从存储器储存装置中读取数据。Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage device.

图1是根据本发明的一实施例所绘示的主机系统与存储器储存装置的示意图。图2是根据本发明的一实施例所绘示的计算机、输入/输出装置与存储器储存装置的示意图。FIG. 1 is a schematic diagram of a host system and a memory storage device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a computer, an input/output device and a memory storage device according to an embodiment of the present invention.

请参照图1，主机系统11一般包括计算机12与输入/输出(input/output,I/O)装置13。计算机12包括微处理器122、随机存储器(random access memory,RAM)124、系统总线126与数据传输接口128。输入/输出装置13包括如图2的鼠标21、键盘22、显示器23与打印机24。必须了解的是，图2所示的装置非限制输入/输出装置13，输入/输出装置13可包括其他装置。Referring to FIG. 1 , the host system 11 generally includes a computer 12 and an input/output (I/O) device 13 . The computer 12 includes a microprocessor 122 , a random access memory (RAM) 124 , a system bus 126 and a data transmission interface 128 . The input/output device 13 includes a mouse 21 , a keyboard 22 , a monitor 23 and a printer 24 as shown in FIG. 2 . It must be understood that the device shown in FIG. 2 is not limited to the input/output device 13, and the input/output device 13 may include other devices.

在一实施例中，存储器储存装置10是通过数据传输接口128与主机系统11的其他元件电性连接。借助微处理器122、随机存储器124与输入/输出装置13的运行可将数据写入至存储器储存装置10或从存储器储存装置10中读取数据。例如，存储器储存装置10可以是如图2所示的U盘25、记忆卡26或固态硬盘(Solid State Drive,SSD)27等的可复写式非挥发性存储器储存装置。In one embodiment, the memory storage device 10 is electrically connected to other components of the host system 11 through the data transmission interface 128 . Data can be written into the memory storage device 10 or read from the memory storage device 10 by means of the operation of the microprocessor 122 , the random access memory 124 and the input/output device 13 . For example, the memory storage device 10 may be a rewritable non-volatile memory storage device such as a USB flash drive 25 , a memory card 26 or a solid state drive (Solid State Drive, SSD) 27 as shown in FIG. 2 .

图3是根据本发明的一实施例所绘示的主机系统与存储器储存装置的示意图。FIG. 3 is a schematic diagram of a host system and a memory storage device according to an embodiment of the present invention.

一般而言，主机系统11为可实质地与存储器储存装置10配合以储存数据的任意系统。虽然在本实施例中，主机系统11是以计算机系统来做说明，然而，另一实施例中，主机系统11可以是数码相机、摄影机、通信装置、音频播放器或视频播放器等系统。例如，在主机系统为数码相机(摄影机)31时，可复写式非挥发性存储器储存装置则为其所使用的SD卡32、MMC卡33、记忆棒(memory stick)34、CF卡35或嵌入式储存装置36(如图3所示)。嵌入式储存装置36包括嵌入式多媒体卡(Embedded MMC,eMMC)。值得一提的是，嵌入式多媒体卡是直接电性连接于主机系统的主板上。In general, the host system 11 is any system that can substantially cooperate with the memory storage device 10 to store data. Although in this embodiment, the host system 11 is described as a computer system, however, in another embodiment, the host system 11 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host system is a digital camera (video camera) 31, the rewritable non-volatile memory storage device is an SD card 32, an MMC card 33, a memory stick (memory stick) 34, a CF card 35 or an embedded Formula storage device 36 (as shown in Figure 3). The embedded storage device 36 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly electrically connected to the motherboard of the host system.

图4是图1所示的存储器储存装置的概要方块图。FIG. 4 is a schematic block diagram of the memory storage device shown in FIG. 1 .

请参照图4，存储器储存装置10包括连接接口单元402、存储器控制电路单元404与可复写式非挥发性存储器模块406。Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

在本实施例中，连接接口单元402是兼容串行高级技术附件(Serial AdvancedTechnology Attachment,SATA)标准。然而，必须了解的是，本发明不限于此，连接接口单元402也可以是符合并行高级技术附件(Parallel Advanced Technology Attachment,PATA)标准、电气和电子工程师协会(Institute of Electrical and Electronic Engineers,IEEE)1394标准、高速周边部件互联接口(Peripheral Component Interconnect Express,PCI Express)标准、通用串行总线(Universal Serial Bus,USB)标准、安全数码(SecureDigital,SD)接口标准、超高速一代(Ultra High Speed-I，UHS-I)接口标准、超高速二代(Ultra High Speed-II，UHS-II)接口标准、记忆棒(Memory Stick,MS)接口标准、多媒体储存卡(Multi Media Card,MMC)接口标准、嵌入式多媒体储存卡(Embedded MultimediaCard，eMMC)接口标准、通用闪存(Universal Flash Storage，UFS)接口标准、紧凑型闪存(Compact Flash,CF)接口标准、集成设备电子接口(Integrated Device Electronics,IDE)标准或其他适合的标准。连接接口单元402可与存储器控制电路单元404封装在一个晶片中，或者连接接口单元402是布设于一包含存储器控制电路单元404的晶片外。In this embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a device conforming to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, Secure Digital (SD) interface standard, Ultra High Speed- I, UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard , Embedded Multimedia Card (eMMC) interface standard, Universal Flash Storage (UFS) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standards or other suitable standards. The connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404 .

存储器控制电路单元404用以执行以硬件型式或固件型式实现的多个逻辑门或控制指令，并且根据主机系统11的指令在可复写式非挥发性存储器模块406中进行数据的写入、读取与抹除等操作。The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and write and read data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 and erase operations.

可复写式非挥发性存储器模块406是电性连接至存储器控制电路单元404，并且用以储存主机系统11所写入的数据。可复写式非挥发性存储器模块406可以是单阶存储元(Single Level Cell,SLC)NAND型闪存模块、多阶存储元(Multi Level Cell,MLC)NAND型闪存模块(即，一个存储元中可储存2个位元数据的闪存模块)、三阶存储元(Triple LevelCell，TLC)NAND型闪存模块(即，一个存储元中可储存3个位元数据的闪存模块)、其他闪存模块或其他具有相同特性的存储器模块。The rewritable non-volatile memory module 406 is electrically connected to the memory control circuit unit 404 and used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 can be a single-level storage unit (Single Level Cell, SLC) NAND flash memory module, a multi-level storage unit (Multi Level Cell, MLC) NAND flash memory module (that is, one storage unit can A flash memory module that stores 2 bits of data), a triple level cell (Triple LevelCell, TLC) NAND flash memory module (that is, a flash memory module that can store 3 bits of data in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

图5是根据本发明的一实施例所绘示的可复写式非挥发性存储器模块的概要方块图。图6是根据本发明的一实施例所绘示的存储元阵列的示意图。FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an embodiment of the present invention. FIG. 6 is a schematic diagram of a memory element array according to an embodiment of the present invention.

请参照图5，可复写式非挥发性存储器模块406包括存储元阵列502、字元线控制电路504、位元线控制电路506、列解码器(column decoder)508、数据输入/输出缓冲器510与控制电路512。Please refer to FIG. 5, the rewritable non-volatile memory module 406 includes a memory cell array 502, a word line control circuit 504, a bit line control circuit 506, a column decoder (column decoder) 508, and a data input/output buffer 510 and control circuit 512 .

在本实施例中，存储元阵列502可包括用以储存数据的多个存储元602、多个选择栅漏极(select gate drain,SGD)晶体管612与多个选择栅源极(select gate source,SGS)晶体管614、以及连接这些存储元的多条位元线604、多条字元线606、与共用源极线608(如图6所示)。存储元602是以阵列方式(或立体堆迭的方式)配置在位元线604与字元线606的交叉点上。当从存储器控制电路单元404接收到写入指令或读取指令时，控制电路512会控制字元线控制电路504、位元线控制电路506、列解码器508、数据输入/输出缓冲器510来写入数据至存储元阵列502或从存储元阵列502中读取数据，其中字元线控制电路504用以控制施加至字元线606的电压，位元线控制电路506用以控制施加至位元线604的电压，列解码器508依据指令中的行位址以选择对应的位元线，并且数据输入/输出缓冲器510用以暂存数据。In this embodiment, the memory element array 502 may include a plurality of memory elements 602 for storing data, a plurality of select gate drain (SGD) transistors 612 and a plurality of select gate source (select gate source, SGS) transistor 614, and a plurality of bit lines 604, a plurality of word lines 606, and a common source line 608 (as shown in FIG. 6 ) connecting these memory cells. The memory cells 602 are arranged in an array (or three-dimensionally stacked) at intersections of the bit lines 604 and the word lines 606 . When receiving a write instruction or a read instruction from the memory control circuit unit 404, the control circuit 512 controls the word line control circuit 504, the bit line control circuit 506, the column decoder 508, and the data input/output buffer 510 to Write data to the memory cell array 502 or read data from the memory cell array 502, wherein the word line control circuit 504 is used to control the voltage applied to the word line 606, and the bit line control circuit 506 is used to control the voltage applied to the bit line The voltage of the bit line 604, the column decoder 508 selects the corresponding bit line according to the row address in the instruction, and the data input/output buffer 510 is used for temporarily storing data.

可复写式非挥发性存储器模块406中的每一个存储元是以临界电压的改变来储存一或多个位元。具体来说，每一个存储元的控制栅极(control gate)与通道之间有一个电荷捕捉层。通过施加一写入电压至控制栅极，可以改变电荷补捉层的电子量，因而改变了存储元的临界电压。此改变临界电压的程序也称为”把数据写入至存储元”或”程序化存储元”。随着临界电压的改变，存储元阵列502的每一个存储元具有多个储存状态。并且通过读取电压可以判断存储元是属于哪一个储存状态，由此取得存储元所储存的一或多个位元。Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing the threshold voltage. Specifically, there is a charge trapping layer between the control gate (control gate) of each memory element and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory element. This process of changing the threshold voltage is also called "writing data into a memory cell" or "programming a memory cell". As the threshold voltage changes, each memory cell of the memory cell array 502 has multiple storage states. And by reading the voltage, it can be determined which storage state the storage element belongs to, thereby obtaining one or more bits stored in the storage element.

图7是根据本发明的一实施例所绘示的储存于存储元阵列中的写入数据所对应的栅极电压的统计分布图。FIG. 7 is a statistical distribution diagram of gate voltages corresponding to write data stored in a memory cell array according to an embodiment of the present invention.

请参照图7，以MLC NAND型闪存为例，随着不同的临界电压，每一存储元具有4种储存状态，并且这些储存状态分别地代表"11"、"10"、"00"与"01"等位元。换言之，每一个储存状态包括最低有效位元(Least Significant Bit，LSB)以及最高有效位元(MostSignificant Bit，MSB)。在本实施例中，储存状态(即，"11"、"10"、"00"与"01")中从左侧算起的第1个位元为LSB，而从左侧算起的第2个位元为MSB。因此，在此实施例中，每一存储元可储存2个位元。必须了解的是，图7所绘示的临界电压及其储存状态的对应仅为一个范例。在本发明另一实施例中，临界电压与储存状态的对应也可是随着临界电压越大而以"11"、"10"、"01"与"00"排列，或是其他排列。此外，在另一实施例中，也可定义从左侧算起的第1个位元为MSB，而从左侧算起的第2个位元为LSB。Please refer to Figure 7, taking MLC NAND flash memory as an example, with different threshold voltages, each memory element has 4 storage states, and these storage states represent "11", "10", "00" and "" respectively. 01" equivalent. In other words, each storage state includes a least significant bit (Least Significant Bit, LSB) and a most significant bit (Most Significant Bit, MSB). In this embodiment, the first bit from the left in the storage state (i.e., "11", "10", "00" and "01") is the LSB, and the bit from the left 2 bits are MSB. Therefore, in this embodiment, each memory cell can store 2 bits. It should be understood that the correspondence between the threshold voltage and its storage state shown in FIG. 7 is just an example. In another embodiment of the present invention, the correspondence between the threshold voltage and the storage state can also be arranged in "11", "10", "01" and "00" as the threshold voltage increases, or other arrangements. In addition, in another embodiment, it may also be defined that the first bit from the left is the MSB, and the second bit from the left is the LSB.

图8是根据本发明的一实施例所绘示的从存储元中读取数据的示意图，其是以MLCNAND型闪存为例。FIG. 8 is a schematic diagram of reading data from a storage element according to an embodiment of the present invention, which takes MLCNAND flash memory as an example.

请参照图8，存储元阵列502的存储元的读取操作是借助施加读取电压于控制栅极，借助存储元通道的导通状态，来识别存储元储存的数据。验证位元(VA)是用以指示施加读取电压VA时存储元通道是否为导通；验证位元(VC)是用以指示施加读取电压VC时，存储元通道是否为导通；验证位元(VB)是用以指示施加读取电压VB时，存储元通道是否为导通。在此假设验证位元是“1”时表示对应的存储元通道导通，而验证位元是“0”时表示对应的存储元通道没有导通。如图8所示，通过验证位元(VA)～(VC)可以判断存储元是处于哪一个储存状态，进而取得所储存的位元。Referring to FIG. 8 , the read operation of the memory cells of the memory cell array 502 is to identify the data stored in the memory cells by applying a read voltage to the control gate and by means of the conduction state of the memory cell channels. The verification bit (VA) is used to indicate whether the memory element channel is turned on when the read voltage VA is applied; the verification bit (VC) is used to indicate whether the memory element channel is turned on when the read voltage VC is applied; The bit (VB) is used to indicate whether the memory cell channel is turned on when the read voltage VB is applied. Here, it is assumed that when the verification bit is “1”, it means that the corresponding storage element channel is turned on, and when the verification bit is “0”, it means that the corresponding memory element channel is not turned on. As shown in FIG. 8 , by verifying the bits (VA)˜(VC), it can be determined which storage state the storage element is in, and then the stored bit can be obtained.

图9是根据本发明的另一实施例所绘示的从存储元中读取数据的示意图。FIG. 9 is a schematic diagram of reading data from a storage element according to another embodiment of the present invention.

请参照图9，以一TLC NAND型闪存为例，每一个储存状态包括左侧算起的第1个位元的最低有效位元LSB、从左侧算起的第2个位元的中间有效位元(Center SignificantBit，CSB)以及从左侧算起的第3个位元的最高有效位元MSB。在此范例中，依照不同的临界电压，存储元具有8种储存状态(即，"111"、"110"、"100"、"101"、"001"、"000"、"010"与"011")。借助施加读取电压VA～VG于控制栅极，可以识别存储元所储存的位元。其中，值得说明的是，此8种储存状态的排列顺序，可依制造商的设计而定，不限于本范例的排列方式。Please refer to Figure 9. Taking a TLC NAND flash memory as an example, each storage state includes the least significant bit LSB of the first bit from the left, and the middle effective bit of the second bit from the left. Bit (Center SignificantBit, CSB) and the most significant bit MSB of the third bit from the left. In this example, according to different threshold voltages, the memory cell has 8 storage states (i.e., "111", "110", "100", "101", "001", "000", "010" and " 011"). By applying read voltages VA˜VG to the control gates, the bits stored in the memory cells can be identified. Wherein, it is worth noting that the sequence of the eight storage states can be determined according to the design of the manufacturer, and is not limited to the arrangement in this example.

图10是根据本发明的一实施例所绘示的管理可复写式非挥发性存储器模块的示意图。FIG. 10 is a schematic diagram of managing a rewritable non-volatile memory module according to an embodiment of the present invention.

请参照图10，可复写式非挥发性存储器模块406的存储元702会构成多个实体程序化单元，并且这些实体程序化单元会构成多个实体抹除单元400(0)～400(N)。具体来说，同一条字元线上的存储元会组成一或多个实体程序化单元。如果每一个存储元可储存2个以上的位元，则同一条字元线上的实体程序化单元可被分类为下实体程序化单元与上实体程序化单元。例如，每一存储元的LSB是属于下实体程序化单元，并且每一存储元的MSB是属于上实体程序化单元。一般来说，在MLC NAND型闪存中，下实体程序化单元的写入速度会大于上实体程序化单元的写入速度。此外，在一般情况下，下实体程序化单元的可靠度是高于上实体程序化单元的可靠度。Please refer to FIG. 10, the storage unit 702 of the rewritable non-volatile memory module 406 will constitute a plurality of physical programming units, and these physical programming units will constitute a plurality of physical erasing units 400(0)-400(N) . Specifically, storage elements on the same word line form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be classified into lower physical programming units and upper physical programming units. For example, the LSB of each memory cell belongs to the lower physical programming unit, and the MSB of each memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit. In addition, in general, the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

在此实施例中，实体程序化单元为程序化的最小单元。即，实体程序化单元为写入数据的最小单元。例如，实体程序化单元为实体页面或是实体扇区(sector)。如果实体程序化单元为实体页面，则每一个实体程序化单元通常包括数据位元区与冗余位元区。数据位元区包含多个实体扇区，用以储存使用者的数据，而冗余位元区用以储存系统的数据(例如，错误更正码)。在本实施例中，每一个数据位元区包含32个实体扇区，且一个实体扇区的大小为512字节(byte,B)。然而，在其他实施例中，数据位元区中也可包含8个、16个或数目更多或更少的实体扇区，本发明并不限制实体扇区的大小以及个数。另一方面，实体抹除单元为抹除的最小单位。即，每一实体抹除单元含有最小数目的一并被抹除的存储元。例如，实体抹除单元为实体区块。In this embodiment, the entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. For example, the entity programming unit is an entity page or an entity sector (sector). If the physical programming unit is a physical page, each physical programming unit usually includes a data bit area and a redundant bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is for storing system data (eg, error correction code). In this embodiment, each data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the present invention does not limit the size and number of physical sectors. On the other hand, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains the minimum number of memory cells to be erased together. For example, the physical erasing unit is a physical block.

图11是根据本发明的一实施例所绘示的存储器控制电路单元的概要方块图。必须了解的是，图11所示的存储器控制电路单元的结构仅为一范例，本发明不以此为限。FIG. 11 is a schematic block diagram of a memory control circuit unit according to an embodiment of the present invention. It must be understood that the structure of the memory control circuit unit shown in FIG. 11 is just an example, and the present invention is not limited thereto.

请参照图11，存储器控制电路单元404包括存储器管理电路1102、主机接口1104、存储器接口1106与错误检查与校正电路1108。Referring to FIG. 11 , the memory control circuit unit 404 includes a memory management circuit 1102 , a host interface 1104 , a memory interface 1106 and an error checking and correction circuit 1108 .

存储器管理电路1102用以控制存储器控制电路单元404的整体运行。具体来说，存储器管理电路1102具有多个控制指令，并且在存储器储存装置10运行时，这些控制指令会被执行以进行数据的写入、读取与抹除等操作。以下说明存储器管理电路1102的操作时，等同于说明存储器控制电路单元404的操作，以下并不再赘述。The memory management circuit 1102 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 1102 has a plurality of control instructions, and when the memory storage device 10 is running, these control instructions will be executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 1102 is equivalent to the description of the operation of the memory control circuit unit 404 , which will not be repeated below.

在本实施例中，存储器管理电路1102的控制指令是以固件型式来实现。例如，存储器管理电路1102具有微处理器单元(未绘示)与只读存储器(未绘示)，并且这些控制指令是被烧录至此只读存储器中。当存储器储存装置10运行时，这些控制指令会由微处理器单元来执行以进行数据的写入、读取与抹除等操作。In this embodiment, the control instructions of the memory management circuit 1102 are implemented in the form of firmware. For example, the memory management circuit 1102 has a microprocessor unit (not shown) and a ROM (not shown), and these control instructions are burned into the ROM. When the memory storage device 10 is running, these control instructions will be executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

在本发明另一实施例中，存储器管理电路1102的控制指令也可以程序码型式储存于可复写式非挥发性存储器模块406的特定区域(例如，存储器模块中专用于存放系统数据的系统区)中。此外，存储器管理电路1102具有微处理器单元(未绘示)、只读存储器(未绘示)及随机存储器(未绘示)。特别是，此只读存储器具有驱动码，并且当存储器控制电路单元404被致能时，微处理器单元会先执行此驱动码段来将储存于可复写式非挥发性存储器模块406中的控制指令载入至存储器管理电路1102的随机存储器中。之后，微处理器单元会运行这些控制指令以进行数据的写入、读取与抹除等操作。In another embodiment of the present invention, the control instructions of the memory management circuit 1102 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of program code (for example, the system area in the memory module dedicated to storing system data) middle. In addition, the memory management circuit 1102 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has a driver code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the driver code segment to store the control code stored in the rewritable non-volatile memory module 406. The instructions are loaded into the RAM of the memory management circuit 1102 . Afterwards, the microprocessor unit runs these control instructions to perform operations such as writing, reading and erasing data.

此外，在本发明另一实施例中，存储器管理电路1102的控制指令也可以一硬件型式来实现。例如，存储器管理电路1102包括微控制器、存储元管理电路、存储器写入电路、存储器读取电路、存储器抹除电路与数据处理电路。存储元管理电路、存储器写入电路、存储器读取电路、存储器抹除电路与数据处理电路被电性连接至微控制器。其中，存储元管理电路用以管理可复写式非挥发性存储器模块406的实体区块；存储器写入电路用以对可复写式非挥发性存储器模块406下达写入指令以将数据写入至可复写式非挥发性存储器模块406中；存储器读取电路用以对可复写式非挥发性存储器模块406下达读取指令以从可复写式非挥发性存储器模块406中读取数据；存储器抹除电路用以对可复写式非挥发性存储器模块406下达抹除指令以将数据从可复写式非挥发性存储器模块406中抹除；而数据处理电路用以处理欲写入至可复写式非挥发性存储器模块406的数据以及从可复写式非挥发性存储器模块406中读取的数据。In addition, in another embodiment of the present invention, the control instructions of the memory management circuit 1102 can also be implemented in a hardware form. For example, the memory management circuit 1102 includes a microcontroller, a storage unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The storage element management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. Wherein, the storage unit management circuit is used to manage the physical block of the rewritable non-volatile memory module 406; the memory write circuit is used to issue a write command to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. In the rewritable non-volatile memory module 406; the memory read circuit is used to issue a read instruction to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406; the memory erase circuit It is used to issue an erase command to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406; and the data processing circuit is used to process the The data of the memory module 406 and the data read from the rewritable non-volatile memory module 406 .

主机接口1104是电性连接至存储器管理电路1102并且用以接收与识别主机系统11所传送的指令与数据。也就是说，主机系统11所传送的指令与数据会通过主机接口1104来传送至存储器管理电路1102。在本实施例中，主机接口1104是兼容于SATA标准。然而，必须了解的是本发明不限于此，主机接口1104也可以是兼容于PATA标准、IEEE 1394标准、PCIExpress标准、USB标准、SD标准、UHS-I标准、UHS-II标准、MS标准、MMC标准、eMMC标准、UFS标准、CF标准、IDE标准或其他适合的数据传输标准。The host interface 1104 is electrically connected to the memory management circuit 1102 and used for receiving and identifying commands and data transmitted by the host system 11 . That is to say, the commands and data sent by the host system 11 are sent to the memory management circuit 1102 through the host interface 1104 . In this embodiment, the host interface 1104 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 1104 may also be compatible with PATA standard, IEEE 1394 standard, PCIExpress standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

存储器接口1106是电性连接至存储器管理电路1102并且用以存取可复写式非挥发性存储器模块406。也就是说，欲写入至可复写式非挥发性存储器模块406的数据会经由存储器接口1106转换为可复写式非挥发性存储器模块406所能接受的格式。具体来说，如果存储器管理电路1102要存取可复写式非挥发性存储器模块406时，则存储器接口1106会传送对应的指令序列。这些指令序列可包括一或多个信号，或是在总线上的数据。例如，在读取指令序列中，会包括读取的辨识码、存储器位址等信息。The memory interface 1106 is electrically connected to the memory management circuit 1102 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 via the memory interface 1106 . Specifically, if the memory management circuit 1102 wants to access the rewritable non-volatile memory module 406, the memory interface 1106 will transmit a corresponding instruction sequence. These command sequences may include one or more signals, or data on a bus. For example, in the read command sequence, the read identification code, memory address and other information will be included.

错误检查与校正电路1108是电性连接至存储器管理电路1102并且用以执行错误检查与校正程序以确保数据的正确性。具体来说，当存储器管理电路1102从主机系统11中接收到写入指令时，错误检查与校正电路1108会为对应此写入指令的数据产生对应的错误更正码(error correcting code,ECC code)及/或错误检查码(error detecting code,EDC)，并且存储器管理电路1102会将对应此写入指令的数据与对应的错误更正码或错误检查码写入至可复写式非挥发性存储器模块406中。之后，当存储器管理电路1102从可复写式非挥发性存储器模块406中读取数据时会同时读取此数据对应的错误更正码及/或错误检查码，并且错误检查与校正电路1108会依据此错误更正码及/或错误检查码对所读取的数据执行错误检查与校正程序。在此实施例中，错误检查与校正电路1108所使用的是低密度奇偶检查校正码(low density parity code，LDPC)。然而，在另一实施例中，错误检查与校正电路1108所使用的也可以是BCH码、卷积码(convolutional code)、涡轮码(turbocode)，但不限于此。The error checking and correcting circuit 1108 is electrically connected to the memory management circuit 1102 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 1102 receives a write command from the host system 11, the error checking and correction circuit 1108 will generate a corresponding error correction code (error correcting code, ECC code) for the data corresponding to the write command and/or error detecting code (error detecting code, EDC), and the memory management circuit 1102 will write the data corresponding to the write command and the corresponding error correction code or error checking code into the rewritable non-volatile memory module 406 middle. Afterwards, when the memory management circuit 1102 reads data from the rewritable non-volatile memory module 406, it will simultaneously read the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 1108 will follow this The error correction code and/or the error check code executes error checking and correction procedures on the read data. In this embodiment, the ECC circuit 1108 uses a low density parity code (LDPC). However, in another embodiment, the error checking and correcting circuit 1108 may also use a BCH code, a convolutional code, or a turbo code, but is not limited thereto.

在一实施例中，存储器控制电路单元404还包括缓存1110与电源管理电路1112。In one embodiment, the memory control circuit unit 404 further includes a cache 1110 and a power management circuit 1112 .

缓存1110是电性连接至存储器管理电路1102并且用以暂存来自于主机系统11的数据与指令或来自于可复写式非挥发性存储器模块406的数据。The cache 1110 is electrically connected to the memory management circuit 1102 and used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 .

电源管理电路1112是电性连接至存储器管理电路1102并且用以控制存储器储存装置10的电源。The power management circuit 1112 is electrically connected to the memory management circuit 1102 and used to control the power of the memory storage device 10 .

在低密度奇偶检查校正码中，是用一个奇偶检查矩阵来定义有效的码字。以下将奇偶检查矩阵标记为矩阵H，并且一码字标记为CW。依照以下方程式(1)，如果奇偶检查矩阵H与码字CW的相乘是零向量，则表示码字CW为有效的码字。其中运算符表示模2(mod 2)的矩阵相乘。换言之，矩阵H的零空间(null space)便包含了所有的有效码字。然而，本发明并不限制码字CW的内容。例如，码字CW也可以包括用任意演算法所产生的错误更正码或是错误检查码。In low-density parity-check correction codes, a parity-check matrix is used to define effective codewords. The parity check matrix is denoted as matrix H, and a codeword is denoted as CW in the following. According to the following equation (1), if the multiplication of the parity check matrix H and the codeword CW is a zero vector, it means that the codeword CW is a valid codeword. where operator Represents matrix multiplication modulo 2. In other words, the null space of the matrix H includes all valid codewords. However, the invention does not limit the content of the codeword CW. For example, the codeword CW may also include error-correcting codes or error-checking codes generated by arbitrary algorithms.

其中矩阵H的维度是k×n(k-by-n)，码字CW的维度是1×n。k与n为正整数。码字CW中包括了信息位元与奇偶位元，即码字CW可以表示成[M P]，其中向量M是由信息位元所组成，向量P是由奇偶位元所组成。向量M的维度是1×(n-k)，而向量P的维度是1×k。以下将信息位元与奇偶位元统称为数据位元。换言之，码字CW中具有n个数据位元，其中信息位元的长度为(n-k)位元，并且奇偶位元的长度是k位元，即码字CW的码率(code rate)为(n-k)/n。The dimension of the matrix H is k×n (k-by-n), and the dimension of the codeword CW is 1×n. k and n are positive integers. The codeword CW includes information bits and parity bits, that is, the codeword CW can be expressed as [MP], wherein the vector M is composed of information bits, and the vector P is composed of parity bits. The dimension of the vector M is 1×(n-k), and the dimension of the vector P is 1×k. Hereinafter, information bits and parity bits are collectively referred to as data bits. In other words, there are n data bits in the code word CW, wherein the length of the information bit is (n-k) bits, and the length of the parity bit is k bits, that is, the code rate (code rate) of the code word CW is ( n-k)/n.

一般来说在编码时会使用一个产生矩阵(以下标记为G)，使得对于任意的向量M都可满足以下方程式(2)。其中产生矩阵G的维度是(n-k)×n。Generally, a generator matrix (marked as G below) is used during encoding, so that the following equation (2) can be satisfied for any vector M. The dimension of the generated matrix G is (n-k)×n.

由方程式(2)所产生的码字CW为有效的码字。因此可将方程式(2)代入方程式(1)，由此得到以下方程式(3)。The codeword CW generated by equation (2) is a valid codeword. Equation (2) can therefore be substituted into equation (1), thereby obtaining the following equation (3).

由于向量M可以是任意的向量，因此以下方程式(4)必定会满足。也就是说，在决定奇偶检查矩阵H以后，对应的产生矩阵G也可被决定。Since the vector M can be any vector, the following equation (4) must be satisfied. That is to say, after the parity check matrix H is determined, the corresponding generation matrix G can also be determined.

在解码一个码字CW时，会先对码字中的数据位元执行一个奇偶检查程序，例如将奇偶检查矩阵H与码字CW相乘以产生一个向量(以下标记为S，如以下方程式(5)所示)。如果向量S是零向量，则可直接输出码字CW。如果向量S不是零向量，则表示码字CW不是有效的码字。When decoding a codeword CW, a parity check procedure will be performed on the data bits in the codeword first, for example, the parity check matrix H is multiplied by the codeword CW to generate a vector (marked as S below, such as the following equation ( 5) as shown). If the vector S is a zero vector, the codeword CW can be output directly. If the vector S is not a zero vector, it means that the codeword CW is not a valid codeword.

向量S的维度是k×1，其中每一个元素也称为校验子(syndrome)。如果码字CW不是有效的码字，则错误检查与校正电路1108会执行一个解码程序，以尝试更正码字CW中的错误位元。The dimension of the vector S is k×1, and each element is also called a syndrome. If the codeword CW is not a valid codeword, the ECC circuit 1108 performs a decoding process to try to correct the erroneous bits in the codeword CW.

图12是根据本发明的一实施例绘示的奇偶检查矩阵的示意图。FIG. 12 is a schematic diagram of a parity check matrix according to an embodiment of the present invention.

请参照图12，一般来说，奇耦检查矩阵H可以表示为二分图(bipartite graph)1230，其中包括奇偶节点1232(1)～1232(k)与信息节点1234(1)～1234(n)。每一个奇偶节点1232(1)～1232(k)是对应到一个校验子，而每一个信息节点1234(1)～1234(n)是对应一个数据位元。数据位元与校验子之间的对应关系(即，信息节点1234(1)～1234(n)与奇偶节点1232(1)～1232(k)之间的连结关系)是根据奇偶检查矩阵所产生。具体来说，如果奇耦检查矩阵中第i行第j列的元素为1，则第i个奇偶节点1232(i)便会连接到第j个信息节点1234(j)，其中i与j为正整数。Please refer to FIG. 12 , in general, the parity check matrix H can be represented as a bipartite graph 1230, which includes parity nodes 1232(1)~1232(k) and information nodes 1234(1)~1234(n) . Each parity node 1232(1)-1232(k) corresponds to a syndrome, and each information node 1234(1)-1234(n) corresponds to a data bit. The corresponding relationship between data bits and syndromes (that is, the connection relationship between information nodes 1234(1)~1234(n) and parity nodes 1232(1)~1232(k)) is determined according to the parity check matrix. produce. Specifically, if the element in row i and column j in the odd-coupled check matrix is 1, the i-th parity node 1232(i) will be connected to the j-th information node 1234(j), where i and j are positive integer.

当存储器管理电路1102从可复写式非挥发性存储器模块406中读取n个数据位元(形成一个码字)时，则存储器管理电路1102也会取得每一个数据位元的一通道可靠度信息。此通道可靠度信息是用以表示对应的数据位元被解码为位元“1”或是“0”的机率(或称信心度)，以下再详细说明。在二分图1230中，信息节点1234(1)～1234(n)也会接收到对应的通道可靠度信息。例如，信息节点1232(1)会接收第1个数据位元的通道可靠度信息L₁，而信息节点1232(j)会接收第j个数据位元的通道可靠度信息L_j。When the memory management circuit 1102 reads n data bits (forming a code word) from the rewritable non-volatile memory module 406, the memory management circuit 1102 also obtains a channel reliability information of each data bit . The channel reliability information is used to represent the probability (or confidence) that the corresponding data bit is decoded as a bit "1" or "0", which will be described in detail below. In the bipartite graph 1230, information nodes 1234(1)-1234(n) also receive corresponding channel reliability information. For example, the information node 1232(1) receives the channel reliability information L ₁ of the 1st data bit, and the information node 1232(j) receives the channel reliability information L _j of the jth data bit.

错误检查与校正电路1108会根据二分图1230的结构与通道可靠度信息L₁～L_n来执行解码程序。此解码程序会包括迭代解码。具体来说，在迭代解码中，信息节点1234(1)～1234(n)会计算出可靠度信息给奇偶节点1232(1)～1232(k)，并且奇偶节点1232(1)～1232(k)也会计算出可靠度信息给信息节点1234(1)～1234(n)。这些可靠度信息会沿着这些二分图1230中的边(edge)来传送。例如，奇偶节点1232(i)传送给信息节点1234(j)的是可靠度信息L_i→j，而信息节点1234(j)传送给奇偶节点1232(i)是可靠度信息L_j→i。这些可靠度信息是用来表示一个节点认为某一个数据位元被解码为“1”或是“0”的机率(也称为信心度)有多少。举例来说，可靠度信息L_j→i表示信息节点1234(j)认为第j个数据位元被解码为“1”或是“0”的信心度(可为正或是负)，而可靠度信息L_i→j表示奇偶节点1232(i)认为第j个数据位元被解码为“1”或是“0”的信心度。而信息节点1234(1)～1234(n)与奇偶节点1232(1)～1232(k)会根据输入的可靠度信息来计算输出的可靠度信息，其近似于计算一个数据位元被解码为“1”或是“0”的条件机率。因此，上述传送可靠度信息的过程又被称为置信传播(belief propagation)。The error checking and correcting circuit 1108 executes the decoding process according to the structure of the bipartite graph 1230 and the channel reliability information L ₁ -L _n . This decoding procedure would include iterative decoding. Specifically, in iterative decoding, information nodes 1234(1)~1234(n) will calculate reliability information to parity nodes 1232(1)~1232(k), and parity nodes 1232(1)~1232(k) The reliability information is also calculated and sent to the information nodes 1234(1)-1234(n). The reliability information will be transmitted along the edges in the bipartite graph 1230 . For example, what the parity node 1232(i) transmits to the information node 1234(j) is reliability information L _i→j , and the information node 1234(j) transmits reliability information L _j→i to the parity node 1232(i). The reliability information is used to indicate the probability (also called confidence) that a node believes that a certain data bit is decoded as "1" or "0". For example, the reliability information L _j→i represents the confidence (may be positive or negative) that the information node 1234(j) believes that the jth data bit is decoded as "1" or "0", and the reliability The degree information L _i→j represents the degree of confidence that the parity node 1232(i) believes that the jth data bit is decoded as "1" or "0". The information nodes 1234(1)-1234(n) and parity nodes 1232(1)-1232(k) will calculate the output reliability information according to the input reliability information, which is similar to calculating a data bit decoded as Conditional probability of "1" or "0". Therefore, the above process of transmitting reliability information is also called belief propagation.

当采用不同的演算法，信息节点1234(1)～1234(n)及/或奇偶节点1232(1)～1232(k)会计算出不同的可靠度信息。例如，错误检查与校正电路1108可以采用总和乘积演算法(Sum-Product Algorithm)、最小值总和演算法(Min-Sum Algorithm)、或是位元翻转(bit-flipping Algorithm)，本发明并不限制采用何种演算法。When using different algorithms, the information nodes 1234(1)-1234(n) and/or the parity nodes 1232(1)-1232(k) will calculate different reliability information. For example, the error checking and correcting circuit 1108 may adopt a sum-product algorithm (Sum-Product Algorithm), a minimum value sum algorithm (Min-Sum Algorithm), or a bit-flipping (bit-flipping Algorithm), the present invention is not limited Which algorithm to use.

在迭代解码的每一次迭代中，信息节点1234(1)～1234(n)会传递可靠度信息给奇偶节点1232(1)～1232(k)，并且奇偶节点1232(1)～1232(k)会传递可靠度信息给信息节点1234(1)～1234(n)。在每一次迭代过后，信息节点1234(1)～1234(n)会根据目前的可靠度信息计算出每一个数据位元应该被解码为位元“1”或是“0”。接下来对这些计算出的数据位元执行奇偶检查程序，即将数据位元所形成的码字与奇偶检查矩阵相乘，由此判断该码字是否为有效的码字。如果所产生的码字为有效的码字，则迭代解码会停止。如果所产生的码字不是有效的码字，则会进行下一次的迭代。如果迭代解码的迭代次数超过一个预设值，则迭代解码也会停止，表示解码失败。In each iteration of iterative decoding, information nodes 1234(1)~1234(n) will transmit reliability information to parity nodes 1232(1)~1232(k), and parity nodes 1232(1)~1232(k) The reliability information will be delivered to the information nodes 1234(1)-1234(n). After each iteration, the information nodes 1234(1)-1234(n) calculate according to the current reliability information whether each data bit should be decoded as a bit "1" or "0". Next, a parity check program is performed on the calculated data bits, that is, the code word formed by the data bits is multiplied by the parity check matrix, thereby judging whether the code word is a valid code word. The iterative decoding stops if the resulting codeword is a valid codeword. If the generated codeword is not a valid codeword, the next iteration will be performed. If the number of iterations of the iterative decoding exceeds a preset value, the iterative decoding will also stop, indicating that the decoding fails.

图13是根据本发明的一实施例绘示的读取验证位元的示意图。请参照图13，在此假设属于储存状态1310的存储元所储存的是位元“1”，而属于储存状态1320的存储元所储存的是位元“0”。储存状态1310与储存状态1320有部分的重叠，即在某些读取电压，部分属于储存状态1310的存储元会被判别为属于储存状态1320，而部分属于储存状态1320的存储元会被判别为属于储存状态1310。在一实施例中，当施加读取电压于存储元的控制栅极以后，随着存储元通道是否导通，存储器管理电路1102所取得的验证位元会是“0”或是“1”。在此假设如果存储元通道没有导通时则对应的验证位元是“0”，反之则是“1”。如果存储器管理电路1102施加了读取电压V₁～V₅至某一存储元，则存储器管理电路1102会取得5个验证位元。具体来说，读取电压V₁是对应到验证位元b₁；读取电压V₂是对应到验证位元b₂；读取电压V₃是对应到验证位元b₃；读取电压V₄是对应到验证位元b₄；读取电压V₅是对应到验证位元b₅。如果一个存储元的临界电压是在区间1301，则从验证位元b₁至验证位元b₅，存储器管理电路1102所取得的验证位元会是“11111”；如果存储元的临界电压是在区间1302，则验证位元会是“01111”；如果存储元的临界电压是在区间1303，则验证位元会是“00111”；如果存储元的临界电压是在区间1304，则验证位元会是“00011”；如果存储元的临界电压是在区间1305，则验证位元会是“00001”；如果存储元的临界电压是在区间1306，则验证位元会是“00000”。在另一实施例中，可复写式非挥发性存储器模块406也可以将对验证位元b₁～b₅做运算以后，把运算后的验证位元传送给存储器管理电路1102。例如，验证位元b₂与b₄会进行异或运算，而验证位元b₁与b₅会进行异或运算。如此一来，存储器管理电路1102只会取得3个验证位元。本发明并不限制验证位元的个数与内容。FIG. 13 is a schematic diagram of reading verification bits according to an embodiment of the present invention. Referring to FIG. 13 , it is assumed that the memory cells belonging to the storage state 1310 store a bit “1”, and the memory cells belonging to the storage state 1320 store a bit “0”. The storage state 1310 and the storage state 1320 partially overlap, that is, at certain read voltages, some of the memory cells belonging to the storage state 1310 will be judged as belonging to the storage state 1320, and some of the memory cells belonging to the storage state 1320 will be judged as being Belongs to storage state 1310 . In one embodiment, after the read voltage is applied to the control gate of the memory cell, the verification bit obtained by the memory management circuit 1102 will be "0" or "1" according to whether the channel of the memory cell is turned on or not. It is assumed here that if the storage element channel is not turned on, the corresponding verification bit is "0", otherwise it is "1". If the memory management circuit 1102 applies the read voltages V ₁ -V ₅ to a certain memory cell, the memory management circuit 1102 will obtain 5 verification bits. Specifically, the read voltage V ₁ corresponds to the verification bit b ₁ ; the read voltage V ₂ corresponds to the verification bit b ₂ ; the read voltage V ₃ corresponds to the verification bit b ₃ ; the read voltage V ₄ corresponds to the verification bit b ₄ ; the read voltage V ₅ corresponds to the verification bit b ₅ . If the threshold voltage of a storage element is in the interval 1301, then from the verification bit b ₁ to the verification bit b ₅ , the verification bit obtained by the memory management circuit 1102 will be "11111"; if the threshold voltage of the storage element is in In interval 1302, the verification bit will be "01111"; if the threshold voltage of the storage element is in the interval 1303, the verification bit will be "00111"; if the threshold voltage of the storage element is in the interval 1304, then the verification bit will be is "00011"; if the threshold voltage of the storage element is in the interval 1305, the verification bit will be "00001"; if the threshold voltage of the storage element is in the interval 1306, the verification bit will be "00000". In another embodiment, the rewritable non-volatile memory module 406 may also transmit the calculated verification bits to the memory management circuit 1102 after performing operations on the verification bits b ₁ -b ₅ . For example, verification bits b2 and _b4 are XORed, and verification bits _b1 and _b5 are _XORed . In this way, the memory management circuit 1102 only obtains 3 verification bits. The present invention does not limit the number and content of verification bits.

在此实施例中，读取电压V₁～V₅的其中之一会被设定为正负号(sign)读取电压。此正负号读取电压是用来决定数据位元为何。例如，如果读取电压V₃为正负号读取电压，则数据位元会相同于验证位元b₃；如果读取电压V₂为正负号读取电压，则数据位元会相同于验证位元b₂，以此类推。在每一个区间中，根据存储元属于储存状态1310的机率与属于储存状态1320的机率，可以计算出对数似然比(Log Likelihood Ratio，LLR)，而在此实施例中此对数似然比也被称为数据位元的通道可靠度信息。在一实施例中，各个区间所对应的对数似然比可以事先被计算出来并且储存在一个查找表中。存储器管理电路1102可以将验证位元b₁～b₅输入此查找表中，由此取得对应的对数似然比以作为通道可靠度信息。所取得的通道可靠度信息(即，图12中的L₁～L_n)便可以来执行上述的迭代解码。在一实施例中，如果设定不同的正负号读取电压，则会使用不同的查找表来取得通道可靠度信息。In this embodiment, one of the read voltages V ₁ -V ₅ is set as a sign read voltage. The sign read voltage is used to determine what the data bit is. For example, if the read voltage _V3 is a signed read voltage, the data bit will be the same as the verification bit b3 _; if the read voltage V2 is a _signed read voltage, the data bit will be the same as Verify bit b ₂ , and so on. In each interval, according to the probability of the storage element belonging to the storage state 1310 and the probability of belonging to the storage state 1320, the log likelihood ratio (Log Likelihood Ratio, LLR) can be calculated, and in this embodiment, the log likelihood ratio Channel reliability information, also known as data bits. In an embodiment, the logarithmic likelihood ratios corresponding to each interval can be calculated in advance and stored in a lookup table. The memory management circuit 1102 can input the verification bits b ₁ -b ₅ into the lookup table, thereby obtaining the corresponding log-likelihood ratio as channel reliability information. The obtained channel reliability information (ie, L ₁ -L _n in FIG. 12 ) can be used to perform the above iterative decoding. In one embodiment, if different sign reading voltages are set, different look-up tables are used to obtain channel reliability information.

在上述的实施例中，如果读取电压的个数为x个，则可以分出x+1个区间，其中x为正整数。然而，在另一实施例中，如果读取电压的个数为x个，则可以分出y个区间，其中y可为任意的正整数。本发明并不限制x个读取电压会产生几个区间。如果读取电压的个数为1(例如，仅使用读取电压V₃)，则所进行的解码程序也被称为硬位元模式解码程序。如果读取电压的个数大于1，则所进行的解码程序也被称为软位元模式解码程序。一般来说，软位元模式解码程序所使用的信息较多，因此能更正较多的错误位元，但执行速度也比较慢。此外，在一实施例中，当进行硬位元模式解码程序时，存储器管理电路1102可以直接根据所取得的验证位元来计算出通道可靠度信息，并不会通过查找表。例如，如果验证位元为“1”，则通道可靠度信息可设定为z；如果验证位元为“0”，则通道可靠度信息可设定为-z，其中z为实数。In the above embodiment, if the number of read voltages is x, then x+1 intervals can be divided, where x is a positive integer. However, in another embodiment, if the number of read voltages is x, then y intervals can be divided, wherein y can be any positive integer. The present invention does not limit how many intervals can be generated by x read voltages. If the number of read voltages is 1 (for example, only read voltage V ₃ is used), the decoding process performed is also referred to as a hard bit pattern decoding process. If the number of read voltages is greater than 1, the performed decoding process is also referred to as a soft bit pattern decoding process. Generally speaking, the soft bit pattern decoding process uses more information, so more error bits can be corrected, but the execution speed is also slower. In addition, in one embodiment, when performing the hard bit pattern decoding process, the memory management circuit 1102 can directly calculate the channel reliability information according to the acquired verification bits without going through the lookup table. For example, if the verification bit is "1", the channel reliability information can be set to z; if the verification bit is "0", the channel reliability information can be set to -z, where z is a real number.

在本实施例中，如果存储器管理电路1102接收到来自主机系统的一读取指令或执行区块合并(merging)或垃圾回收(garbage collecting)程序等数据整理程序，存储器管理电路1102会发送一读取指令序列(也称为第一读取指令序列)至可复写式非挥发性存储器模块406。此第一读取指令序列包括一或多个程序码或指令码。此第一读取指令序列指示从可复写式非挥发性存储器模块406中的多个存储元读取一或多个数据。以读取一个实体程序化单元中的数据为例，此数据会包括多个位元。在取得这些位元后，错误检查与校正电路1108会对这些位元执行解码(也称为第一解码)。在本实施例中，第一解码可以是上述迭代解码或者任意可用以找出错误的解码程序。如果第一解码有找到一或多个错误，则存储器管理电路1102会判断每一个所找到的错误是属于第一类错误或第二类错误。In this embodiment, if the memory management circuit 1102 receives a read command from the host system or executes a data finishing program such as merging or garbage collection, the memory management circuit 1102 will send a read command. Fetch the instruction sequence (also referred to as the first read instruction sequence) to the rewritable non-volatile memory module 406 . The first read instruction sequence includes one or more program codes or instruction codes. The first read command sequence instructs to read one or more data from a plurality of memory cells in the rewritable non-volatile memory module 406 . Taking reading data in a physical programming unit as an example, the data will include multiple bits. After obtaining these bits, the ECC circuit 1108 performs decoding (also referred to as first decoding) on these bits. In this embodiment, the first decoding may be the above-mentioned iterative decoding or any decoding procedure that can be used to find errors. If the first decoding finds one or more errors, the memory management circuit 1102 will determine whether each found error belongs to the first type of error or the second type of error.

在本实施例中，第一类错误是指源错误(source error)。例如，如果所找到的某一个错误是因数据在传输至可复写式非挥发性存储器模块406时受到噪声干扰所产生的错误，则此错误是属于第一类错误。或者，如果所找到的某一个错误是在程序化存储元的过程中引起的，则此错误也是属于第一类错误。以图7为例，假设在程序化某一个存储元的MSB时，如果此程序化过程受到此存储元的LSB的影响，则可能会导致原先要将此存储元程序化成储存位元“11(正确)”变成储存位元“01(发生错误)”。而后，当此存储元的位元被读取出来解码时，不管是使用上述硬位元模式解码程序、软位元模式解码程序或任意的解码演算法，可能都无法解码成功。例如，不管如何的调整读取电压VA，可能都无法取得正确的位元。或者，即使可以找出属于第一类错误的错误，可能也需要耗费较多的时间。也就是说，产生第一类错误的主要原因通常是数据在写入时就发生了错误，而不是因为存储元的使用时间过长或者存储元的读取次数、写入次数或抹除次数过多等等。相对地，第二类错误则可以视为是除了第一类错误以外的各种错误。例如，因存储元的使用时间过长或者存储元的读取次数、写入次数或抹除次数过多所引起的错误等等。此外，在另一实施例中，也可以将特定的错误类型归类为第一类错误或第二类错误，或者也可以还划分第三类错误及/或第四类错误等等，本发明不加以限制。In this embodiment, the first type of error refers to a source error. For example, if an error found is caused by noise interference when the data is transmitted to the rewritable non-volatile memory module 406, then this error belongs to the first type of error. Or, if a certain error found is caused in the process of programming the storage element, then this error also belongs to the first type of error. Taking Fig. 7 as an example, assuming that when programming the MSB of a certain storage element, if the programming process is affected by the LSB of the storage element, it may cause the original storage element to be programmed into the storage bit "11( Correct)" becomes the storage bit "01 (error occurred)". Then, when the bits of the storage unit are read and decoded, no matter whether the above-mentioned hard bit mode decoding program, soft bit mode decoding program or any decoding algorithm is used, the decoding may not be successful. For example, no matter how the reading voltage VA is adjusted, the correct bit may not be obtained. Or, even if errors that fall into the first category can be found, it may take more time. That is to say, the main cause of the first type of error is usually that the data is wrong when it is written, not because the storage element is used for too long or the number of reads, writes or erasures of the storage element is too high. Wait more. In contrast, Type II errors can be regarded as various errors other than Type I errors. For example, the errors caused by the storage unit being used for too long or the storage unit being read, written or erased are too many times. In addition, in another embodiment, a specific error type can also be classified as the first type of error or the second type of error, or can also be divided into the third type of error and/or the fourth type of error, etc., the present invention Not limited.

在本实施例中，如果所找到的一或多个错误中的某一个错误(也称为第一错误)是属于第一类错误，则存储器管理电路1102会记录下此第一错误的相关信息，例如，记录在可复写式非挥发性存储器模块406中。第一错误的相关信息可以包括发生错误的数据、发生错误的存储元、发生错误的存储元的位置、数据中发生错误的位元(也称为错误位元)、发生错误的存储元是属于上实体程序化单元或下实体程序化单元、以及发生错误的存储元所储存的另一或多个位元(也称为参考位元)等信息的至少其中之一。此外，第一错误的相关信息也可以包括任意有用的信息，本发明不加以限制。值得一提的是，在此提及的第一错误的相关信息并不是使用在当前的解码中。例如，在本实施例中，是在发生错误的数据被更正之后，也就是解码成功之后，此第一错误的相关信息才会被记录下来。此外，在另一实施例中，此第一错误的相关信息也可以是在任意的时间点进行记录。另一方面，如果第一错误是属于第二类错误，则存储器管理电路1102不会记录此第一错误的相关信息。换言之，传统的作法是只要数据发生错误则错误位元在数据中的位置就会被记录下来，然而，在此提及的第一错误的相关信息则只有在找到的第一错误是属于第一类错误时才会被记录下来。由此，可减少需要储存的数据的数据量。以迭代解码为例，假设一个欲进行解码的数据是“11111111”，则在对于此数据的迭代解码成功之后，如果发现此数据中第2与第5个位元被更正，例如，错误检查与校正电路1108输出的数据为“11011011”，则存储器管理电路1102会判断第2与第5个位元的错误是否是属于第一类错误。假设第2个位元的错误是属于第二类错误且第5个位元的错误是属于第一类错误，则第5个位元的错误的相关信息会被记录下来，而第2个位元的错误的相关信息不会被记录下来。In this embodiment, if one of the found one or more errors (also referred to as the first error) belongs to the first type of error, the memory management circuit 1102 will record the relevant information of the first error , recorded in the rewritable non-volatile memory module 406, for example. The relevant information of the first error may include the data where the error occurred, the storage element where the error occurred, the location of the storage element where the error occurred, the bit where the error occurred in the data (also called the error bit), and the storage element where the error occurred. At least one of the upper physical programming unit or the lower physical programming unit, and another or more bits (also referred to as reference bits) stored in the error memory element. In addition, the relevant information of the first error may also include any useful information, which is not limited in the present invention. It is worth mentioning that the information about the first error mentioned here is not used in the current decoding. For example, in this embodiment, the information related to the first error will not be recorded until the data in which the error occurs is corrected, that is, after the decoding is successful. In addition, in another embodiment, the relevant information of the first error may also be recorded at any point in time. On the other hand, if the first error belongs to the second type of error, the memory management circuit 1102 will not record the relevant information of the first error. In other words, the traditional practice is that as long as an error occurs in the data, the position of the error bit in the data will be recorded. However, the relevant information about the first error mentioned here is only when the first error found belongs to the first error. Class errors are logged. Thus, the amount of data to be stored can be reduced. Taking iterative decoding as an example, assuming that the data to be decoded is "11111111", after the iterative decoding of this data is successful, if the 2nd and 5th bits in the data are found to be corrected, for example, the error check and The data output by the correction circuit 1108 is "11011011", and the memory management circuit 1102 will determine whether the errors in the second and fifth bits belong to the first type of errors. Assuming that the error of the 2nd bit belongs to the second type of error and the error of the 5th bit belongs to the first type of error, then the relevant information of the 5th bit error will be recorded, and the 2nd bit Information about meta errors will not be logged.

在一实施例中，存储器管理电路1102会获得第一错误在这些位元中对应的位元(即，错误位元)的通道可靠度信息。关于通道可靠度信息的获得方式已于前述说明，在此便不赘述。存储器管理电路1102会判断此通道可靠度信息的值是否大于一阈值(也称为可靠度阈值)。特别是，由于通道可靠度信息的初始值可能是负的，因此在此是使用通道可靠度信息的绝对值来与可靠度阈值进行比较。如果通道可靠度信息的值大于可靠度阈值，则存储器管理电路1102会判定第一错误是属于第一类错误。如果通道可靠度信息的值没有大于可靠度阈值，则存储器管理电路1102会判定第一错误是属于第二类错误。In one embodiment, the memory management circuit 1102 obtains the channel reliability information of the bit corresponding to the first error (ie, the error bit) among the bits. The manner of obtaining the channel reliability information has been described above, and will not be repeated here. The memory management circuit 1102 determines whether the value of the channel reliability information is greater than a threshold (also referred to as a reliability threshold). In particular, since the initial value of the channel reliability information may be negative, here the absolute value of the channel reliability information is used for comparison with the reliability threshold. If the value of the channel reliability information is greater than the reliability threshold, the memory management circuit 1102 will determine that the first error belongs to the first type of error. If the value of the channel reliability information is not greater than the reliability threshold, the memory management circuit 1102 will determine that the first error belongs to the second type of error.

在一实施例中，存储器管理电路1102会辨识出第一错误在这些存储元中对应的一个存储元(也称为第一存储元)。换言之，此第一存储元就是指储存有此第一错误对应的错误位元的存储元。存储器管理电路1102会判断从第一存储元中读取的另一个位元(即，参考位元)是否是一个特定的值(也称为第一值)。其中，此参考位元不是此第一错误在这些位元中对应的错误位元。在本实施例中，第一值是“1”，然而，在另一实施例中，第一值也可以是“0”。如果此参考位元是第一值，则存储器管理电路1102会判定此第一错误是属于第一类错误。如果此参考位元不是第一值，则存储器管理电路1102会判定此第一错误是属于第二类错误。在本实施例中，此参考位元与第一错误在这些位元中对应的错误位元是储存在同一个多阶存储元或三阶存储元中。例如，在本实施例中，第一错误对应的错误位元是第一存储元中的LSB，并且此参考位元是第一存储元中的MSB。更具体而言，在本实施例中，这些存储元是属于同一个下实体程序化单元且属于同一个上实体程序化单元，此第一错误所对应的错误位元是对应至此下实体程序化单元，并且此参考位元是对应至此上实体程序化单元。以图7为例，假设解码找出的错误位元是某一个存储元的LSB且其更正后的值是“1”(例如，从“0”更正成“1”)，如果此存储元的MSB也是“1”，则表示此存储元应该要储存位元“11”，但是却错误地被程序化成储存位元“01”。这种在数据传输或程序化时发生的错误即为第一类错误。In one embodiment, the memory management circuit 1102 identifies a memory cell (also referred to as a first memory cell) corresponding to the first error among the memory cells. In other words, the first memory element refers to the memory element storing the error bit corresponding to the first error. The memory management circuit 1102 will determine whether another bit (ie, the reference bit) read from the first storage element is a specific value (also referred to as the first value). Wherein, the reference bit is not the error bit corresponding to the first error among the bits. In this embodiment, the first value is "1", however, in another embodiment, the first value may also be "0". If the reference bit is the first value, the memory management circuit 1102 will determine that the first error belongs to the first type of error. If the reference bit is not the first value, the memory management circuit 1102 will determine that the first error belongs to the second type of error. In this embodiment, the reference bit and the error bits corresponding to the first error are stored in the same multi-level storage unit or third-level storage unit. For example, in this embodiment, the error bit corresponding to the first error is the LSB in the first storage unit, and the reference bit is the MSB in the first storage unit. More specifically, in this embodiment, these storage elements belong to the same lower physical programming unit and belong to the same upper physical programming unit, and the error bit corresponding to the first error is corresponding to the lower physical programming unit unit, and this reference bit is corresponding to this entity programming unit. Taking Fig. 7 as an example, assuming that the error bit found by decoding is the LSB of a certain storage element and its corrected value is "1" (for example, from "0" to "1"), if the storage element's The MSB is also "1", which means that the memory element should store bit "11", but it is wrongly programmed to store bit "01". This kind of error that occurs during data transmission or programming is the first type of error.

然而，在另一实施例中，此参考位元也可以是从与第一存储元相邻的存储元或任意具有参考价值的存储元中读取出来，本发明不加以限制。此外，此参考位元可以是随着第一错误对应的错误位元被读取出来。或者，此参考位元也可以是独立地在此错误位元之前或之后随着另一个数据被读取出来，本发明不加以限制。此外，此参考位元的数目可以是一或多个，本发明不加以限制。例如，如果第一存储元是多阶存储元，则此参考位元的数量是一个；如果第一存储元是三阶存储元，则此参考位元的数量则可能是一个或两个。However, in another embodiment, the reference bit can also be read from a storage unit adjacent to the first storage unit or any storage unit with reference value, which is not limited by the present invention. In addition, the reference bit can be read out along with the error bit corresponding to the first error. Alternatively, the reference bit can also be read independently before or after the error bit along with another data, which is not limited by the present invention. In addition, the number of the reference bits can be one or more, which is not limited by the present invention. For example, if the first storage unit is a multi-level storage unit, the number of the reference bit is one; if the first storage unit is a third-level storage unit, the number of the reference bit may be one or two.

在记录一个数据中属于第一类错误的一或多个错误的相关信息之后，这些相关信息可以例如是在下一次读取此数据时使用。例如，在一实施例中，在记录下上述数据中属于第一类错误的一或多个错误的相关信息之后，如果存储器管理电路1102接收到来自主机系统的另一读取指令或执行区块合并或垃圾回收程序等数据整理程序，存储器管理电路1102会发送一读取指令序列(也称为第二读取指令序列)至可复写式非挥发性存储器模块406。此第二读取指令序列包括一或多个程序码或指令码。此第二读取指令序列指示从可复写式非挥发性存储器模块406中的上述存储元读取数据。一般来说，如果第一读取指令序列与第二读取指令序列都是针对相同的存储元进行读取且储存在这些存储元中的数据没有被抹除，则根据第二读取指令序列取得的数据会与第一读取指令序列取得的数据相同。在错误检查与校正电路1108对此数据中的多个位元进行解码(亦称为第二解码)之前，存储器管理电路1102会从可复写式非挥发性存储器模块406中读取先前记录的与此数据中的第一类错误有关的相关信息并且根据此相关信息来更正这些位元。例如，更正这些位元中对应于第一类错误的一或多个错误位元。然后，错误检查与校正电路1108会对更正后的这些位元执行第二解码。由此，通过在解码前将不容易找到的具有第一类错误的错误位元更正，可有效提升后续执行的解码的速度。After recording the relevant information of one or more errors belonging to the first type of errors in a piece of data, the relevant information can be used, for example, when reading the data next time. For example, in one embodiment, after recording information about one or more errors belonging to the first type of errors in the above data, if the memory management circuit 1102 receives another read command or execution block from the host system For data sorting programs such as merging or garbage collection programs, the memory management circuit 1102 sends a read command sequence (also referred to as a second read command sequence) to the rewritable non-volatile memory module 406 . The second read instruction sequence includes one or more program codes or instruction codes. The second read instruction sequence instructs to read data from the above storage elements in the rewritable non-volatile memory module 406 . Generally speaking, if the first read command sequence and the second read command sequence both target the same storage element for reading and the data stored in these storage elements has not been erased, then according to the second read command sequence The obtained data will be the same as the data obtained by the first read command sequence. The memory management circuit 1102 reads the previously recorded and Relevant information about type 1 errors in this data and correct the bits based on this relative information. For example, one or more erroneous bits corresponding to the first type of errors among the bits are corrected. Then, the ECC circuit 1108 performs a second decoding on the corrected bits. Therefore, by correcting the erroneous bits with the first type of error that are not easy to find before decoding, the speed of subsequent decoding can be effectively improved.

在一实施例中，如果存储器管理电路1102判定所读取出的数据中包括第一类错误，则在更正此数据之后，存储器管理电路1102就会发送一个写入指令序列至可复写式非挥发性存储器模块406。此写入指令序列包括一或多个程序码或指令码。此写入指令序列用以指示将更正后的这些位元写入至储存这些位元的存储元。由此，在下一次从相同的存储元中读取数据时，所读取出的数据中就有很大的机率不会存在先前已被侦测出的第一类错误。特别是，在此实施例中，由于包括第一类错误的数据会被实时地更正并且被重新写入至对应的存储元，因此，存储器管理电路1102可以不记录第一类错误的相关信息。由此，可节省存储器空间。In one embodiment, if the memory management circuit 1102 determines that the read data includes the first type of error, after correcting the data, the memory management circuit 1102 will send a write command sequence to the rewritable non-volatile Sex memory module 406. The write command sequence includes one or more program codes or instruction codes. The write command sequence is used to instruct to write the corrected bits into the storage element storing the bits. Therefore, when data is read from the same storage element next time, there is a high probability that the read data will not have the previously detected Type 1 error. In particular, in this embodiment, since the data including the first type of error will be corrected in real time and rewritten to the corresponding storage element, therefore, the memory management circuit 1102 may not record the relevant information of the first type of error. Thus, memory space can be saved.

然而，在另一实施例中，存储器管理电路1102不会每次找到第一类错误就都更新存储元中的数据。例如，存储器管理电路1102会累计读取出的多个位元中属于第一类错误的一或多个错误的总数，并且判断此总数是否大于一阈值(也称为错误阈值)。如果此总数大于错误阈值，则存储器管理电路1102会发送上述写入指令序列以将更新后的这些位元写入至储存这些位元的存储元。如果此总数没有大于错误阈值，则存储器管理电路1102则不会发送上述写入指令序列。由此，可避免太频繁地对存储元进行读写。在一实施例中，此错误阈值可以是10～30或者更多或更少。以错误阈值是10为例，如果某一笔数据中属于第一类错误的多个错误的总数是8个，则此数据中与第一类错误有关的相关信息会被记录下来供下一次解码时使用，但更正后的此数据可能还不会被重新写入至储存此数据的存储元；然而，如果此笔数据中属于第一类错误的多个错误的总数是11个，则此数据中与第一类错误有关的相关信息不仅会被记录下来，并且更正后的数据会被重新写入至储存此数据的存储元中。However, in another embodiment, the memory management circuit 1102 does not update the data in the storage element every time a type I error is found. For example, the memory management circuit 1102 accumulates the total number of one or more errors belonging to the first type of errors among the read bits, and determines whether the total number is greater than a threshold (also referred to as an error threshold). If the total number is greater than the error threshold, the memory management circuit 1102 will send the above-mentioned write command sequence to write the updated bits into the memory cells storing the bits. If the total number is not greater than the error threshold, the memory management circuit 1102 will not send the above-mentioned sequence of write commands. Thus, too frequent reading and writing of storage elements can be avoided. In an embodiment, the error threshold may be 10-30 or more or less. Taking the error threshold of 10 as an example, if the total number of multiple errors belonging to the first type of error in a certain piece of data is 8, the relevant information related to the first type of error in this data will be recorded for the next decoding However, if the total number of multiple errors belonging to the first type of errors in this data is 11, then this data Not only will the relevant information related to the first type of error be recorded, but the corrected data will be rewritten to the memory element storing this data.

在另一实施例中，假设存储器管理电路1102是从某一个存储元中读取出包含多个位元的数据，则在判定这些位元中包含第一类错误并且更正此数据之后，存储器管理电路1102就会发送一个写入指令序列至可复写式非挥发性存储器模块406。此写入指令序列包括一或多个程序码或指令码。此写入指令序列用以指示将更正后的这些位元写入至另一个存储元。其中，被写入更正后的位元的存储元与原先储存这些位元的存储元并不相同。也就是说，在此实施例中，被识别出储存有包含第一类错误的数据的存储元会被舍弃，而此存储元所储存的数据会被更正并且搬移至其他的存储元，从而减少此数据往后再次出错的机率。此外，如果所读取出的数据不包括第一类错误(例如，仅包含第二类错误)，则在更正此数据之后，存储器管理电路1102会直接输出这些位元。在此实施例中，由于包括第一类错误的数据会被实时的更正并且被重新写入至对应的存储元，因此，存储器管理电路1102可以不记录第一类错误的相关信息。由此，可节省存储器空间。In another embodiment, assuming that the memory management circuit 1102 reads data containing a plurality of bits from a certain storage element, after determining that these bits contain the first type of error and correcting the data, the memory management The circuit 1102 then sends a write command sequence to the rewritable non-volatile memory module 406 . The write command sequence includes one or more program codes or instruction codes. The write command sequence is used to instruct to write the corrected bits into another storage element. Wherein, the memory cells into which the corrected bits are written are different from the memory cells originally storing these bits. That is to say, in this embodiment, the storage unit that is identified to store data containing the first type of error will be discarded, and the data stored in this storage unit will be corrected and moved to other storage units, thereby reducing The probability that this data will be wrong again in the future. In addition, if the read data does not contain Type 1 errors (for example, only contains Type 2 errors), the memory management circuit 1102 will directly output these bits after correcting the data. In this embodiment, since the data including the first type of error will be corrected in real time and rewritten to the corresponding storage element, therefore, the memory management circuit 1102 may not record the relevant information of the first type of error. Thus, memory space can be saved.

此外，在一实施例中，上述将更正后的数据重新写入至对应的存储元中的操作可以是实时地执行或者是仅在特定的时间点执行。其中，此特定的时间点可能是任何不会影响使用者正常操作的时间。例如，此特定的时间点可以是可复写式非挥发性存储器模块406闲置一段时间后、开机之后、关机之前或者由使用者自行决定等等，本发明不加以限制。或者，在一实施例中，存储器管理电路1102也可能会每隔一段时间或者在上述特定时间点自动从可复写式非挥发性存储器模块406的部分存储元中读取数据，并且执行上述找出数据中的第一类错误以及上述更正储存在这些存储元中的数据的操作。换言之，由于第一类错误的特性是不容易随着存储元的使用时间或者存储元的读取次数、写入次数或抹除次数等而产生，因此只要把存储元中具有第一类错误的位元进行更正，即可有效提升往后对相同数据进行解码的效率。In addition, in an embodiment, the above operation of rewriting the corrected data into the corresponding storage element may be performed in real time or only at a specific time point. Wherein, the specific time point may be any time that will not affect the normal operation of the user. For example, the specific time point may be after the rewritable non-volatile memory module 406 has been idle for a period of time, after it is turned on, before it is turned off, or determined by the user, which is not limited by the present invention. Or, in an embodiment, the memory management circuit 1102 may also automatically read data from some storage elements of the rewritable non-volatile memory module 406 at regular intervals or at the above-mentioned specific time point, and perform the above-mentioned finding Type I errors in data and the above-mentioned operations to correct the data stored in these memory cells. In other words, due to the characteristics of the first type of error, it is not easy to produce with the use time of the storage element or the number of times of reading, writing, or erasing of the storage element, so as long as the storage element has the first type of error By correcting the bits, the efficiency of subsequent decoding of the same data can be effectively improved.

图14是根据本发明的一实施例所绘示的错误处理方法的流程图。FIG. 14 is a flowchart of an error handling method according to an embodiment of the present invention.

请参照图14，在步骤S1401中，发送第一读取指令序列，其中第一读取指令序列用以从多个存储元中读取多个位元。在步骤S1402中，对所述位元执行第一解码。在步骤S1403中，判断第一解码是否成功。如果第一解码失败，则例如是执行调整读取电压以重新读取所述存储元等操作，本发明不加以限制。如果第一解码成功，则在步骤S1404中，判断所述位元中是否具有错误。如果所述位元中不具有错误，则例如是执行输出所述位元等操作，本发明不加以限制。如果所述位元中具有错误，则在步骤S1405中，判断每一个错误是属于第一类错误或第二类错误。在此，以判断所述错误中的第一错误是属于第一类错误或第二类错误为例。如果此第一错误是属于第一类错误，则在步骤S1406中，记录下此第一错误的相关信息。如果此第一错误是属于第二类错误，则在步骤S1407，不记录第一错误的相关信息。步骤S1405至S1407会重复执行，直到检查完所有错误为止。此外，在另一实施例中，步骤S1407也可以忽略。Please refer to FIG. 14 , in step S1401 , a first read command sequence is sent, wherein the first read command sequence is used to read a plurality of bits from a plurality of storage elements. In step S1402, a first decoding is performed on the bit. In step S1403, it is judged whether the first decoding is successful. If the first decoding fails, operations such as adjusting the read voltage to read the storage element again are performed, which is not limited in the present invention. If the first decoding is successful, in step S1404, it is judged whether there is an error in the bit. If there is no error in the bit, an operation such as outputting the bit is performed, and the invention is not limited thereto. If there is an error in the bit, then in step S1405, it is determined whether each error belongs to the first type of error or the second type of error. Here, it is taken as an example to determine whether the first error among the errors belongs to the first type of error or the second type of error. If the first error belongs to the first type of error, then in step S1406, record the relevant information of the first error. If the first error belongs to the second type of error, then in step S1407, the relevant information of the first error is not recorded. Steps S1405 to S1407 are repeatedly executed until all errors are checked. In addition, in another embodiment, step S1407 can also be ignored.

图15是根据本发明的另一实施例所绘示的错误处理方法的流程图。FIG. 15 is a flowchart of an error handling method according to another embodiment of the present invention.

请参照图15，在步骤S1501中，发送第二读取指令序列，其中第二读取指令序列用以从多个存储元中读取多个位元。在此实施例中，这些位元已经经过至少一次的读取以及解码，并且这些位元中属于第一类错误的错误的相关信息也已被纪录下来。在步骤S1502中，根据所记录的相关信息，更正这些位元。具体而言，步骤S1502是指更正这些位元中具有第一类错误的错误位元。在将这些位元中具有第一类错误的错误位元更正之后，在步骤S1503中，对更正后的这些位元执行第二解码。Referring to FIG. 15 , in step S1501 , a second read instruction sequence is sent, wherein the second read instruction sequence is used to read a plurality of bits from a plurality of storage elements. In this embodiment, the bits have been read and decoded at least once, and the relevant information of the errors belonging to the first type of errors in the bits has also been recorded. In step S1502, these bits are corrected according to the recorded relevant information. Specifically, step S1502 refers to correcting the erroneous bits with the first type of error among the bits. After correcting the erroneous bits with the first type of error among the bits, in step S1503, the second decoding is performed on the corrected bits.

然而，图14与图15中各步骤已详细说明如上，在此便不再赘述。值得注意的是，图14与图15中各步骤可以实现为多个程序码或是电路，本发明不加以限制。此外，图14与图15的方法可以搭配以上实施例使用，也可以单独使用，本发明不加以限制。However, each step in FIG. 14 and FIG. 15 has been described in detail above, and will not be repeated here. It should be noted that each step in FIG. 14 and FIG. 15 can be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the methods shown in FIG. 14 and FIG. 15 can be used in combination with the above embodiments, or can be used alone, which is not limited by the present invention.

综上所述，在对读取出的数据执行第一解码之后，如果此数据中存在特定类型的错误，则这些错误的相关信息会被记录下来。例如，在下一次对同样的数据进行解码之前，这些特定类型的错误就会先被更正，以加快后续的解码速度。或者，在更正数据中特定类型的错误之后，此数据也可以被重新写入至对应的存储元中，以避免每次读取此数据时都要执行相同的更正。另外，不属于此特定类型的错误的相关信息则不会被记录下来，由此节省存储器空间。To sum up, after the first decoding is performed on the read data, if there are specific types of errors in the data, the relevant information of these errors will be recorded. For example, before the next time the same data is decoded, these specific types of errors are corrected to speed up subsequent decoding. Alternatively, after correcting a specific type of error in the data, the data can also be rewritten into the corresponding memory element, so as to avoid performing the same correction every time the data is read. In addition, information about errors that do not belong to this specific type will not be recorded, thereby saving memory space.

虽然本发明已以实施例揭示如上，然而其并非用以限定本发明，任何本领域技术人员在不脱离本发明的精神和范围下，当可做些许的更动与润饰，故本发明的保护范围是以本发明的权利要求为准。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention, so the protection of the present invention The scope is defined by the claims of the present invention.