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CN106301305B - A kind of switching matrix drive circuit and method - Google Patents

  • ️Fri Jan 04 2019
A kind of switching matrix drive circuit and method

Technical field

The present invention relates to switch matrix control field, especially a kind of switching matrix drive circuit and method.

Background technique

Currently, existing switch matrix control method is not as shown in Figure 1, driving chip has data selection function, how many The SEL signal of position, can only just drive the relay of identical digit, driving circuit is difficult to effectively simplify.The control of driving chip is believed It number corresponds, cannot share with driving chip, it is every to increase a piece of driving chip, then it needs to increase corresponding piece choosing and switch level Deng control signal, main control chip needs many pins of overabsorption to control these driving chips.

Traditional large-scale switches matrix, due to relay and the various complexity of control circuit, it is difficult to realization device it is small-sized Change, occupies many space resources, be unfavorable for building for Auto-Test System.

Traditional switch matrix device, control line is attached directly to relay array after driver is pressurized and expands stream, to reach All control signals of the accurate control of switching channels, driving circuit require individual control signal wire to control, and occupy Very more plate grade resource, so that the expansible space of switch matrix is very small, it is difficult to adapt to the testing requirement of high speed development.

Traditional switch matrix control method, can not reasonable common drive chip control signal, control signal shares meeting The maloperation for generating a large amount of relays, cannot achieve signal transmission and routing be precisely controlled, not can guarantee in test macro and believe Number switching and routing that output and input.

In traditional switch matrix control method, when needing to keep a relay control signal state, it is necessary to keep it The control signal condition of corresponding driving chip, when longtime running, caused by power consumption penalty it is very big, and be unfavorable for device Heat dissipation.

Summary of the invention

The purpose of the present invention is to overcome above-mentioned the deficiencies in the prior art, provide a kind of switching matrix drive circuit and side Method.

To achieve the above object, the present invention adopts the following technical solutions:

A kind of switching matrix drive circuit, comprising:

CPLD chip for receiving the instruction of bus interface transmission, and decodes received instruction;

Relay driving chip, with CPLD chip by connection, for receiving the instruction after CPLD chip decodes, And selection output significance bit is decoded to control the corresponding actuating of relay by address date SEL;

Wherein, the relay driving chip is M group, and any group includes N number of driving chip, shares one with driving chip is organized A piece selects CS, and n-th of chip of difference group shares a switch level signal LVL, and all driving chips share a number of addresses According to SEL, wherein n≤N.

Preferably, the switch level signal LVL and address date SEL default conditions are low level, by driving The high level pulse of switch level and address date pin sending time span the covering chip selection signal effectual time of chip, is realized Switch level signal LVL and address date SEL by low level to high level jump, and after piece selects CS invalid, switch level letter Number LVL and address date SEL is low level by high level jump.Above-mentioned design advantageously reduces entire switching matrix drive circuit Power consumption, reduce the generation of heat.

Preferably, all driving chips share global reset signal RESET, when global reset signal RESET is effective, own The output of driving chip is shielded.By the way that global reset signal is arranged, so that entire driving circuit is without increasing bus marco letter Number pin, can judge the state of chip selection signal CS in bus control signal in CPLD chip, when chip selection signal CS is entirely effective, Global reset signal RESTET signal is effective, and all driving chips share a RESET signal, to realize the function of Global reset Energy.

Based on the driving method of above-mentioned switching matrix drive circuit, when the X of n-th of driving chip in control M group When a output bit, the corresponding chip selection signal of M group driving chip is placed in effective status, while all driving chips in M group X position output bit is in by mode of operation, and the present invention solves non-targeted output bit by improvement control method and is misused The problem of;

Specific step is as follows:

Step 1 judges the grouping where the corresponding driving chip A of controlled relay, obtains point where driving chip A Group # M;

Step 2, the driving chip for including in addition to driving chip A in the M driving chip group in query steps one;

Step 3 inquires the X output bit of driving chips all in addition to the driving chip A driving chip group Nei;

If the X position output bit state of n-th of driving chip is high in the driving chip group, in the control routine sent The corresponding code of switch level signal LVL (n) is set to 1;

If the X position output bit state of n-th of driving chip is low in the driving chip group, in the control routine sent The corresponding code of switch level signal LVL (n) is set to 0.

The beneficial effects of the present invention are:

1. being grouped shared control signals by rationally designing driving circuit, the service efficiency for controlling pin is maximized, and And by state recording and inquiry, control routine is flexibly sent, effectively solves the problems, such as that control signal shares bring maloperation;

2. the present invention significantly improves the integrated design degree of switch matrix, reduce the resource and sky of control circuit occupancy Between, meet the Miniaturization Design demand of automatic test equipment;

3. the present invention has Universal and scalability can be according to switch suitable for the switch matrix of any interface form Matrix size flexible expansion, convenient for flexibly building for Auto-Test System.

Detailed description of the invention

Fig. 1 is existing switch matrix control method schematic diagram;

Fig. 2 is the structural schematic diagram of switching matrix drive circuit provided by the invention;

Fig. 3 is the flow chart of switch matrix driving method provided by the invention.

Specific embodiment

Present invention will be further explained below with reference to the attached drawings and examples.

In the prior art, each driving chip be all made of individual piece choosing, switch level, address date come realize operation, However along with the expansion of switch matrix scale, the control signal for needing enormous amount controls switch matrix, so, Control circuit resource is utilized to be minimal, the present invention provides a kind of switching matrix drive circuit and method, it can be achieved that control The effective use of circuit resource processed.

As shown in Fig. 2, a kind of switching matrix drive circuit, comprising:

CPLD chip for receiving the instruction of bus interface transmission, and decodes received instruction;

Relay driving chip, with CPLD chip by connection, for receiving the instruction after CPLD chip decodes, And selection output significance bit is decoded to control the corresponding actuating of relay by address date SEL;All output bits are mutually indepedent, mutually It does not influence;

Wherein, the relay driving chip is M group, and any group includes N number of driving chip, shares one with driving chip is organized A piece selects CS, and n-th of chip of difference group shares a switch level signal LVL, and all driving chips share a number of addresses According to SEL, wherein n≤N.

Switch level signal LVL is used to operate the level state of output bit, and switch level signal LVL is defaulted as low electricity Flat, piece selects when rising edge such as control switch is opened, then sends high level pulse, and control switch disconnects, then keeps low level;B Address date SEL selection signal is defaulted as low level, and high level pulse signal, driving chip are sent when address date SEL is effective When piece selects effective, effective output bit operated by SEL signal framing is read, reads LVL signal to determine effective output bit Output level.

The switch level signal LVL and address date SEL default conditions are low level, pass through opening to driving chip The high level pulse of powered-down gentle address date pin sending time span covering chip selection signal effectual time, realizes switch level Signal LVL and address date SEL by low level to high level jump, and after piece selects CS invalid, switch level signal LVL and Address date SEL is low level by high level jump.Above-mentioned design advantageously reduces the power consumption of entire switching matrix drive circuit, Reduce the generation of heat.

Preferably, all driving chips share global reset signal RESET, when global reset signal RESET is effective, own The output of driving chip is shielded.By the way that global reset signal is arranged, so that entire driving circuit is without increasing bus marco letter Number pin, can judge the state of chip selection signal CS in bus control signal in CPLD chip, when chip selection signal CS is entirely effective, Global reset signal RESTET signal is effective, and all driving chips share a RESET signal, to realize the function of Global reset Energy.

Based on the driving method of above-mentioned switching matrix drive circuit, when the X of n-th of driving chip in control M group When a output bit, the corresponding chip selection signal of M group driving chip is placed in effective status, while all driving chips in M group X position output bit is in by mode of operation, and the present invention solves non-targeted output bit by improvement control method and is misused The problem of;

Specific step is as follows:

All driving chips all share an address date SEL, when the X for n-th of driving chip for needing to control M group When a output bit, this group of chip chip selection signal can be placed in effective status, and since the address date of all chips all shares, will The X position of all driving chips in the driving chip group is caused to export all in by mode of operation, it is therefore desirable to look by state Ask determine LVL signal in control routine each data value, set LVL as it is high when output significance bit be also it is high, judge Process is as shown in Figure 3.Other driving chips in same group are first found out, inquire the state of the X position output bit of these chips, such as The X position of n-th of driving chip is height in group, wherein switch level signal is expressed as LVL (n), then is sending control routine When, the correspondence code of LVL (n) is 1, as X position be it is low, then when sending control routine, the correspondence code of LVL (n) is 0, with This changes standing state to prevent the corresponding identical output bit of identical SEL signal with the chip of a piece of choosing to be misused.

Further, operational relay driving chip output bit is the specific steps of effective status are as follows:

When driving chip chip selection signal is effective, driving chip latch switch level signal and address date state pass through Address data signal decoding determines which output pin of operation, and how switch level signal deciding operates and (draw high or drag down) should Pin.

If the address date SEL of each driving chip is B, each driving chip controls A relay, driving chip Effective output bit is determined that the numerical value of the quantity A of output pin is 2B by SEL signal interpretation, then spool is controlled needed for switch matrix Foot quantity is that piece selects the sum of quantity, switch level number of signals and address date digit, i.e. M+N+B, simultaneously as each drive Dynamic A relay of chip controls, driving chip sum are the divisor of total number of relays and A, i.e. driving chip sum=relay Sum/A.Therefore, compared to Figure 1 the present invention, improves the integrated design degree of switch matrix, reduces driving circuit occupancy Resource and space meet the miniature requirement of automatic test equipment.

The present invention by by driving chip carry out it is reasonable must be grouped, convert large-scale switches matrix majorization to that " N × M drives The control of dynamic chip matrix ", each column share a chip selection signal, and every row shares a switch level signal, passes through chip selection signal The grouping of " driving chip matrix " can be positioned, i.e., one group correspondence one arranges, and each driving chip is opened by different in any group Level signal LVL is closed to be controlled.

Above-mentioned, although the foregoing specific embodiments of the present invention is described with reference to the accompanying drawings, not protects model to the present invention The limitation enclosed, those skilled in the art should understand that, based on the technical solutions of the present invention, those skilled in the art are not Need to make the creative labor the various modifications or changes that can be made still within protection scope of the present invention.