CN106783900B - A SOI pixel detector structure - Google Patents
- ️Tue Aug 11 2020
CN106783900B - A SOI pixel detector structure - Google Patents
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- CN106783900B CN106783900B CN201611094845.7A CN201611094845A CN106783900B CN 106783900 B CN106783900 B CN 106783900B CN 201611094845 A CN201611094845 A CN 201611094845A CN 106783900 B CN106783900 B CN 106783900B Authority
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- 238000001514 detection method Methods 0.000 claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
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- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
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- 229910052698 phosphorus Inorganic materials 0.000 description 3
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- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
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- H10F39/80—Constructional details of image sensors
- H10F39/803—Pixels having integrated switching, control, storage or amplification elements
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- H10F39/80—Constructional details of image sensors
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Abstract
The invention discloses an SOI pixel detector structure, which comprises a low-resistance silicon layer, an oxygen burying layer, a gate oxide layer, a high-resistance n-type substrate, a buried p-well, a buried n-well, a p-type detection well, a buried n-well leading-out electrode, a transmission gate electrode, a p-type detection well reading electrode and a back electrode, wherein the low-resistance silicon layer is arranged on the low-resistance silicon layer; wherein the low-resistance silicon layer (circuit layer) and the high-resistance n-type substrate are separated by a buried oxide layer; the buried n-well is surrounded by a deeper buried p-well, and the entire high-resistance n-type substrate is depleted to form a charge sensitive region. The buried n-well of the structure is connected with a proper voltage so as to shield the influence of the substrate voltage on the circuit layer; the larger buried p-well forms a large charge collection and storage region, while the smaller p-type sensing well serves as a sensing region and is connected to the readout electrode, thereby reducing the capacitance of the sensitive node of the SOI pixel sensor.
Description
技术领域technical field
本发明涉及有源像素传感器领域，主要是一种绝缘体上硅(SOI)像素探测器结构。The invention relates to the field of active pixel sensors, and mainly relates to a silicon-on-insulator (SOI) pixel detector structure.
背景技术Background technique
硅像素探测器分为混合型(Hybrid)和单片集成式(Monolithic)两大类。随着辐射探测器的发展，将传感层与电路层整合的单片集成式探测器，成为高性能辐射图像探测器的一种需求，也是对混合型探测器的改进：降低成本和减少物质量。而SOI技术很有希望满足上述要求。Silicon pixel detectors are divided into two categories: Hybrid and Monolithic. With the development of radiation detectors, a monolithic integrated detector that integrates the sensing layer and the circuit layer has become a demand for high-performance radiation image detectors, and it is also an improvement to hybrid detectors: reducing costs and materials. quality. And SOI technology is promising to meet the above requirements.
SOI像素探测器的传感层(高阻衬底)与电路层(低阻Si层)直接集成在单个芯片上，集成度非常高，消除了体硅CMOS的闩锁效应，不需要键合(Bump Bonding)组装工艺，工艺难度和造价得到改善。但SOI像素探测器存在如背栅效应，电路与传感器间的串扰等问题。The sensing layer (high-resistance substrate) and the circuit layer (low-resistance Si layer) of the SOI pixel detector are directly integrated on a single chip, with a very high level of integration, eliminating the latch-up effect of bulk silicon CMOS and requiring no bonding ( Bump Bonding) assembly process, the process difficulty and cost are improved. However, SOI pixel detectors have problems such as back gate effect and crosstalk between circuits and sensors.
文章“F.F.Khalid,G.W.Deptuch,A.Shenai,et al.Monolithic Active PixelMatrix with Binary Counters(MAMBO)ASIC.Nuclear Science Symposium ConferenceRecord NSS/MIC)，2010IEEE.2010,1544-1550.”中提出嵌套阱结构(Nested wellstructure)，该结构可以隔离电路与传感器间的串扰，抑制背栅效应，但P阱结构完全包含电路部分，敏感节点电容较大。公开专利“申请号：CN200910083526.X，高文玉、陈杰、旷章曲，SOICMOS图像传感器结构及其制作方法”给出了一种单片集成式结构，但是与本发明的结构和要解决的问题不相关。Nested well structure proposed in the article "F.F.Khalid, G.W.Deptuch, A.Shenai, et al. Monolithic Active PixelMatrix with Binary Counters (MAMBO) ASIC. Nuclear Science Symposium Conference Record NSS/MIC), 2010IEEE.2010,1544-1550." (Nested well structure), this structure can isolate the crosstalk between the circuit and the sensor and suppress the back gate effect, but the P-well structure completely includes the circuit part, and the sensitive node capacitance is large. The published patent "Application No.: CN200910083526.X, Gao Wenyu, Chen Jie, Kuang Zhangqu, SOICMOS image sensor structure and its manufacturing method" provides a monolithic integrated structure, but it is different from the structure of the present invention and the problems to be solved irrelevant.
为了最大化电荷收集效率，连接读出电极的电荷收集阱需要尽可能的大；然而，好的增益或灵敏度却需要小的敏感节点电容，而相同条件下，小的敏感节点电容要求比较小的电荷收集阱。In order to maximize the charge collection efficiency, the charge collection trap connected to the readout electrode needs to be as large as possible; however, good gain or sensitivity requires a small sensitive node capacitance, and under the same conditions, a small sensitive node capacitance requires a relatively small capacitance charge collection trap.
发明内容SUMMARY OF THE INVENTION
本发明的目的是提供一种拥有较小的敏感节点电容，同时拥有较大的电荷收集区及敏感区电场均匀的SOI像素探测器结构。The purpose of the present invention is to provide a SOI pixel detector structure with smaller sensitive node capacitance, larger charge collection area and uniform electric field in the sensitive area.
本发明的目的是这样实现的：The object of the present invention is achieved in this way:
一种SOI像素探测器结构，包括低阻硅层、埋氧层、栅氧化层、高阻n型衬底、埋p阱、埋n阱、p型探测阱、埋n阱引出电极、传输门电极、p型探测阱读出电极和背部电极；An SOI pixel detector structure, comprising a low-resistance silicon layer, a buried oxide layer, a gate oxide layer, a high-resistance n-type substrate, a buried p-well, a buried n-well, a p-type detection well, a buried n-well lead-out electrode, and a transmission gate electrode, p-type probe well readout electrode and back electrode;
所述的低阻硅层与高阻n型衬底由埋氧层隔开；高阻n型衬底上设有三个埋氧层，三个埋氧层中间通过传输门电极隔开，低阻硅层设置在两侧埋氧层的上方；两个埋氧层下方分别设有反偏埋n阱；反偏埋n阱被埋p阱包围；引出电极穿过低阻硅层、埋氧层连接埋n阱，以屏蔽衬底与电路层之间影响及反偏埋n阱与埋p阱之间形成的二极管；p型探测阱设置在两个埋氧层的下方，p型探测阱设置在中间的埋氧层下方，读出电极穿过埋氧层连接p型探测阱，传输门电极下方设有栅氧化层；高阻n型衬底底部设有背部电极。The low-resistance silicon layer and the high-resistance n-type substrate are separated by a buried oxide layer; the high-resistance n-type substrate is provided with three buried oxygen layers, and the three buried oxide layers are separated by a transmission gate electrode, and the low-resistance n-type substrate is provided with three buried oxygen layers. The silicon layer is arranged above the buried oxide layers on both sides; the reverse-biased buried n-well is respectively provided under the two buried-oxide layers; the reverse-biased buried n-well is surrounded by the buried p-well; the lead-out electrode passes through the low-resistance silicon layer and the buried oxide layer The buried n-well is connected to shield the effect between the substrate and the circuit layer and the diode formed between the reverse-biased buried n-well and the buried p-well; the p-type detection well is arranged under the two buried oxide layers, and the p-type detection well is arranged Below the buried oxide layer in the middle, the readout electrode is connected to the p-type detection well through the buried oxide layer, the gate oxide layer is arranged under the transmission gate electrode, and the back electrode is arranged at the bottom of the high-resistance n-type substrate.
整个高阻n型衬底耗尽为电荷灵敏区；即埋p阱和p型探测阱，前者用于电荷收集和储存，后者用于电荷探测，且两者之间存在防串通掺杂区。The entire high-resistance n-type substrate is depleted into a charge-sensitive region; that is, a buried p-well and a p-type detection well, the former is used for charge collection and storage, the latter is used for charge detection, and there is an anti-cross-talk doped region between the two .
所述的两个p阱为两个n阱，此时，对应的衬底为p型，原反偏埋n阱为p阱。The two p-wells are two n-wells. At this time, the corresponding substrates are p-type, and the originally reverse-biased buried n-wells are p-wells.
所述的作为电荷探测的p型探测阱306远小于用于电荷收集的埋p阱304。The described p-type detection well 306 for charge detection is much smaller than the buried p-well 304 for charge collection.
本发明的有益效果在于：本发明的提供了一种SOI像素探测器结构。该结构保留了屏蔽衬底电压对电路层影响的特点；较大的埋p阱形成一个大的电荷收集和储存区域，在灵敏区形成较均匀的电场，提高电荷收集效率；较小的p型探测阱作为探测区，与读出电极相连，降低SOI像素探测器敏感节点电容。The beneficial effects of the present invention are as follows: the present invention provides an SOI pixel detector structure. The structure retains the characteristics of shielding the influence of the substrate voltage on the circuit layer; the larger buried p-well forms a large charge collection and storage area, which forms a more uniform electric field in the sensitive area and improves the charge collection efficiency; the smaller p-type The detection well is used as a detection area and is connected to the readout electrode to reduce the capacitance of the sensitive node of the SOI pixel detector.
附图说明Description of drawings
图1为已提出的埋p阱SOI像素结构。FIG. 1 shows the proposed buried p-well SOI pixel structure.
图2为已提出的嵌套阱SOI像素结构。Figure 2 shows the proposed nested well SOI pixel structure.
图3是本发明提出的SOI像素结构。FIG. 3 is the SOI pixel structure proposed by the present invention.
图4—图7是本发明实施例的像素结构的具体步骤的示意图。4 to 7 are schematic diagrams of specific steps of a pixel structure according to an embodiment of the present invention.
图8为本发明像素读出信号与收集电荷数量的关系曲线。FIG. 8 is a graph showing the relationship between the pixel readout signal and the amount of collected charges in the present invention.
具体实施方式Detailed ways
下面结合后附图对本发明做进一步描述。The present invention will be further described below in conjunction with the accompanying drawings.
针对图1和图2中SOI像素结构，提出一种既拥有较高探测效率，又拥有较高增益的SOI像素探测器结构，同时保证探测器结构传感器部分与电路层之间的屏蔽性。Aiming at the SOI pixel structure in Figures 1 and 2, a SOI pixel detector structure with high detection efficiency and high gain is proposed, while ensuring the shielding between the sensor part of the detector structure and the circuit layer.
SOI像素结构中，形成两个埋p阱，较大的埋p阱用于形成一个大的电荷收集和储存区域，在灵敏区形成较均匀的电场；较小的p型探测阱作为探测区，与读出电极相连。In the SOI pixel structure, two buried p-wells are formed, the larger buried p-well is used to form a large charge collection and storage area, and a relatively uniform electric field is formed in the sensitive area; the smaller p-type detection well is used as the detection area, connected to the readout electrode.
本发明的技术方案如下：The technical scheme of the present invention is as follows:
根据本发明，一种SOI像素探测器结构，包括低阻硅层301、埋氧层302、栅氧化层302a、高阻n型衬底303、埋p阱304、埋n阱305、p型探测阱306、埋n阱引出电极307、传输门电极308、p型探测阱读出电极309和背部电极310；According to the present invention, an SOI pixel detector structure includes a low-resistance silicon layer 301, a buried oxide layer 302, a gate oxide layer 302a, a high-resistance n-type substrate 303, a buried p-well 304, a buried n-well 305, and a p-type detector. well 306, buried n-well lead-out electrode 307, transmission gate electrode 308, p-type detection well readout electrode 309 and back electrode 310;
所述的低阻硅层301与高阻n型衬底303由埋氧层302隔开；高阻n型衬底303上设有三个埋氧层302，三个埋氧层302中间通过传输门电极308隔开，低阻硅层301设置在两侧埋氧层302的上方；两个埋氧层302下方分别设有反偏埋n阱305；反偏埋n阱305被埋p阱304包围；引出电极307穿过低阻硅层301、埋氧层302连接埋n阱，以屏蔽衬底303与电路层301之间影响及反偏埋n阱305与埋p阱304之间形成的二极管；p型探测阱306设置在两个埋氧层302的下方，p型探测阱306设置在中间的埋氧层302下方，读出电极309穿过埋氧层302连接p型探测阱，传输门电极308下方设有栅氧化层302a；高阻n型衬底303底部设有背部电极310。The low-resistance silicon layer 301 and the high-resistance n-type substrate 303 are separated by a buried oxide layer 302; the high-resistance n-type substrate 303 is provided with three buried oxide layers 302, and the three buried oxide layers 302 pass through a transmission gate in the middle The electrodes 308 are separated, and the low-resistance silicon layer 301 is arranged above the buried oxide layers 302 on both sides; a reverse-biased buried n-well 305 is arranged under the two buried-oxide layers 302 respectively; the reverse-biased buried n-well 305 is surrounded by a buried p-well 304 The lead-out electrode 307 is connected to the buried n-well through the low-resistance silicon layer 301 and the buried oxide layer 302 to shield the diode formed between the substrate 303 and the circuit layer 301 and the diode formed between the reverse-biased buried n-well 305 and the buried p-well 304 The p-type detection well 306 is arranged under the two buried oxide layers 302, the p-type detection well 306 is arranged under the buried oxide layer 302 in the middle, the readout electrode 309 is connected to the p-type detection well through the buried oxide layer 302, and the transmission gate A gate oxide layer 302 a is provided below the electrode 308 ; a back electrode 310 is provided at the bottom of the high-resistance n-type substrate 303 .
实施步骤：Implementation steps:
参考附图描述为示范性实施例。为了清楚地说明的目的，附图中实处的部分被简化或放大。特点层或区域的位置可以表示相对位置，但实际情况不一定与示意图中比例相同。Exemplary embodiments are described with reference to the drawings. For the purpose of clarity of illustration, actual parts in the drawings are simplified or exaggerated. The position of the feature layer or area can represent the relative position, but the actual situation is not necessarily the same as the scale in the schematic diagram.
图1为已提出的埋p阱SOI像素结构。该结构包括低阻硅层(电路层)101、埋氧层102、高阻衬底103、埋p阱或埋n阱104、读出电极105、背部电极106。FIG. 1 shows the proposed buried p-well SOI pixel structure. The structure includes a low-resistance silicon layer (circuit layer) 101 , a buried oxide layer 102 , a high-resistance substrate 103 , a buried p-well or a buried n-well 104 , a readout electrode 105 , and a back electrode 106 .
图2为已提出的嵌套阱SOI像素结构。该结构包括低阻硅层(电路层)201、埋氧层202、高阻n型衬底203、埋p阱204、埋n阱205、读出电极206、埋n阱引出电极207、背部电极208。Figure 2 shows the proposed nested well SOI pixel structure. The structure includes a low-resistance silicon layer (circuit layer) 201, a buried oxide layer 202, a high-resistance n-type substrate 203, a buried p-well 204, a buried n-well 205, a readout electrode 206, a buried n-well lead-out electrode 207, and a back electrode 208.
图3是本发明提出的SOI像素结构。该包括低阻硅层(电路层)301、埋氧层302、栅氧化层302a、高阻n型衬底303、埋p阱304、埋n阱305、p型探测阱306、埋n阱引出电极307、传输门电极308、p型探测阱读出电极309、背部电极310。FIG. 3 is the SOI pixel structure proposed by the present invention. This includes a low-resistance silicon layer (circuit layer) 301, a buried oxide layer 302, a gate oxide layer 302a, a high-resistance n-type substrate 303, a buried p-well 304, a buried n-well 305, a p-type probe well 306, and a buried n-well extraction Electrode 307 , transfer gate electrode 308 , p-type detection well readout electrode 309 , back electrode 310 .
图4-7关注于像素中阱的形成。步骤如下：4-7 focus on the formation of wells in the pixel. Proceed as follows:
SOI材料选取或制备。包括低阻硅层(电路层)301、埋氧层302、高阻n型衬底303。低阻硅层(电路层)301厚度为40纳米，埋氧层302厚度约200纳米，高阻n型衬底303电阻率为1000Ω·cm(根据需求可以选其他规格1000Ω·cm～10000Ω·cm)。SOI material selection or preparation. It includes a low-resistance silicon layer (circuit layer) 301 , a buried oxide layer 302 , and a high-resistance n-type substrate 303 . The thickness of the low-resistance silicon layer (circuit layer) 301 is 40 nanometers, the thickness of the buried oxide layer 302 is about 200 nanometers, and the resistivity of the high-resistance n-type substrate 303 is 1000Ω·cm (other specifications can be selected according to requirements, 1000Ω·cm～10000Ω·cm ).
形成埋p阱304、埋n阱304、p型探测阱306，采用掩膜(mask)光刻技术和离子植入法。The buried p-well 304, the buried n-well 304, and the p-type probe well 306 are formed using mask photolithography and ion implantation.
如图4所示，埋p阱304通过植入硼离子形成，例如能量为150kev剂量为7E11/cm2。As shown in FIG. 4 , the buried p-well 304 is formed by implanting boron ions, for example, the energy is 150kev and the dose is 7E11/cm 2 .
如图5所示，埋n阱305通过植入磷离子形成，例如能量为200kev剂量为5E12/cm2。As shown in FIG. 5 , the buried n-well 305 is formed by implanting phosphorus ions, for example, the energy is 200kev and the dose is 5E12/cm 2 .
所述的埋p阱和埋n阱能量需要控制，使得掺杂浓度峰值位于埋氧层下方。The energy of the buried p-well and buried n-well needs to be controlled so that the peak of the doping concentration is located below the buried oxide layer.
如图6所示，p型探测阱306通过植入硼离子形成，例如能量为60kev剂量为1E15/cm2。As shown in FIG. 6 , the p-type probe well 306 is formed by implanting boron ions, for example, the energy is 60kev and the dose is 1E15/cm 2 .
形成传输门，如图7所示，采用刻蚀技术和干氧氧化，形成传输门栅氧化层302a，例如厚度10纳米，沟道区掺杂，通过植入磷离子调节传输门阈值，例如能量为10kev剂量为4E11/cm2。埋p阱304与p型探测阱306之间通过植入磷离子形成防串通掺杂区域，例如进行两次掺杂，能量分别为200kev和500kev剂量为2E12/cm2。A transmission gate is formed, as shown in FIG. 7, using etching technology and dry oxygen oxidation to form a transmission gate gate oxide layer 302a, for example, with a thickness of 10 nanometers, the channel region is doped, and the threshold of the transmission gate is adjusted by implanting phosphorus ions, such as energy For 10kev the dose is 4E11/cm 2 . Phosphorus ions are implanted between the buried p-well 304 and the p-type probe well 306 to form an anti-collision doping region, for example, doping twice, the energy is 200kev and 500kev respectively, and the dose is 2E12/cm 2 .
形成电极。淀积多晶硅，去掉多余部分，形成传输门电极308。通过刻蚀技术和填充，形成埋n阱引出电极307和p型探测阱读出电极309。背部采用欧姆金属接触形成背部电极310。form electrodes. Polysilicon is deposited and excess portions are removed to form transfer gate electrodes 308 . Buried n-well lead-out electrodes 307 and p-type probe well readout electrodes 309 are formed by etching techniques and filling. The backside uses ohmic metal contacts to form the backside electrode 310 .
图8为本发明像素读出信号与收集电荷数量的关系曲线。转移曲线拥有很好的线性度。FIG. 8 is a graph showing the relationship between the pixel readout signal and the amount of collected charges in the present invention. The transfer curve has good linearity.
以上所述仅为本发明的较佳实施例，并非用以限定本发明。在不脱离本发明的实质和范围内，可做些许的调整和优化，本发明的保护范围以权利要求为准。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Some adjustments and optimizations may be made without departing from the spirit and scope of the present invention, and the protection scope of the present invention is subject to the claims.
Claims (2)
1.一种SOI像素探测器结构，包括低阻硅层(301)、埋氧层(302)、栅氧化层(302a)、高阻n型衬底(303)、埋p阱(304)、反偏埋n阱(305)、p型探测阱(306)、埋n阱引出电极(307)、传输门电极(308)、p型探测阱读出电极(309)和背部电极(310)；1. An SOI pixel detector structure, comprising a low-resistance silicon layer (301), a buried oxide layer (302), a gate oxide layer (302a), a high-resistance n-type substrate (303), a buried p-well (304), Reverse bias buried n-well (305), p-type detection well (306), buried n-well extraction electrode (307), transmission gate electrode (308), p-type detection well readout electrode (309) and back electrode (310); 其特征在于：所述高阻n型衬底(303)顶部的左右两侧各设有一个低阻硅层(301)，两个所述的低阻硅层(301)与高阻n型衬底(303)均由埋氧层(302)隔开；所述高阻n型衬底(303)左右两侧分别设有反偏埋n阱(305)；两个所述反偏埋n阱(305)分别与两个所述低阻硅层(301)位置上下对应，且所述反偏埋n阱(305)与所述低阻硅层(301)由所述埋氧层(302)隔开，所述反偏埋n阱(305)被加深的埋p阱(304)包围；埋n阱引出电极(307)穿过低阻硅层(301)、埋氧层(302)连接埋n阱（305）；两个所述反偏埋n阱(305)之间设有p型探测阱(306)，所述p型探测阱(306)上方设有埋氧层(302)，读出电极(309)穿过埋氧层(302)连接p型探测阱(306)；所述低阻硅层(301)下方的埋氧层(302)与所述p型探测阱(306)上方的埋氧层(302)中间通过传输门电极(308)隔开，传输门电极(308)下方设有栅氧化层(302a)；高阻n型衬底(303)底部设有背部电极(310)；It is characterized in that: a low-resistance silicon layer (301) is provided on the left and right sides of the top of the high-resistance n-type substrate (303), two of the low-resistance silicon layers (301) and the high-resistance n-type substrate The bottom (303) is separated by a buried oxide layer (302); the left and right sides of the high-resistance n-type substrate (303) are respectively provided with reverse-biased buried n-wells (305); two of the reverse-biased buried n-wells (305) respectively correspond to the upper and lower positions of the two low-resistance silicon layers (301), and the reverse-biased buried n-well (305) and the low-resistance silicon layer (301) are formed by the buried oxide layer (302) separated, the reverse-biased buried n-well (305) is surrounded by a deepened buried p-well (304); the buried n-well lead-out electrode (307) is connected to the buried n-well through the low-resistance silicon layer (301) and the buried oxide layer (302) An n-well (305); a p-type detection well (306) is arranged between the two reverse-biased buried n-wells (305), and a buried oxide layer (302) is arranged above the p-type detection well (306). The output electrode (309) is connected to the p-type detection well (306) through the buried oxide layer (302); the buried oxide layer (302) under the low-resistance silicon layer (301) is above the p-type detection well (306) The middle of the buried oxide layer (302) is separated by a transfer gate electrode (308), and a gate oxide layer (302a) is provided under the transfer gate electrode (308); a back electrode (310) is provided at the bottom of the high resistance n-type substrate (303). ); 整个高阻n型衬底(303)耗尽为电荷灵敏区；所述埋n阱引出电极(307)连接电压以屏蔽高阻n型衬底(303)与低阻硅层(301)之间影响及反偏埋n阱(305)与埋p阱(304)之间形成的二极管；所述埋p阱(304)用于电荷收集和储存，所述p型探测阱(306)用于电荷探测，所述埋p阱(304)与所述p型探测阱(306)之间存在防串通掺杂区；The entire high-resistance n-type substrate (303) is depleted into a charge-sensitive area; the buried n-well lead-out electrode (307) is connected to a voltage to shield the gap between the high-resistance n-type substrate (303) and the low-resistance silicon layer (301). Influence and reverse bias the diode formed between the buried n-well (305) and the buried p-well (304); the buried p-well (304) is used for charge collection and storage, and the p-type probe well (306) is used for charge detecting, there is an anti-cross-talk doped region between the buried p-well (304) and the p-type detection well (306); 所述用于电荷探测的p型探测阱(306)小于用于电荷收集的埋p阱(304)。The p-type detection well (306) for charge detection is smaller than the buried p-well (304) for charge collection. 2.根据权利要求1所述的一种SOI像素探测器结构，其特征在于：所述的埋p阱(304)、p型探测阱(306)替换为n阱，反偏埋n阱(305) 替换为p阱，此时，对应的衬底为p型。2. A SOI pixel detector structure according to claim 1, characterized in that: the buried p-well (304) and the p-type detection well (306) are replaced by n-wells, and the reverse-biased buried n-well (305) ) is replaced with p-well, at this time, the corresponding substrate is p-type.
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