CN106788417A - Using the low-noise phase-locked loop circuit of sub-sampling technology - Google Patents

本发明公开了一种采用亚采样技术的低噪声锁相环电路，包括：亚采样环路与锁频环路；其中，亚采样环路包括：亚采样鉴相器、亚采样电荷泵、脉冲发生器、环路滤波器与压控振荡器，所述亚采样鉴相器、亚采样电荷泵、环路滤波器与压控振荡器依次相连，脉冲发生器与亚采样电荷泵相连，亚采样鉴相器与压控振荡器相连；所述锁频环路包括：依次连接的分频器、鉴频鉴相器、死区产生器与电荷泵；所述亚采样环路中的压控振荡器与锁频环路中的分频器相连，所述锁频环路中的电荷泵还与亚采样环路中的环路滤波器相连。该锁相环电路，可以降低锁相环的带内噪声，从而使得无线通信收发机系统的噪声性能以及其他性能得以提升。

The invention discloses a low-noise phase-locked loop circuit adopting sub-sampling technology, comprising: a sub-sampling loop and a frequency-locked loop; wherein, the sub-sampling loop includes: a sub-sampling phase detector, a sub-sampling charge pump, a pulse Generator, loop filter and voltage controlled oscillator, described sub-sampling phase detector, sub-sampling charge pump, loop filter and voltage-controlled oscillator are connected in turn, pulse generator is connected with sub-sampling charge pump, sub-sampling The phase detector is connected with the voltage-controlled oscillator; the frequency-locked loop includes: a frequency divider, a frequency detector, a phase detector, a dead zone generator and a charge pump connected in sequence; the voltage-controlled oscillation in the sub-sampling loop The device is connected to the frequency divider in the frequency-locked loop, and the charge pump in the frequency-locked loop is also connected to the loop filter in the sub-sampling loop. The phase-locked loop circuit can reduce the in-band noise of the phase-locked loop, thereby improving the noise performance and other performances of the wireless communication transceiver system.

采用亚采样技术的低噪声锁相环电路Low Noise PLL Circuit Using Subsampling Technology

技术领域technical field

本发明涉及射频和模拟集成电路技术领域，尤其涉及一种采用亚采样技术的低噪声锁相环电路。The invention relates to the technical field of radio frequency and analog integrated circuits, in particular to a low-noise phase-locked loop circuit using sub-sampling technology.

背景技术Background technique

随着无线通信行业的高速发展及物联网时代到来，人们对无线通信工具的性能要求越来越高。集成电路产业在过去的几十年中迅猛发展，跟随着摩尔定律，集成电路上可容纳的元器件的数目，约每隔18个月便会增加一倍，性能也将提升一倍。With the rapid development of the wireless communication industry and the advent of the Internet of Things era, people have higher and higher performance requirements for wireless communication tools. The integrated circuit industry has developed rapidly in the past few decades. Following Moore's Law, the number of components that can be accommodated on an integrated circuit will double every 18 months, and the performance will also double.

在集成电路设计中，时钟信号很多时候是必不可少的，例如为无线通信收发机提供精确的本振信号。为了得到一个精确的时钟信号，时域上的抖动所对应频域上的相位噪声是其不可忽略的因素之一。降低相位噪声会降低所需信号的信噪比(signal-to-noiseratio，SNR)。所以，一个性能较好的IC设计需要低噪声的时钟信号源。In integrated circuit design, clock signals are often necessary, such as providing accurate local oscillator signals for wireless communication transceivers. In order to obtain an accurate clock signal, the phase noise in the frequency domain corresponding to the jitter in the time domain is one of the factors that cannot be ignored. Reducing phase noise reduces the signal-to-noise ratio (SNR) of the desired signal. Therefore, a better-performing IC design requires a low-noise clock source.

在无线通信收发机中，锁相环电路可以为数据的发送和接收提供精确的时钟信号，其相位噪声性能决定了时钟信号抖动的大小，对于数据发送、接收时信号的噪声性能起着至关重要的作用。In a wireless communication transceiver, a phase-locked loop circuit can provide an accurate clock signal for data transmission and reception, and its phase noise performance determines the size of the clock signal jitter, which plays an important role in the noise performance of the signal during data transmission and reception. important role.

如图1所示，为传统电荷泵锁相环的示意图，其包括：鉴频鉴相器(PFD)、电荷泵(CP)、环路滤波器(LPF)、压控振荡器(VCO)、分频器(Divider)。其噪声模型如图2所示，锁相环的带内噪声主要由PFD/CP的噪声贡献，可以得到PFD/CP的噪声传输函数为：As shown in Figure 1, it is a schematic diagram of a traditional charge pump phase-locked loop, which includes: phase frequency detector (PFD), charge pump (CP), loop filter (LPF), voltage controlled oscillator (VCO), Divider. Its noise model is shown in Figure 2. The in-band noise of the phase-locked loop is mainly contributed by the noise of PFD/CP. The noise transfer function of PFD/CP can be obtained as:

G(s)＝K_d·F_LPF(s)·K_vco/sG(s)＝K _d · F _LPF (s) · K _vco /s

其中，H_PDCP(s)是锁相环的噪声传输函数，φ_out,n是锁相环的输出噪声，φ_PDCP,n是由PFD/CP贡献的噪声,G(s)是PLL开环传递函数，K_d是PFD/CP的线性增益，F_LPF(s)为环路滤波器的增益，K_VCO/s是压控振荡器的增益，N为分频器的分频比。where H _PDCP (s) is the noise transfer function of the PLL, φ _out,n is the output noise of the PLL, φ _PDCP,n is the noise contributed by PFD/CP, and G(s) is the PLL open-loop transfer function, K _d is the linear gain of PFD/CP, F _LPF (s) is the gain of the loop filter, K _VCO /s is the gain of the voltage-controlled oscillator, and N is the frequency division ratio of the frequency divider.

由PFD/CP贡献的带内噪声可以近似为：The in-band noise contributed by PFD/CP can be approximated as:

其中，相位噪声L_inband为传统电荷泵锁相环的噪声功率，S_iPDCP,n表示为由SSPD/SSCP贡献的噪声频率谱密度。由上式可以看出，对于传统的电荷泵锁相环，由于在锁定状态下有分频器的作用，由鉴频鉴相器和电荷泵所产生的带内噪声会被放大N²倍，从而会使锁相环的带内噪声极大程度的增加，这使得传统的电荷泵锁相环的带宽受限，从而会影响收发机系统的整体性能。Among them, the phase noise L _inband is the noise power of the traditional charge pump phase-locked loop, and S _iPDCP,n is expressed as the noise frequency spectral density contributed by SSPD/SSCP. It can be seen from the above formula that for the traditional charge pump phase-locked loop, due to the function of the frequency divider in the locked state, the in-band noise generated by the frequency detector and the charge pump will be amplified by N ² times, As a result, the in-band noise of the phase-locked loop is greatly increased, which limits the bandwidth of the traditional charge-pump phase-locked loop, thereby affecting the overall performance of the transceiver system.

发明内容Contents of the invention

本发明的目的是提供一种采用亚采样技术的低噪声锁相环电路，可以降低锁相环的带内噪声，从而使得模拟时钟电路或无线通信收发机系统的噪声性能以及其他性能得以提升。The purpose of the present invention is to provide a low-noise phase-locked loop circuit using sub-sampling technology, which can reduce the in-band noise of the phase-locked loop, thereby improving the noise performance and other performances of an analog clock circuit or a wireless communication transceiver system.

本发明的目的是通过以下技术方案实现的：The purpose of the present invention is achieved through the following technical solutions:

一种采用亚采样技术的低噪声锁相环电路，包括：亚采样环路与锁频环路；其中，亚采样环路包括：亚采样鉴相器、亚采样电荷泵、脉冲发生器、环路滤波器与压控振荡器，所述亚采样鉴相器、亚采样电荷泵、环路滤波器与压控振荡器依次相连，脉冲发生器与亚采样电荷泵相连，亚采样鉴相器与压控振荡器相连；所述锁频环路包括：依次连接的分频器、鉴频鉴相器、死区产生器与电荷泵；所述亚采样环路中的压控振荡器与锁频环路中的分频器相连，所述锁频环路中的电荷泵还与亚采样环路中的环路滤波器相连。A low-noise phase-locked loop circuit using sub-sampling technology, including: a sub-sampling loop and a frequency-locked loop; wherein, the sub-sampling loop includes: a sub-sampling phase detector, a sub-sampling charge pump, a pulse generator, a loop The circuit filter is connected with the voltage-controlled oscillator, the sub-sampling phase detector, the sub-sampling charge pump, and the loop filter are connected with the voltage-controlled oscillator in sequence, the pulse generator is connected with the sub-sampling charge pump, and the sub-sampling phase detector is connected with the sub-sampling charge pump. The voltage-controlled oscillator is connected; the frequency-locked loop includes: a frequency divider, a frequency and phase detector, a dead zone generator and a charge pump connected in sequence; the voltage-controlled oscillator and the frequency-locked in the sub-sampling loop The frequency divider in the loop is connected, and the charge pump in the frequency-locked loop is also connected with the loop filter in the sub-sampling loop.

当锁相环电路尚未锁定时，亚采样环路与锁频环路同时工作，当输入的参考时钟信号Ref与锁频环路中分频器输出信号Div相位差小于阈值π时，锁频环路中的鉴频鉴相器的输出会掉入死区，使得锁频环路中的电荷泵无法开启，锁频环路停止工作，仅有亚采样环路工作，直至锁相环电路锁定；When the phase-locked loop circuit is not locked, the sub-sampling loop and the frequency-locked loop work at the same time. When the phase difference between the input reference clock signal Ref and the frequency divider output signal Div in the frequency-locked loop is less than the threshold π, the frequency-locked loop The output of the frequency and phase detector in the circuit will fall into the dead zone, so that the charge pump in the frequency-locked loop cannot be turned on, the frequency-locked loop stops working, and only the sub-sampling loop works until the phase-locked loop circuit is locked;

当锁相环电路锁定时，输入的参考时钟信号Ref的上升沿与亚采样环路中压控振荡器输出波形的直流点对齐。When the phase-locked loop circuit is locked, the rising edge of the input reference clock signal Ref is aligned with the DC point of the voltage-controlled oscillator output waveform in the sub-sampling loop.

所述亚采样电荷泵包括：15个MOS管，记为M0～M14；其中，M0、M1、M2、M7、M8、M12、M13与M14均为NMOS管，M3、M4、M5、M6、M9、M10与M11均为PMOS管；The sub-sampling charge pump includes: 15 MOS transistors, denoted as M0-M14; among them, M0, M1, M2, M7, M8, M12, M13 and M14 are all NMOS transistors, M3, M4, M5, M6, M9 , M10 and M11 are PMOS tubes;

连接关系如下：M0的栅端接偏置电压V_bias，漏端接M1、M2的源端，M1、M2的栅端分别接采样输出电压V_sam+、V_sam-，M1、M2的漏端分别接M3、M4的栅端和漏端，M3、M4的栅端分别连接M5、M9的栅端形成电流镜，M5、M6、M7与M8依次连接，M6栅端接GND，M7栅端接VDD，M8的栅端和漏端接M14的栅端形成电流镜，M10、M11、M12与M13的栅端分别连接脉冲产生器产生的输出信号，M3、M4、M5与M9的源端均接VDD，M0、M8与M14的源端均接GND。The connection relationship is as follows: the gate terminal of M0 is connected to the bias voltage V _bias , the drain terminal is connected to the source terminals of M1 and M2, the gate terminals of M1 and M2 are respectively connected to the sampling output voltage V _sam +, V _sam -, and the drain terminals of M1 and M2 Connect the gate and drain terminals of M3 and M4 respectively. The gate terminals of M3 and M4 are respectively connected to the gate terminals of M5 and M9 to form a current mirror. M5, M6, M7 and M8 are connected in sequence. The gate terminal of M6 is connected to GND, and the gate terminal of M7 is connected VDD, the gate terminal and drain terminal of M8 are connected to the gate terminal of M14 to form a current mirror, the gate terminals of M10, M11, M12 and M13 are respectively connected to the output signal generated by the pulse generator, and the source terminals of M3, M4, M5 and M9 are all connected The sources of VDD, M0, M8 and M14 are all connected to GND.

由上述本发明提供的技术方案可以看出，由于消除了传统电荷泵锁相环中分频器对相位噪声的影响，鉴频鉴相器和电荷泵所产生的带内噪声不会被放大N²倍，从而减少锁相环的带内噪声，使得模拟时钟电路或无线通信收发机系统的噪声性能以及其他性能得以提升。As can be seen from the technical scheme provided by the present invention above, due to the elimination of the influence of the frequency divider on the phase noise in the traditional charge pump phase-locked loop, the in-band noise produced by the frequency detector and the charge pump will not be amplified. ² times, thereby reducing the in-band noise of the phase-locked loop, so that the noise performance of the analog clock circuit or the wireless communication transceiver system and other performances can be improved.

附图说明Description of drawings

为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他附图。In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings on the premise of not paying creative work.

图1为本发明背景技术提供的传统电荷泵锁相环的示意图；Fig. 1 is the schematic diagram of the traditional charge pump phase-locked loop provided by the background technology of the present invention;

图2为本发明背景技术提供的传统电荷泵锁相环的噪声模型图；Fig. 2 is the noise model diagram of the traditional charge pump phase-locked loop provided by the background technology of the present invention;

图3为本发明实施例提供的一种采用亚采样技术的低噪声锁相环电路的结构示意图；3 is a schematic structural diagram of a low-noise phase-locked loop circuit using sub-sampling technology provided by an embodiment of the present invention;

图4为本发明实施例提供的亚采样电荷泵晶体管级电路结构示意图；4 is a schematic structural diagram of a sub-sampling charge pump transistor-level circuit provided by an embodiment of the present invention;

图5为本发明实施例提供的亚采样鉴相器与亚采样电荷泵结构示意图；5 is a schematic structural diagram of a subsampling phase detector and a subsampling charge pump provided by an embodiment of the present invention;

图6为本发明实施例提供的采用亚采样技术的低噪声锁相环电路噪声模型示意图；6 is a schematic diagram of a noise model of a low-noise phase-locked loop circuit using sub-sampling technology provided by an embodiment of the present invention;

图7为本发明实施例提供的采用亚采样技术的低噪声锁相环电路(SSPLL)与传统电荷泵锁相环(CPPLL)相位噪声性能对比图。FIG. 7 is a comparison diagram of phase noise performance between a low-noise phase-locked loop circuit (SSPLL) using sub-sampling technology and a traditional charge-pump phase-locked loop (CPPLL) provided by an embodiment of the present invention.

具体实施方式detailed description

下面结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明的保护范围。The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

图3为本发明实施例提供的一种采用亚采样技术的低噪声锁相环电路的结构示意图。如图3所示，其主要包括：亚采样环路(Core Loop)与锁频环路(FLL)；其中，亚采样环路包括：亚采样鉴相器(SSPD)、亚采样电荷泵(SSCP)、脉冲发生器(Pulser)、环路滤波器(LPF)与压控振荡器(VCO)，所述亚采样鉴相器、亚采样电荷泵、环路滤波器与压控振荡器依次相连，脉冲发生器与亚采样电荷泵相连，亚采样鉴相器与压控振荡器相连；所述锁频环路包括：依次连接的分频器(Divider)、鉴频鉴相器(PFD)、死区产生器(Deadzone Creator)与电荷泵(CP)；所述亚采样环路中的压控振荡器与锁频环路中的分频器相连，所述锁频环路中的电荷泵还与亚采样环路中的环路滤波器相连。FIG. 3 is a schematic structural diagram of a low-noise phase-locked loop circuit using sub-sampling technology provided by an embodiment of the present invention. As shown in Figure 3, it mainly includes: a sub-sampling loop (Core Loop) and a frequency-locked loop (FLL); wherein, the sub-sampling loop includes: a sub-sampling phase detector (SSPD), a sub-sampling charge pump (SSCP) ), a pulse generator (Pulser), a loop filter (LPF) and a voltage-controlled oscillator (VCO), the sub-sampling phase detector, sub-sampling charge pump, loop filter and the voltage-controlled oscillator are connected in sequence, The pulse generator is connected with the sub-sampling charge pump, and the sub-sampling phase detector is connected with the voltage-controlled oscillator; Zone generator (Deadzone Creator) and charge pump (CP); The voltage-controlled oscillator in the sub-sampling loop is connected with the frequency divider in the frequency-locked loop, and the charge pump in the frequency-locked loop is also connected with The loop filter in the subsampling loop is connected.

本发明实施例中，在核心的亚采样环路中，压控振荡器的输出信号即为锁相环电路的输出信号Out。压控振荡器的输出信号被亚采样鉴相器采样，采样信号为输入参考信号Ref。如图4所示为亚采样电荷泵晶体管级电路结构示意图，其主要包括15个MOS管，记为M0～M14；其中，M0、M1、M2、M7、M8、M12、M13与M14均为NMOS管，M3、M4、M5、M6、M9、M10与M11均为PMOS管。连接关系如下：M0的栅端接偏置电压V_bias，漏端接M1、M2的源端，M1、M2的栅端分别接采样输出电压V_sam+、V_sam-，M1、M2的漏端分别接M3、M4的栅端和漏端，M3、M4的栅端分别连接M5、M9的栅端形成电流镜，M5、M6、M7与M8依次连接，M6栅端接GND(地)，M7栅端接VDD(电源电压)，M8的栅端和漏端接M14的栅端形成电流镜，M10、M11、M12与M13的栅端分别接由图5所示的脉冲产生器(Pulser)产生的输出信号(Pul+、Pul-、Pul-、Pul+)，由脉冲产生器控制M10、M11、M12与M13的导通与关断。M3、M4、M5与M9的源端均接VDD，M0、M8与M14的源端均接GND。In the embodiment of the present invention, in the core sub-sampling loop, the output signal of the voltage-controlled oscillator is the output signal Out of the phase-locked loop circuit. The output signal of the voltage controlled oscillator is sampled by the sub-sampling phase detector, and the sampling signal is the input reference signal Ref. Figure 4 is a schematic diagram of the sub-sampling charge pump transistor-level circuit structure, which mainly includes 15 MOS transistors, marked as M0~M14; among them, M0, M1, M2, M7, M8, M12, M13 and M14 are all NMOS Tubes, M3, M4, M5, M6, M9, M10 and M11 are all PMOS tubes. The connection relationship is as follows: the gate terminal of M0 is connected to the bias voltage V _bias , the drain terminal is connected to the source terminals of M1 and M2, the gate terminals of M1 and M2 are respectively connected to the sampling output voltage V _sam +, V _sam -, and the drain terminals of M1 and M2 Connect the gate and drain terminals of M3 and M4 respectively. The gate terminals of M3 and M4 are respectively connected to the gate terminals of M5 and M9 to form a current mirror. M5, M6, M7 and M8 are connected in sequence. The gate terminal is connected to VDD (power supply voltage), the gate terminal and drain terminal of M8 are connected to the gate terminal of M14 to form a current mirror, and the gate terminals of M10, M11, M12 and M13 are respectively connected to the pulse generator (Pulser) shown in Figure 5. The output signals (Pul+, Pul-, Pul-, Pul+) of the pulse generator control the on and off of M10, M11, M12 and M13. The source terminals of M3, M4, M5 and M9 are all connected to VDD, and the source terminals of M0, M8 and M14 are all connected to GND.

V_bias为电流源管M0提供偏置电压，可以得到M0漏端电流。M1，M2的漏端分别与M3，M4的漏端相连，使得M3，M4的电流分别与M1，M2相同。M3，M4栅端分别与M5，M9相连形成电流镜，使得M5、M9的电流分别与M3、M4相同。M6、M7的栅端分别接GND、VDD不仅可以降低电压，而且可以用作M10/M11、M12/M13的对称管，从而使得电流镜M8/M14复制更加精确。由M3/M9及M8/M14电流镜复制可以得到I_UP、I_DN。V _bias provides a bias voltage for the current source tube M0, and the drain current of M0 can be obtained. The drain terminals of M1 and M2 are respectively connected to the drain terminals of M3 and M4, so that the currents of M3 and M4 are respectively the same as those of M1 and M2. The gate ends of M3 and M4 are respectively connected with M5 and M9 to form a current mirror, so that the currents of M5 and M9 are the same as those of M3 and M4 respectively. The gate terminals of M6 and M7 are connected to GND and VDD respectively, which can not only reduce the voltage, but also can be used as a symmetrical tube of M10/M11, M12/M13, so that the replication of current mirror M8/M14 is more accurate. I _UP and I _DN can be obtained by duplicating the M3/M9 and M8/M14 current mirrors.

如图5所示，电流输入管将采样电压转换为电流，通过电流镜将电流复制，就可以得到亚采样电荷泵的上下电流I_UP＝g_m*V_sam+，I_DN＝g_m*V_sam-，其中g_m为输入管的跨导。当锁相环电路时，采样电压V_sam+＝V_sam-，所以可以得到I_UP＝I_DN，从而由亚采样电荷泵输入到环路滤波器的电流icp＝0，环路滤波器的电压保持不变，从而VCO的输出频率不变。As shown in Figure 5, the current input tube converts the sampling voltage into a current, and the current is copied through the current mirror to obtain the upper and lower currents of the sub-sampling charge pump I _UP =g _m *V _sam +, I _DN =g _m *V _sam -, where g _m is the transconductance of the input tube. In the phase-locked loop circuit, the sampling voltage V _sam + = V _sam -, so I _UP = I _DN can be obtained, so that the current icp input to the loop filter by the sub-sampling charge pump = 0, the voltage of the loop filter remains unchanged, so that the output frequency of the VCO remains unchanged.

但是如果仅使用核心电路，由于亚采样鉴相器的捕获范围有限，在采样的过程中，采样器无法区分采样频率是所需的N·f_REF或是f_REF的其它谐波，故加入锁频环路可以得到所需的锁定频率N·f_REF。当锁相环电路尚未锁定时，亚采样环路与锁频环路同时工作；其中的锁频环路起主要作用，将VCO的输出频率调节接近至N·f_REF频率处。当输入的参考时钟信号Ref与锁频环路中分频器输出信号Div相位差小于阈值π时，锁频环路中的鉴频鉴相器的输出会掉入死区，使得锁频环路中的电荷泵无法开启，电荷泵的输出电流为0，锁频环路停止工作，仅有亚采样环路工作，直至锁相环电路锁定。However, if only the core circuit is used, due to the limited capture range of the sub-sampling phase detector, during the sampling process, the sampler cannot distinguish whether the sampling frequency is the required N f _REF or other harmonics of f _REF , so a lock is added The frequency loop can get the required locking frequency N·f _REF . When the phase-locked loop circuit is not locked, the sub-sampling loop and the frequency-locked loop work at the same time; the frequency-locked loop plays a major role, adjusting the output frequency of the VCO close to the N·f _REF frequency. When the phase difference between the input reference clock signal Ref and the frequency divider output signal Div in the frequency-locked loop is less than the threshold π, the output of the frequency and phase detector in the frequency-locked loop will fall into the dead zone, making the frequency-locked loop The charge pump in the circuit cannot be turned on, the output current of the charge pump is 0, the frequency-locked loop stops working, and only the sub-sampling loop works until the phase-locked loop circuit is locked.

当锁相环电路锁定时，输入的参考时钟信号Ref的上升沿与亚采样环路中压控振荡器输出波形的直流点对齐。When the phase-locked loop circuit is locked, the rising edge of the input reference clock signal Ref is aligned with the DC point of the voltage-controlled oscillator output waveform in the sub-sampling loop.

如图5所示的亚采样鉴相器与亚采样电荷泵结构示意图，经过亚采样鉴相器采样给电容C_sam充电，当MOS管关断时，电容C_sam可以保持一个恒定的电压。通过亚采样电荷泵将采样后电容C_sam的电压转化为电荷泵的上下电流I_UP和I_DN。当Ref采样得到的电压相等时，可以得到亚采样电荷泵的上下电流相等，没有电流流入环路滤波器，从而输出电压保持恒定，环路锁定。As shown in Figure 5, the sub-sampling phase detector and the sub-sampling charge pump structure schematic diagram, through the sub-sampling phase detector to charge the capacitor C _sam , when the MOS tube is turned off, the capacitor C _sam can maintain a constant voltage. The voltage of the sampled capacitor C _sam is converted into the upper and lower currents I _UP and I _DN of the charge pump through the sub-sampling charge pump. When the voltages sampled by Ref are equal, the upper and lower currents of the sub-sampled charge pump are equal, and no current flows into the loop filter, so the output voltage remains constant and the loop is locked.

此外，根据前文背景技术中提到的噪声L_inband计算公式来看，较大的PFD/CP增益及较小的分频比会得到更优的噪声性能；具体到本发明实施例的方案中，当环路锁定时，FLL不工作，所以锁相环电路的噪声模型可以简化成如图6所示。其中，K_d是SSPD/SSCP的线性增益，F_LPF(s)是环路滤波器的增益，Kvco/s是VCO的增益；φ_Ref,n是由参考源贡献的噪声,φ_SSPDCP,n是由SSPD/SSCP贡献的噪声,φ_LPF,n是由环路滤波器贡献的噪声,φ_VCO,n是由VCO贡献的噪声,φ_out,n是SSPLL的输出噪声。从而可以得到SSPD/SSCP的噪声传输函数为：In addition, according to the noise L _inband calculation formula mentioned in the previous background technology, a larger PFD/CP gain and a smaller frequency division ratio will obtain better noise performance; specifically in the solution of the embodiment of the present invention, When the loop is locked, the FLL does not work, so the noise model of the PLL circuit can be simplified as shown in Figure 6. where K _d is the linear gain of SSPD/SSCP, F _LPF (s) is the gain of the loop filter, Kvco/s is the gain of the VCO; φ _Ref,n is the noise contributed by the reference source, φ _SSPDCP,n is The noise contributed by SSPD/SSCP, φ _LPF,n is the noise contributed by the loop filter, φ _VCO,n is the noise contributed by the VCO, φ _out,n is the output noise of the SSPLL. Thus, the noise transfer function of SSPD/SSCP can be obtained as:

G(s)＝K_d·F_LPF(s)·K_vco/s；G(s)＝K _d F _LPF (s) K _vco /s;

其中，H_SSPDCP(s)是SSPLL的噪声传输函数，G(s)是SSPLL开环传递函数。where H _SSPDCP (s) is the noise transfer function of the SSPLL, and G(s) is the SSPLL open-loop transfer function.

由SSPD/SSCP贡献的带内噪声可以近似为：The in-band noise contributed by SSPD/SSCP can be approximated as:

其中，相位噪声L_inband为SSPLL的噪声功率，S_iSSPDCP,n表示为由SSPD/SSCP贡献的噪声频率谱密度。由于少了分频器的噪声，SSPD/SSCP对整个环路贡献的噪声不会被放大N²倍，使得锁相环的带内噪声大幅度减小，从而解决传统电荷泵锁相环中鉴频鉴相器和电荷泵所产生的带内噪声被放大N²倍的问题。Among them, the phase noise L _inband is the noise power of SSPLL, and S _iSSPDCP,n is expressed as the noise frequency spectral density contributed by SSPD/SSCP. Due to the lack of noise from the frequency divider, the noise contributed by SSPD/SSCP to the entire loop will not be amplified by N ² times, so that the in-band noise of the phase-locked loop is greatly reduced, thus solving the problem of traditional charge pump phase-locked loop The in-band noise generated by the frequency phase detector and the charge pump is amplified by N ² times.

另外，还将本发明实施例提供的采用亚采样技术的低噪声锁相环电路(SSPLL)与传统电荷泵锁相环(CPPLL)的相位噪声性能进行了对比，对比结果如图7所示；从图7中可以明显看出本发明提供的采用亚采样技术的低噪声锁相环电路带内噪声性能有很大程度提升。In addition, the phase noise performance of the low-noise phase-locked loop circuit (SSPLL) using the sub-sampling technology provided by the embodiment of the present invention is compared with the phase noise performance of the traditional charge pump phase-locked loop (CPPLL), and the comparison results are shown in Figure 7; It can be clearly seen from FIG. 7 that the in-band noise performance of the low-noise phase-locked loop circuit using the sub-sampling technology provided by the present invention is greatly improved.

以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明披露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求书的保护范围为准。The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person familiar with the technical field can easily conceive of changes or changes within the technical scope disclosed in the present invention. Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.