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CN106815801B - Median filter circuit structure and median acquisition method - Google Patents

  • ️Fri May 15 2020
中值滤波器电路结构及中值获取方法Median filter circuit structure and median acquisition method

技术领域technical field

本发明涉及数字集成电路技术领域,具体涉及一种中值滤波器电路结构以及获取中值的方法。The invention relates to the technical field of digital integrated circuits, in particular to a circuit structure of a median filter and a method for obtaining the median.

背景技术Background technique

中值滤波是在数字图像处理和信号处理中常用的非线性滤波技术。在数字图像处理中,与常用的均值滤波,高斯滤波和维纳滤波等一起构成了常见的图像优化和预处理方法。中值滤波主要用于对椒盐噪声进行处理。在CIS图像处理电路中的出现的坏点,因其输出特性与椒盐噪声相似,所以常用中值滤波器进行预处理。中值滤波算法,现已得到极大优化,其中基于均值加速的快速中值滤波和自适应的中值滤波技术已取得较好的效果。但对于数字电路,常用的中值滤波结构依旧为两类:Median filtering is a nonlinear filtering technique commonly used in digital image processing and signal processing. In digital image processing, together with the commonly used mean filtering, Gaussian filtering and Wiener filtering, it constitutes a common image optimization and preprocessing method. The median filter is mainly used to deal with salt and pepper noise. The bad pixels that appear in the CIS image processing circuit are often preprocessed by median filter because their output characteristics are similar to salt and pepper noise. The median filtering algorithm has been greatly optimized, among which the fast median filtering based on mean acceleration and the adaptive median filtering technology have achieved good results. But for digital circuits, the commonly used median filter structures are still two types:

第一类,存在对深度为N的数据进行寄存的缓冲区,并添加深度为N的大小数据寄存器,用于存储N个数据的大小顺序。通过排序确认顺序,并最终确认中值即为大小数据寄存器中(N+1)/2对应的那个数据。In the first category, there is a buffer for registering data with a depth of N, and a size data register with a depth of N is added to store the size sequence of the N data. Confirm the order by sorting, and finally confirm that the median value is the data corresponding to (N+1)/2 in the size data register.

第二类,存在对深度为N的数据进行寄存的缓冲区,并添加深度为N的进出顺序寄存器。N个数据按顺序进行排列,当新数据进入时,最新的,最新的N个数据按大小重新排序,更新当前N个数据的先后顺序。In the second category, there is a buffer that registers data of depth N, and an in-out sequence register of depth N is added. The N pieces of data are arranged in order. When new data comes in, the newest and latest N pieces of data are reordered by size, and the order of the current N pieces of data is updated.

现有的方法中,对第一类中值滤波结构进行优化,将数据存储设备的深度从N个减少为N-1个,从而实现更小的电路面积。但是这引入了不必要的数据重排电路,电路结构依旧存在优化空间。In the existing method, the first type of median filtering structure is optimized to reduce the depth of data storage devices from N to N-1, thereby achieving a smaller circuit area. However, this introduces unnecessary data rearrangement circuits, and there is still room for optimization of the circuit structure.

发明内容SUMMARY OF THE INVENTION

为了克服以上问题,本发明旨在提供一种中值滤波器电路结构,从而减小逻辑电路的复杂度。In order to overcome the above problems, the present invention aims to provide a median filter circuit structure, thereby reducing the complexity of the logic circuit.

为了达到上述目的,本发明提供了一种中值滤波器电路结构,其特征在于,包括:数据寄存器、比较及排序电路、位宽增加电路和生命周期衰减及终结电路;所述中值滤波器电路结构用于对N个m bit位数据进行中值滤波,N为大于等于2的整数;m为大于等于1的整数;其中,In order to achieve the above object, the present invention provides a median filter circuit structure, which is characterized in that it includes: a data register, a comparison and sorting circuit, a bit width increase circuit, and a life cycle attenuation and termination circuit; the median filter The circuit structure is used to perform median filtering on N m bit data, where N is an integer greater than or equal to 2; m is an integer greater than or equal to 1; among them,

数据寄存器,用于存寄存上一周期按大小顺序排列的N-1个数据;The data register is used to store and register the N-1 data arranged in the order of size in the previous cycle;

位宽增加电路,接收第N个数据,将第N个数据的m bit位的位宽增加n bit数据位,得到增加后的n+m bit位,并将高n bit位设置初始值N,低m bit位保持不变,并将增加位宽后的第N个数据发送给比较及排序电路;The bit width increasing circuit receives the Nth data, increases the bit width of the m bits of the Nth data by n bits, and obtains the increased n+m bits, and sets the high n bits to the initial value N, The lower m bits remain unchanged, and the Nth data after increasing the bit width is sent to the comparison and sorting circuit;

比较及排序电路,用于对位宽增加电路输出的增加位宽后的第N个数据与数据寄存器中的N-1个按大小顺序排列的数据进行比较,确定增加位宽后的第N个数据的位置,从而生成新的顺序,并输出到生命周期衰减及终结电路中;The comparison and sorting circuit is used to compare the N-th data after the increased bit width output by the bit-width increasing circuit with the N-1 data in the data register arranged in order of size, and determine the N-th data after the increased bit width. The location of the data, thereby generating a new sequence and outputting it to the life cycle decay and termination circuit;

生命周期衰减及终结电路,用于对接收到的所有数据高n bit位减去2m,以完成高n bit位的衰减,并删除其中高n bit位为0的那组数据,完成数据的衰减和终结,将其余数据存入数据寄存器中,以为下一周期备用。The life cycle attenuation and termination circuit is used to subtract 2 m from the high n bits of all received data to complete the attenuation of the high n bits, and delete the group of data in which the high n bits are 0 to complete the data processing. Attenuate and terminate, and store the rest of the data in the data register for use in the next cycle.

优选地,增加的n bit数据位为生命周期bit位,用于表征数据在整个中值滤波器中的存在时间;生命周期bit位预置值为N,每进行一次大小顺序比较和排序,生命周期bit位减1,当其值变为0时,该数据的生命终结,清除出整个中值滤波器,以此保证上一周期寄存的数据量一直为N-1;各数据的生命周期bit位大小为1~N-1。Preferably, the added n bits of data bits are life cycle bits, which are used to represent the existence time of data in the entire median filter; the preset value of the life cycle bit bits is N, and each time the size order is compared and sorted, the life cycle The cycle bit is decremented by 1. When its value becomes 0, the life of the data ends, and the entire median filter is cleared, so as to ensure that the amount of data registered in the previous cycle is always N-1; the life cycle bit of each data The bit size is 1 to N-1.

优选地,生命周期衰减及终结电路中的数据的位宽为n,并且,N与n的关系为2(n-1)≤N≤2n,n为大于等于1的整数。Preferably, the bit width of the data in the lifetime decay and termination circuit is n, and the relationship between N and n is 2 (n-1) ≤N≤2 n , where n is an integer greater than or equal to 1.

优选地,增加位宽后的第N个数据的位宽为m+n,总的寄存器消耗为(m+n)*(N-1)。Preferably, the bit width of the Nth data after increasing the bit width is m+n, and the total register consumption is (m+n)*(N-1).

优选地,所述数据寄存器的总位宽为m+n。Preferably, the total bit width of the data register is m+n.

为了达到上述目的,本发明还提供了一种采用上述的中值滤波器电路结构来获取中值的方法,其包括:In order to achieve the above object, the present invention also provides a method for obtaining the median value by adopting the above-mentioned median filter circuit structure, which includes:

步骤01:在上一周期快结束时,生命周期衰减及终结电路将完成衰减和终结后的数据,依序存入数据寄存器中,以为下一周期备用;Step 01: When the previous cycle is about to end, the life cycle decay and termination circuit will store the data after the decay and termination in sequence in the data register for the next cycle;

步骤02:下一周期刚开始,位宽增加电路接收第N个数据,并增加该第N个数据的位宽,然后将增加位宽后的第N个数据发送给比较及排序电路;Step 02: at the beginning of the next cycle, the bit width increasing circuit receives the Nth data, increases the bit width of the Nth data, and then sends the Nth data after the increased bit width to the comparison and sorting circuit;

步骤03:比较及排序电路将增加位宽后的第N个数据与数据寄存器中的N-1个按大小顺序排列的数据进行比较,确定增加位宽后的第N个数据的位置,从而生成新的顺序,然后输出到生命周期衰减及终结电路中;Step 03: The comparison and sorting circuit compares the Nth data after increasing the bit width with the N-1 data in the data register arranged in order of size, and determines the position of the Nth data after increasing the bit width, thereby generating The new sequence is then output to the life cycle decay and termination circuit;

步骤04:生命周期衰减及终结电路对接收到的所有数据高n bit位减去2m,以完成高n bit位的衰减,并删除其中高n bit位为0的那组数据,完成数据的衰减和终结,将其余数据存入数据寄存器中,以为下一周期备用;Step 04: The life cycle attenuation and termination circuit subtracts 2 m from the high n bits of all received data to complete the attenuation of the high n bits, and deletes the group of data in which the high n bits are 0, and completes the data processing. Attenuate and terminate, and store the remaining data in the data register for use in the next cycle;

步骤05:重复步骤01~04,直至完成N个周期循环。根据权利要求5所述的获取中值的方法,其特征在于,步骤04中,生命周期衰减及终结电路中所采用的数据位宽为n,并且,N与n的关系为2(n-1)≤N≤2n,n为大于等于1的整数。Step 05: Repeat steps 01 to 04 until N cycles are completed. The method for obtaining a median value according to claim 5, wherein in step 04, the data bit width used in the life cycle decay and termination circuit is n, and the relationship between N and n is 2 (n-1 ) ≤N≤2 n , where n is an integer greater than or equal to 1.

优选地,所增加的n bit数据位为生命周期bit位,用于表征数据在整个中值滤波器中的存在时间;生命周期bit位预置值为N,每进行一次大小顺序比较和排序,生命周期bit位减1,当其值变为0时,该数据的生命终结,清除出整个中值滤波器,以此保证上一周期寄存的数据量一直为N-1;各数据的生命周期bit位大小为1~N-1。Preferably, the added n bit data bits are life cycle bits, which are used to represent the existence time of the data in the entire median filter; the preset value of the life cycle bit bits is N, and each time a size order comparison and sorting are performed, The life cycle bit is decremented by 1. When its value becomes 0, the life of the data ends, and the entire median filter is cleared, so as to ensure that the amount of data registered in the previous cycle is always N-1; the life cycle of each data The bit size is 1 to N-1.

优选地,步骤02中,增加位宽后的第N个数据的位宽为m+n,总的寄存器消耗为(m+n)*(N-1)。Preferably, in step 02, the bit width of the Nth data after increasing the bit width is m+n, and the total register consumption is (m+n)*(N-1).

优选地,所采用的数据寄存器的总位宽为m+n。Preferably, the total bit width of the used data registers is m+n.

本发明克服了现有中值滤波器消耗寄存器资源高,电路复杂度高的缺点,本发明的电路结构在减小寄存器资源消耗的基础上,减小逻辑电路的复杂度,使得其能够适应更高的时钟速度。The invention overcomes the shortcomings of high consumption of register resources and high circuit complexity of the existing median filter. The circuit structure of the invention reduces the complexity of the logic circuit on the basis of reducing the consumption of register resources, so that it can adapt to more high clock speed.

附图说明Description of drawings

图1为本发明的一个较佳实施例的数据寄存器的结构示意图1 is a schematic structural diagram of a data register according to a preferred embodiment of the present invention

图2为本发明的一个较佳实施例的中值滤波电路结构的示意图2 is a schematic diagram of the structure of a median filter circuit according to a preferred embodiment of the present invention

图3为本发明的一个较佳实施例的获取中值的方法的流程示意图3 is a schematic flowchart of a method for obtaining a median value according to a preferred embodiment of the present invention

图4为本发明的一个较佳实施例的N为5和m为8时的中值滤波器电路结构的示意图4 is a schematic diagram of the circuit structure of the median filter when N is 5 and m is 8 according to a preferred embodiment of the present invention

具体实施方式Detailed ways

为使本发明的内容更加清楚易懂,以下结合说明书附图,对本发明的内容作进一步说明。当然本发明并不局限于该具体实施例,本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below with reference to the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general substitutions known to those skilled in the art are also covered within the protection scope of the present invention.

以下结合附图1~4和具体实施例对本发明作进一步详细说明。需说明的是,附图均采用非常简化的形式、使用非精准的比例,且仅用以方便、清晰地达到辅助说明本实施例的目的。The present invention will be further described in detail below in conjunction with accompanying drawings 1-4 and specific embodiments. It should be noted that, the accompanying drawings are in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly achieve the purpose of assisting the description of the present embodiment.

请参阅图1~2,本实施例中,一种中值滤波器电路结构包括:数据寄存器、比较及排序电路、位宽增加电路和生命周期衰减及终结电路。本实施例中,中值滤波器电路结构用于对N个m bit位数据进行中值滤波,N为大于等于2的整数;m为大于等于1的整数。Please refer to FIGS. 1-2. In this embodiment, a median filter circuit structure includes: a data register, a comparison and sorting circuit, a bit width increase circuit, and a life cycle attenuation and termination circuit. In this embodiment, the median filter circuit structure is used to perform median filtering on N m-bit data, where N is an integer greater than or equal to 2; m is an integer greater than or equal to 1.

数据寄存器,请参阅图1,用于存寄存上一周期按大小顺序排列的N-1个数据;这里的数据寄存器的总位宽为m+n。The data register, please refer to Figure 1, is used to store and register N-1 data arranged in order of size in the previous cycle; the total bit width of the data register here is m+n.

请参阅图2,位宽增加电路,接收第N个数据,将第N个数据的m bit位的位宽增加nbit数据位,得到增加后的n+m bit位,并将高n bit位设置初始值N,低m bit位保持不变,并将增加位宽后的第N个数据发送给比较及排序电路;这里,增加位宽后的第N个数据的位宽为m+n,总的寄存器消耗为(m+n)*(N-1)。这里,所增加的n bit数据位为生命周期bit位,用于表征数据在整个中值滤波器中的存在时间;生命周期bit位预置值为N,每进行一次大小顺序比较和排序,生命周期bit位减1,当其值变为0时,该数据的生命终结,清除出整个中值滤波器,以此保证上一周期寄存的数据量一直为N-1;各数据的生命周期bit位大小为1~N-1。Please refer to Figure 2, the bit width increase circuit, receives the Nth data, increases the bit width of the m bit bit of the Nth data by nbit data bits, obtains the increased n+m bit bits, and sets the high n bits The initial value N, the lower m bits remain unchanged, and the Nth data after the increased bit width is sent to the comparison and sorting circuit; here, the bit width of the Nth data after the increased bit width is m+n, and the total The register consumption is (m+n)*(N-1). Here, the added n bit data bits are the life cycle bits, which are used to represent the existence time of the data in the entire median filter; the preset value of the life cycle bit bits is N. The cycle bit is decremented by 1. When its value becomes 0, the life of the data ends, and the entire median filter is cleared, so as to ensure that the amount of data registered in the previous cycle is always N-1; the life cycle bit of each data The bit size is 1 to N-1.

请参阅图2,比较及排序电路,用于对位宽增加电路输出的增加位宽后的第N个数据与数据寄存器中的N-1个按大小顺序排列的数据进行比较,确定增加位宽后的第N个数据的位置,从而生成新的顺序,并输出到生命周期衰减及终结电路中;Please refer to Figure 2, the comparison and sorting circuit is used to compare the Nth data after the increased bit width output by the bit width increasing circuit with the N-1 data in the data register arranged in order of size to determine the increased bit width The position of the next Nth data, thereby generating a new sequence, and outputting it to the life cycle decay and termination circuit;

请参阅图2,生命周期衰减及终结电路,用于对接收到的所有数据高n bit位减去2m,以完成高n bit位的衰减,并删除其中高n bit位为0的那组数据,完成数据的衰减和终结,将其余数据存入数据寄存器中,以为下一周期备用。这里的生命周期衰减及终结电路中的数据的位宽为n,,n为大于等于1的整数,并且,N与n的关系为2(n-1)≤N≤2nPlease refer to Figure 2, the life cycle attenuation and termination circuit is used to subtract 2 m from the high n bits of all received data to complete the attenuation of the high n bits, and delete the group in which the high n bits are 0 data, complete the attenuation and termination of the data, and store the rest of the data in the data register for use in the next cycle. Here, the bit width of the data in the life cycle decay and termination circuit is n, where n is an integer greater than or equal to 1, and the relationship between N and n is 2 ( n -1) ≤N≤2n.

此外,请参阅图3,本实施例中的采用上述的中值滤波器电路结构来获取中值的方法,包括:In addition, referring to FIG. 3 , the method for obtaining the median value using the above-mentioned median filter circuit structure in this embodiment includes:

步骤01:在上一周期快结束时,生命周期衰减及终结电路将完成衰减和终结后的数据,依序存入数据寄存器中,以为下一周期备用;Step 01: When the previous cycle is about to end, the life cycle decay and termination circuit will store the data after the decay and termination in sequence in the data register for the next cycle;

这里采用的数据寄存器的总位宽为m+n。The total bit width of the data register used here is m+n.

步骤02:下一周期刚开始,位宽增加电路接收第N个数据,并增加该第N个数据的位宽,然后将增加位宽后的第N个数据发送给比较及排序电路;Step 02: at the beginning of the next cycle, the bit width increasing circuit receives the Nth data, increases the bit width of the Nth data, and then sends the Nth data after the increased bit width to the comparison and sorting circuit;

具体的,增加位宽后的第N个数据的位宽为m+n,总的寄存器消耗为(m+n)*(N-1)。Specifically, the bit width of the Nth data after increasing the bit width is m+n, and the total register consumption is (m+n)*(N-1).

步骤03:比较及排序电路将增加位宽后的第N个数据与数据寄存器中的N-1个按大小顺序排列的数据进行比较,确定增加位宽后的第N个数据的位置,从而生成新的顺序,然后输出到生命周期衰减及终结电路中;Step 03: The comparison and sorting circuit compares the Nth data after increasing the bit width with the N-1 data in the data register arranged in order of size, and determines the position of the Nth data after increasing the bit width, thereby generating The new sequence is then output to the life cycle decay and termination circuit;

步骤04:生命周期衰减及终结电路对接收到的所有数据高n bit位减去2m,以完成高n bit位的衰减,并删除其中高n bit位为0的那组数据,完成数据的衰减和终结,将其余数据存入数据寄存器中,以为下一周期备用;Step 04: The life cycle attenuation and termination circuit subtracts 2 m from the high n bits of all received data to complete the attenuation of the high n bits, and deletes the group of data in which the high n bits are 0, and completes the data processing. Attenuate and terminate, and store the remaining data in the data register for use in the next cycle;

具体的,生命周期衰减及终结电路中所采用的数据位宽为n,并,n为大于等于1的整数,且,N与n的关系为2(n-1)≤N≤2nSpecifically, the data bit width used in the life cycle decay and termination circuit is n, and n is an integer greater than or equal to 1, and the relationship between N and n is 2 ( n -1) ≤N≤2n.

步骤05:重复步骤01~04,直至完成N个周期循环。Step 05: Repeat steps 01 to 04 until N cycles are completed.

需要说明的是,本实施例中,可以采用时钟来控制每个周期。It should be noted that, in this embodiment, a clock may be used to control each cycle.

请参阅图4,以下以N=5,m=8为例来详细描述上述的中值滤波器电路结构及其工作方法。通过运算得到n=3,则m+n=11。Referring to FIG. 4 , the above-mentioned median filter circuit structure and its working method are described in detail below by taking N=5 and m=8 as an example. Through the operation, n=3 is obtained, then m+n=11.

假设上一时钟周期寄存数据为:4ffH,11eH,210H和308H(16进制数据,按从大到小的数据进行排列),输入数据DS5=0fH。参见图4所示的电路结构及相关说明。Assuming that the registered data in the previous clock cycle are: 4ffH, 11eH, 210H and 308H (hexadecimal data, arranged in descending order), the input data DS5=0fH. Refer to the circuit structure and related descriptions shown in FIG. 4 .

输入数据DS5经过位宽增加模块,增加位宽后,模块输出DS5=50fH。The input data DS5 passes through the bit width increasing module, after increasing the bit width, the module outputs DS5=50fH.

比较及排序电路对数据寄存器中的寄存数据和输入数据DS5进行比较,根据比较输出结果,判断DS5插入的位置,并在同时输出中值数据,根据系统要求,决定是否对生命周期为3的数据即308H进行中值替换,变为310H。在图4中,根据比较结果,按顺序依次为4ffH,11eH,210H,50fH,308H(不进行数据替换)或310H(进行数据替换)。The comparison and sorting circuit compares the registered data in the data register with the input data DS5, judges the insertion position of DS5 according to the comparison output result, and outputs the median data at the same time. That is, the median value of 308H is replaced, and it becomes 310H. In FIG. 4, according to the comparison result, the sequence is 4ffH, 11eH, 210H, 50fH, 308H (without data replacement) or 310H (with data replacement).

生命周期衰减及终结电路进行衰减和终结,生命周期bit位同时减1,数据变为3ffH,01eH,110H,208H或210H。判断生命周期为0的数据为01eH,将其终结。其余数据按顺序存入数据寄存器中,依次为3ffH,110H,40fH,208H或210H,备下一周期使用。The life cycle decay and termination circuit is attenuated and terminated, the life cycle bit is decremented by 1 at the same time, and the data becomes 3ffH, 01eH, 110H, 208H or 210H. It is judged that the data whose life cycle is 0 is 01eH, and it is terminated. The rest of the data are stored in the data register in sequence, 3ffH, 110H, 40fH, 208H or 210H, for use in the next cycle.

虽然本发明已以较佳实施例揭示如上,然实施例仅为了便于说明而举例而已,并非用以限定本发明,本领域的技术人员在不脱离本发明精神和范围的前提下可作若干的更动与润饰,本发明所主张的保护范围应以权利要求书为准。Although the present invention has been disclosed above with preferred embodiments, the embodiments are merely examples for the convenience of description, and are not intended to limit the present invention. Those skilled in the art can make several modifications without departing from the spirit and scope of the present invention. Changes and modifications, the scope of protection claimed by the present invention shall be subject to the claims.