CN107358914B - A kind of emission control circuit, its driving method, display panel and display device - Google Patents

The invention discloses a kind of emission control circuit, its driving method, display panel and display device, emission control circuit includes: multiple cascade shift registers, and the input signal end of first order shift register is connected with initial signal end；Initial signal end has the frame start signal of the significant level of setting duration to the input of first order shift register.When being adjusted to display panel brightness, the duration for extending or shortening the significant level of frame start signal on the basis of current frame start signal using 4N unit time as step-length makes the LED control signal of shift register outputs at different levels accordingly extend or shorten the duration of identical significant level.When adjusting the significant level duration of frame start signal as step-length using 4N unit time, the variation of step can occur to avoid the brightness of display panel, keep the brightness regulation of display panel smoother, display brightness is more evenly.

Light-emitting control circuit, driving method thereof, display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a light emitting control circuit, a driving method thereof, a display panel and a display device.

Background

Organic Light Emitting Diodes (OLEDs) are a hotspot in the research field of Display panels at present, and compared with Liquid Crystal Displays (LCDs), OLED displays have the advantages of low energy consumption, self-luminescence, wide viewing angle, fast response speed, and the like. Currently, in the display fields of mobile phones, tablet computers, digital cameras, and the like, OLED displays have begun to replace traditional LCD displays. Unlike LCDs, which control brightness using voltage, OLEDs are current driven and require a steady current to control their light emission. In general, the OLED display drives the OLED to emit light through a driving transistor in a pixel circuit. While the pixel circuit generally requires a gate driving signal and a light emitting control signal to drive simultaneously, a row of OLED pixels may require a plurality of gate driving signals to drive, and the light emitting control signal is generated by the light emitting control circuit.

At present, many OLED display panels also adopt a dimming mode to adjust the display brightness, and the purpose of adjusting the display brightness is achieved by adjusting the light emitting time of each pixel under the condition that the input value of the data signal voltage can be kept unchanged in the dimming mode. The light emitting time of the pixel is determined by the light emitting control signal, and the light emitting time of the pixel in one frame is longer as the duty ratio of the effective pulse of the light emitting control signal is larger. In the current OLED display panel, the light emitting control signal is generated by a light emitting control circuit. Since the light-emitting control circuit is usually composed of cascaded shift registers, the effective pulse duty ratio of the light-emitting control signal output by each shift register cannot be adjusted at will in order to ensure the validity of the output signal of the shift register. When the dimming mode in the prior art is adopted to adjust the brightness of the display panel, the effective pulse duty of the light-emitting control signal for controlling each row of pixels in the adjusting process cannot be continuously changed, so that the brightness of the display panel is changed in a step manner, and the viewing experience is reduced.

Disclosure of Invention

The embodiment of the invention provides a light-emitting control circuit, a driving method thereof, a display panel and a display device, which are used for smoothly adjusting the display brightness of the display panel.

In a first aspect, an embodiment of the present invention provides a driving method for a light emission control circuit, where the light emission control circuit includes: the input signal end of the shift register of the first stage is connected with the initial signal end; the starting signal end inputs a frame starting signal with an effective level with set duration to the shift register of the first stage; the driving method comprises the following steps:

when the brightness of the display panel is adjusted, the duration of the effective level of the frame starting signal is prolonged or shortened on the basis of the current frame starting signal by taking 4N unit durations as step lengths, so that the duration of the same effective level is correspondingly prolonged or shortened by the light-emitting control signal output by each stage of the shift register; wherein,

n is a positive integer greater than or equal to 1;

the effective level of the light-emitting control signal is used for controlling the corresponding pixel row to emit light;

the unit time length is the time length corresponding to one line of scanned pixels.

In a possible implementation manner, in the foregoing driving method provided by an embodiment of the present invention, when adjusting the brightness of the display panel, the lengthening or shortening the duration of the active level of the frame start signal on the basis of the current frame start signal by taking 4N unit durations as step sizes includes:

and when the brightness of the display panel is increased, prolonging the duration of the effective level of the frame starting signal on the basis of the current frame starting signal by taking 4N unit durations as step lengths.

In a possible implementation manner, in the foregoing driving method provided by an embodiment of the present invention, when adjusting the brightness of the display panel, the extending or shortening the duration of the active level of the frame start signal on the basis of the current frame start signal by using 4N unit durations as step sizes further includes:

and when the brightness of the display panel is reduced, shortening the duration of the effective level of the frame starting signal on the basis of the current frame starting signal by taking 4N unit durations as step lengths.

In a possible implementation manner, in the above driving method provided by the embodiment of the present invention, when the transistor driven by the light emission control circuit is an N-type transistor, the active levels of the frame start signal and the light emission control signal are high levels.

In a possible implementation manner, in the above driving method provided by the embodiment of the present invention, when the transistor driven by the light emission control circuit is a P-type transistor, the active pulse levels of the frame start signal and the light emission control signal are at a low level.

In a possible implementation manner, in the foregoing driving method provided by the embodiment of the present invention, the minimum step size for adjusting the duration of the active level of the frame start signal is 4 unit durations.

A second method, an embodiment of the present invention provides a light emission control circuit using any one of the driving methods, including:

the input signal end of the shift register of the first stage is connected with the initial signal end; except the shift register of the first stage, the input signal ends of the shift registers of the other stages are respectively connected with the output signal end of the shift register of the previous stage.

In a possible implementation manner, in the light-emitting control circuit provided in an embodiment of the present invention, the shift register includes: the device comprises an input module, a control module and an output module; wherein,

the input module is respectively connected with an input signal end, a clock signal end and a first node; the input module is used for providing a signal of the input signal end to a first node under the control of the clock signal end;

the control module is respectively connected with the first node, the clock signal end, the first reference signal end, the second node and the third node; the control module is used for controlling the potentials of the second node and the third node under the action of the first node, the clock signal end and the first reference signal end;

the output module is respectively connected with the second node, the third node, the first reference signal end, the second reference signal end and the output signal end; the output module is configured to provide a signal of the first reference signal terminal or the second reference signal terminal to the output signal terminal under the control of the second node and the third node.

In a third aspect, an embodiment of the present invention provides a display panel, including any one of the light emission control circuits described above.

In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the output signal of each shift register in the light emission control circuit drives one row of pixels to emit light.

In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the output signal of each shift register in the light emission control circuit drives at least two rows of pixels to emit light.

In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the output signal of each shift register in the light emission control circuit drives two rows of pixels to emit light.

In a fourth aspect, an embodiment of the invention provides a display device, including any one of the display panels described above.

The invention has the following beneficial effects:

the embodiment of the invention provides a light-emitting control circuit, a driving method thereof, a display panel and a display device, wherein the light-emitting control circuit comprises: the input signal end of the first stage of shift register is connected with the initial signal end; the start signal terminal inputs a frame start signal having an active level of a set duration to the first stage shift register. When the brightness of the display panel is adjusted, the effective level duration of the frame starting signal is prolonged or shortened on the basis of the current frame starting signal by taking 4N unit durations as step lengths, so that the light-emitting control signals output by the shift registers at all levels correspondingly prolong or shorten the same effective level duration. When the effective level of the frame starting signal is adjusted by taking 4N unit time lengths as step lengths, the step-type change of the brightness of the display panel can be avoided, so that the brightness adjustment of the display panel is smoother, and the display brightness is more uniform.

Drawings

Fig. 1 is a schematic structural diagram of a light-emitting control circuit according to an embodiment of the present invention;

fig. 2 is a flowchart of a driving method of a light emitting control circuit according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 5a is a timing diagram of the shift register shown in FIG. 4;

FIG. 5b is a second timing diagram of the shift register shown in FIG. 4;

FIG. 5c is a third timing diagram of the shift register shown in FIG. 4;

FIG. 5d is a fourth timing diagram of the shift register shown in FIG. 4;

FIG. 5e is a fifth timing diagram of the shift register shown in FIG. 4;

FIG. 6a is a sixth timing diagram of the shift register shown in FIG. 4;

FIG. 6b is a seventh timing diagram of the shift register shown in FIG. 4;

FIG. 6c is an eighth timing diagram of the shift register shown in FIG. 4;

FIG. 6d is a ninth timing diagram of the shift register shown in FIG. 4;

FIG. 6e is a tenth timing diagram of the shift register shown in FIG. 4;

fig. 7 is a schematic diagram of a display device according to an embodiment of the invention.

Detailed Description

The embodiment of the invention provides a light-emitting control circuit, a driving method thereof, a display panel and a display device, which are used for smoothly adjusting the display brightness of the display panel.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention is further described with reference to the accompanying drawings and examples. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

The following describes a light emission control circuit, a driving method thereof, a display panel, and a display device according to embodiments of the present invention in detail with reference to the accompanying drawings.

As shown in fig. 1, a light emission control circuit according to an embodiment of the present invention includes: a plurality of cascaded shift registers (only six cascaded shift registers SR (1) -SR (6) are shown in fig. 1), an input signal terminal of the first stage shift register SR (1) is connected to a start signal terminal STV; the start signal terminal STV inputs a frame start signal having an active level of a set duration to the first stage shift register SR (1).

The light emission control signal (emit 1-emit6 shown in fig. 1) output from each stage of shift register can be used to drive at least one row of pixels to emit light. The active level duration of the emission control signal determines the emission duration of the driven pixel, the emission duration of the pixel can be changed by changing the active level duration of the emission control signal, the overall brightness of the display panel increases when the emission duration increases, and the overall brightness of the display panel decreases when the emission duration decreases. However, the effective level duration of the light-emitting control signal generated by the shift register cannot be adjusted at will, and in practical application, even if the frame start signal connected to the input terminal of the first stage shift register is changed, it cannot be guaranteed that the light-emitting control signals output by the following stages of shift registers are changed accordingly, which causes uneven display brightness of the display panel, and the brightness is increased or decreased step by step in the brightness adjustment process, thereby reducing the viewing experience of users.

In view of the above, the present invention provides a driving method based on the above light emitting control circuit, which includes:

when the brightness of the display panel is adjusted, the effective level duration of the frame starting signal is prolonged or shortened on the basis of the current frame starting signal by taking 4N unit durations as step lengths, so that the light-emitting control signals output by the shift registers at all levels correspondingly prolong or shorten the same effective level duration.

Wherein N is a positive integer greater than or equal to 1; the effective level of the light-emitting control signal is used for controlling the corresponding pixel row to emit light; the unit time length is the time length corresponding to scanning one row of pixels.

When the effective level of the frame starting signal is adjusted by taking 4N unit time lengths as step lengths, the step-type change of the brightness of the display panel can be avoided, so that the brightness adjustment of the display panel is smoother, and the display brightness is more uniform.

Specifically, when adjusting the brightness of the display panel, the steps shown in fig. 2 may be adopted:

s201, determining that the brightness of the current display panel needs to be increased or decreased; when it is determined that the luminance of the display panel increases, step S202 is performed; when it is determined that the luminance of the display panel decreases, step S203 is performed;

s202, prolonging the duration of the effective level of the frame starting signal on the basis of the current frame starting signal by taking 4N unit durations as step lengths;

and S203, shortening the duration of the effective level of the frame starting signal on the basis of the current frame starting signal by taking 4N unit durations as step sizes.

In a specific application, the minimum step size for adjusting the duration of the active level of the frame start signal can be determined according to the brightness adjustment precision of the display panel. For example, the minimum adjustment step size may be 4 unit durations, 8 unit durations, or 12 unit durations, etc. The smooth adjustment of the brightness of the display panel can be realized as long as the adjusted step length is equal each time. In the embodiment of the present invention, in order to improve the precision of the brightness adjustment of the display panel, 4 unit durations may be used as the adjustment step length of the active level duration of the frame start signal.

In a specific implementation, the light emission control circuit is generally formed by connecting a plurality of transistors and capacitors in a specific connection relationship, and if the transistors driven by the light emission control circuit are N-type transistors, the active levels of the frame start signal and the light emission control signal are at a high level. If the transistor driven by the light-emitting control circuit is a P-type transistor, the effective pulse levels of the frame start signal and the light-emitting control signal are low. In practical applications, the type of the transistor needs to be designed according to the practical application environment, and is not limited herein.

The above driving method will be described below with reference to a specific structure of the light emission control circuit.

As described above, referring to fig. 1, the light emission control circuit includes: the shift register comprises a plurality of cascaded shift registers SR (1) -SR (6), wherein an input signal end of a first-stage shift register SR (1) is connected with an initial signal end STV; except for the first stage of shift register SR (1), the input signal ends of the other shift registers SR (2) -SR (6) are respectively connected with the output signal end of the shift register of the previous stage.

The structure of each shift register is shown in fig. 3, and includes: an input module 31, a control module 32 and an output module 33.

As shown in fig. 3, the Input module 31 is connected to the Input signal terminal Input, the clock signal terminal CK and the first node respectively N1; the Input module 31 is used for providing a signal of an Input signal terminal Input to a first node N1 under the control of a clock signal terminal CK;

the control module 32 is respectively connected to the first node N1, the clock signal terminal CK, the first reference signal terminal S1, the second reference signal terminal S2, the second node N2 and the third node N3; the control module 32 is used for controlling the potentials of the second node N2 and the third node N3 under the actions of the first node N1, the clock signal terminal CK, the first reference signal terminal S1 and the second reference signal terminal S2;

the Output module 33 is respectively connected to the second node N2, the third node N3, the first reference signal terminal S1, the second reference signal terminal S2, and the Output signal terminal Output; the Output module 33 is used for providing the signal of the first reference signal terminal S1 or the second reference signal terminal S2 to the Output signal terminal Output under the control of the second node N2 and the third node N3.

In practical applications, all the shift registers in the light-emitting control circuit can be divided into the three modules, and the number of the transistors and the capacitor elements included in each of the divided modules and the connection method thereof are different according to the number and connection method of the transistors and the capacitor elements included in the actual circuit of each shift register.

As shown in fig. 4, the shift register provided in the embodiment of the present invention may include 10 transistors and 3 capacitors, where each transistor may be a P-type transistor or an N-type transistor. The P-type transistor is cut off under the action of a high level and is switched on under the action of a low level; the N-type transistor is turned on under the action of high level and turned off under the action of low level. In practical applications, the type of the driving transistor needs to be designed according to practical application environments, and is not limited herein. In this embodiment, a case where each transistor is a P-type transistor will be described.

Further, as shown in fig. 4, in the shift register circuit provided in the embodiment of the present invention, the input module 31 includes: a first transistor M1; the control module 32 includes: a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a first capacitor C1 and a second capacitor C2; the output module 33 includes: a ninth transistor M9, a third capacitor C3, and a tenth transistor M10.

The clock signal is divided into a first clock signal CK and a second clock signal CKB.

The first reference signal end is a high-level signal end VGH; the second reference signal terminal is a low level signal terminal VGL.

Specifically, the control electrode of the first transistor M1 is connected to the first clock signal CK terminal, the first electrode is connected to the Input signal terminal Input, and the second electrode is connected to the control module.

A control electrode of the second transistor M2 is connected to the first clock signal CK terminal, a first electrode is connected to the second reference signal terminal VGL, and a second electrode is connected to a control electrode of the sixth transistor M6 and a control electrode of the fifth transistor M5, respectively;

a control electrode of the third transistor M3 is connected to the second electrode of the first transistor M1 and the output module, respectively, a first electrode is connected to the first clock control signal terminal, and a second electrode is connected to a control electrode of the fifth transistor M5;

a control electrode of the fourth transistor M4 is connected to the second clock signal terminal CKB, a first electrode thereof is connected to the second electrode of the first transistor M1, and a second electrode thereof is connected to the first electrode of the fifth transistor M5;

a second pole of the fifth transistor M5 is connected to the first reference signal terminal VGH and a second pole of the eighth transistor M8, respectively;

a first pole of the sixth transistor M6 is connected to the second clock signal terminal CKB, and a second pole is connected to the first pole of the seventh transistor M7;

a control electrode of the seventh transistor M7 is connected to the second clock signal terminal CKB and the first electrode of the sixth transistor M6, respectively, and a second electrode is connected to the first electrode of the eighth transistor M8;

a control electrode of the eighth transistor M8 is connected to the second electrode of the first transistor M1 and the output module, respectively, a first electrode of the eighth transistor M8 is connected to the output module, and a second electrode of the eighth transistor M8 is connected to the first reference signal terminal VGH;

one end of the first capacitor C1 is connected to the second clock signal terminal CKB and the first electrode of the sixth transistor M6, and the other end is connected to the second electrode of the first transistor M1, the control electrode of the eighth transistor M8, and the output module;

one end of the second capacitor C2 is connected to the control electrode of the fifth transistor M5, and the other end is connected to the first electrode of the seventh transistor M7.

A control electrode of the ninth transistor M9 is connected to the second electrode of the seventh transistor M7 and the second electrode of the eighth transistor M8, respectively, a first electrode is connected to the Output signal terminal Output, and a second electrode is connected to the first reference signal terminal VGH and the second electrode of the eighth transistor M8, respectively;

a control electrode of the tenth transistor M10 is connected to a control electrode of the eighth transistor M8 and a second electrode of the first transistor M1, respectively, a first electrode is connected to the second reference signal terminal VGL, and a second electrode is connected to the Output signal terminal Output;

one terminal of the third capacitor C3 is connected to the second pole of the eighth transistor M8, and the other terminal is connected to the control pole of the ninth transistor M9.

The transistors may be Thin Film Transistors (TFTs) or Metal Oxide semiconductor field effect transistors (MOS), and are not limited herein. In practical implementation, the control electrode of the transistors is the gate electrode, and the first electrode can be used as the source electrode or the drain electrode of the transistor, and the second electrode can be used as the drain electrode or the source electrode of the transistor according to the type of the transistor and the input signal.

The driving method of the present invention will be specifically described below by taking a P-type transistor as an example of each transistor. When the transistor is a P-type transistor, the active level is a low level. In the following description, 1 represents a high level, and 0 represents a low level. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation of the embodiment of the present invention, and not the voltages applied to the control electrodes of the transistors in the specific implementation.

When the signal shown in fig. 5a is input to each signal terminal of the shift register circuit shown in fig. 4, for convenience of description, the shift register circuit may be divided into T1-T8 periods, where the time length of each period of T1-T8 is one unit time length, that is, the time length corresponding to scanning one row of pixels.

In period T1, Input is 1, CK is 0, and CKB is 1. Since CK is 0, both the first transistor M1 and the second transistor M2 are turned on, the potential of the node a1 is at a high level, and the potential of the node A3 is at a low level; since a1 is equal to 1, the third transistor M3, the eighth transistor M8, and the tenth transistor M10 are all turned off; since a3 is 0, both the fifth transistor M5 and the sixth transistor M6 are turned on; since CKB is equal to 1, the fourth transistor M4 and the seventh transistor M7 are both turned off, the potentials at both ends of the first capacitor C1 are equal and are high, and the potential at both ends of the second capacitor C2 is the potentials of the nodes A3 and a4 (A3 is equal to 0, and a4 is equal to 1). The Output signal terminal Output holds the low level signal at the time of the previous frame for a period T1.

In the first half of the period T2, Input is 1, CK is 0, and CKB is 1, and the operation process is the same as that in the period T1, and will not be described herein again. In the second half of the period T2, Input is 1, CK is 1, and CKB is 1. Since CK is 1, both the first transistor M1 and the second transistor M2 are turned off, and no new input signal is input; since CKB is 1, both the fourth transistor M4 and the seventh transistor M7 are turned off. The Output signal terminal Output holds a low level signal for a period T1.

In period T3, Input is 0, CK is 1, and CKB is 0. Since CK is 1, both the first transistor M1 and the second transistor M2 are turned off, and the potential of one end of the second capacitor at the A3 node becomes low. Since N3 is equal to 0, both the fifth transistor M5 and the sixth transistor M6 are turned on; since CKB is equal to 0, the fourth transistor M4 is turned on, and the fifth transistor M5 and the fourth transistor M4 input the high potential of the high level signal VGH to the node a 1; since a1 is equal to 1, the third transistor M3, the eighth transistor M8, and the tenth transistor M10 are all turned off; since the sixth transistor M6 is turned on, and the low level of the second clock signal terminal CKB is input to the node a4(a4 is equal to 0), the seventh transistor M7 is turned on, a2 is equal to a4 is equal to 0, the ninth transistor M9 is turned on, and the Output signal terminal Output outputs a high level potential (Output is equal to 1), at this time, the potentials at both ends of the first capacitor C1 are the potentials of CKB and a1 (CKB is equal to 0, a1 is equal to 1), the potentials at both ends of the second capacitor C2 are the potentials of the nodes A3 and a4 (A3 is equal to 0, a4 is equal to 0), and the potentials at both ends of the third capacitor C3 are the potentials of VGH and a2 (VGH is equal to 1, and a2 is equal to 0).

In the first half of the period T4, Input is 0, CK is 1, and CKB is 0. The working process is the same as that of the period T3, and the description is omitted here. In the second half of the period T4, Input is 0, CK is 1, and CKB is 1. Since CKB is 1, both the fourth transistor M4 and the seventh transistor M7 are turned off; while the first capacitor C1 holds a1 equal to 1, and thus, the third transistor M3, the eighth transistor M8, and the tenth transistor M10 are all turned off; since the third capacitor C3 holds a2 equal to 0, the ninth transistor M9 is turned on, and the Output signal terminal Output outputs a high-level potential (Output equal to 1).

In period T5, Input is 0, CK is 1, and CKB is 1. Since CK is 0, both the first transistor M1 and the second transistor M2 are turned on, a1 is 0, A3 is 0; since a1 is equal to 0, the third transistor M3, the eighth transistor M8, and the tenth transistor M10 are all turned on, and the Output signal terminal Output outputs the low-level potential of the low-level signal terminal (Output is equal to 0). Since A3 is equal to 0, the sixth transistor M6 is turned on, and a high-level signal of the second clock signal terminal CKB is input to a4(a4 is equal to 1); since the eighth transistor M8 is turned on, a2 becomes 1, and the ninth transistor M9 is turned off. At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 0, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1).

In the first half of the period T6, Input is 0, CK is 0, and CKB is 1. The working process is the same as that of the period T5, and the description is omitted here. In the second half of the period T6, Input is 0, CK is 1, and CKB is 1. Since CK is 1, both the first transistor M1 and the second transistor M2 are turned off; the first capacitor C1 holds a1 equal to 0, so that the third transistor M3, the eighth transistor M8 and the tenth transistor M10 are all turned on, and the Output signal terminal Output outputs the low-level potential of the low-level signal terminal (Output equal to 0), where A3 is equal to 0, a2 is equal to 1, and a4 is equal to 1; at this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 0, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1).

In period T7, Input is 0, CK is 1, and CKB is 0. Since CK is 1, both the first transistor M1 and the second transistor M2 are turned off; since the first capacitor C1 holds the a1 equal to 0, the third transistor M3, the eighth transistor M8, and the tenth transistor M10 are all turned on, the Output signal terminal Output outputs the low-level potential of the low-level signal terminal (Output equal to 0), A3 equal to 1, and a2 equal to 1. At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 0, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 1, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1).

In the first half of the period T8, Input is 0, CK is 1, and CKB is 0. The working process is the same as that of the period T7, and the description is omitted here. In the second half of the period T8, Input is 0, CK is 1, and CKB is 1. Since CKB is 1, both the fourth transistor M4 and the seventh transistor M7 are turned off; since the first capacitor C1 holds N1 equal to 0, the third transistor M3, the eighth transistor M8, and the tenth transistor M10 are all turned on, and the Output signal terminal Output outputs the low-level potential of the low-level signal terminal (Output equal to 0).

It can be seen from the specific working process of the shift register circuit provided in the embodiment of the present invention that, when the effective level of the Input signal at the Input signal end is set long, the effective level duration of the Output signal at the Output signal end is equal to the effective level duration of the Input signal, so that when the Output signal is used as the Input signal of the next-stage shift register, the effective level durations of the Output signal at the next-stage shift register are all equal to the effective level duration of the Output signal at the previous-stage shift register. When the output signal of each shift register is used as the light-emitting control signal of at least one row of pixels, the light-emitting duration of each row of pixels of the display panel can be controlled as long as the input signal of the first-stage shift register, namely the effective level duration of the frame start signal, is controlled, so that the display brightness of the display panel is controlled according to the light-emitting duration of the display panel in one frame.

However, in practical implementation, the duration of the active level of the frame start signal is not extended or shortened by any duration, so that the output signal of the frame start signal or the output signal of the next shift register changes by a corresponding duration. The following describes the above driving method provided by the embodiment of the present invention in detail in the case where the frame start signal is sequentially adjusted by one unit duration.

When the signal shown in fig. 5b is input to each signal terminal of the shift register circuit shown in fig. 4, for convenience of description, the shift register circuit can be divided into T1-T8 periods, where the time length of each period of T1-T8 is one unit time length, that is, the time length corresponding to scanning one row of pixels. The difference from the timing shown in fig. 5a is that in fig. 5b the duration of the active level at the input signal side is shortened by one unit duration with respect to fig. 5 a.

In the periods T1 and T2 shown in FIG. 5b, the operation process is the same as that of the periods T1 and T2 shown in FIG. 5a, and the description is omitted here.

In period T3, Input is 1, CK is 1, and CKB is 0. Since CK is 1, both the first transistor M1 and the second transistor are off; since CKB is 0 and A3 is 0, the sixth transistor M6 and the seventh transistor M7 are both turned on, and a4 is a2 is 0; since a2 is equal to 0, the ninth transistor M9 is turned on, and the Output signal terminal Output receives the high-level potential of the high-level signal terminal (Output is equal to 1). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 0, a1 is 1), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 1, a4 is 0), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 0).

In the first half of the period T4, Input is 0, CK is 1, and CKB is 0. Since CK is 1, both the first transistor M1 and the second transistor are off; since a3 is 1, both the fifth transistor M5 and the sixth transistor M6 are off; since the second capacitor C2 holds a2 equal to 0, the ninth transistor M9 is turned on, and the Output signal terminal Output outputs the high level potential of the high level signal terminal (Output equal to 1). In the second half of the period T4, Input is 0, CK is 1, CKB is 1, no new signal is Input, and the Output signal terminal Output maintains a high level potential.

In the first half of the T5 period and the T6 period, Input is 0, CK is 0, and CKB is 1. Since CK is 0, both the first transistor M1 and the second transistor M2 are turned on, and a1 is 0; since a1 is equal to 0, the tenth transistor M10 is turned on, and the Output signal terminal Output outputs the low level potential of the low level signal terminal VGL (Output is equal to 0). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 0, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1). In the second half of the period T6, Input is 0, CK is 1, CKB is 1, and the first transistor M1, the second transistor M2, the fourth transistor M4, and the seventh transistor M7 are all turned off; since the first capacitor C1 holds a1 equal to 0, the tenth transistor M10 is turned on, and the Output signal terminal Output outputs the low level potential of the low level signal terminal VGL (Output equal to 0). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 0, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1).

In the first half of the T7 period and the T8 period, Input is 0, CK is 1, CKB is 0, and the fourth transistor M4 and the seventh transistor M7 are both turned on; since CKB is equal to 0, the first capacitor further pulls the potential of the node a1 low, so that the tenth transistor M10 is turned on, and the Output signal terminal Output outputs the low level potential of the low level signal terminal VGL (Output is equal to 0). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 0, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 1, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1). In the second half of the period T8, Input is 0, CK is 1, CKB is 1, and no new signal is Input, and a1 is 0, so the tenth transistor M10 is turned on and the Output signal terminal Output outputs the low-level potential of the low-level signal terminal VGL (Output is 0).

As can be seen from the above description of the operation process of the shift register corresponding to fig. 5b, when the duration of the active level of the input signal is adjusted by one unit duration, the duration of the active level of the output signal cannot be changed accordingly.

When the signal shown in fig. 5c is input to each signal terminal of the shift register circuit shown in fig. 4, the effective level time length of the input signal terminal is shortened by two unit time lengths compared with the timing shown in fig. 5 a.

The operation process in the time period T1-T3 is the same as the operation process in the time period T1-T3 shown in FIG. 5b, and further description thereof is omitted.

In the first half of the period T4, Input is 1, CK is 1, and CKB is 0. Since CK is 1, both the first transistor M1 and the second transistor M2 are turned off, and no new signal is input; since CKB is equal to 0, the seventh transistor M7 is turned on, a2 is equal to a4 is equal to 0, the ninth transistor M9 is turned on, and the Output signal terminal Output inputs the high level potential of the high level signal terminal (Output is equal to 1). In the second half of the period T4, Input is 1, CK is 1, CKB is 1, and the potentials at the two ends of the capacitors are kept the same as the potential in the first half, so that a2 is 0, the ninth transistor M9 is turned on, and the Output signal terminal Output inputs the high-level potential of the high-level signal terminal (Output is 1). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 1), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 1, a4 is 0), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 0).

In the first half of the T5 period and the T6 period, Input is 0, CK is 0, and CKB is 1. Since CK is 0, both the first transistor M1 and the second transistor M2 are turned on; since M1 is turned on and Input is 0, a1 is 0, the tenth transistor M10 is turned on, and the Output signal terminal Output receives the low level potential of the low level signal terminal (Output is 0). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 0, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1). In the second half of the period T6, Input is 0, CK is 1, CKB is 1, M1 and M2 are both off, no new signal is Input, and since the first capacitor C1 holds a1 which is 0, the tenth transistor M10 is turned on, and the Output signal terminal Output inputs the low-level potential of the low-level signal terminal (Output is 0). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 1, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1).

In the first half of the T7 period and the T8 period, Input is 0, CK is 1, and CKB is 0. Since CKB is equal to 0, the first capacitor further pulls the potential of the node a1 low, so that the tenth transistor M10 is turned on, and the Output signal terminal Output outputs the low level potential of the low level signal terminal VGL (Output is equal to 0). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 0, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 1, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1). In the second half of the period T8, Input is 0, CK is 1, CKB is 1, and no new signal is Input, and a1 is 0, so the tenth transistor M10 is turned on and the Output signal terminal Output outputs the low-level potential of the low-level signal terminal VGL (Output is 0).

As can be seen from the above description of the operation process of the shift register corresponding to fig. 5c, when the duration of the active level of the input signal is adjusted by two unit durations, the duration of the active level of the output signal cannot be changed accordingly.

When the signal shown in fig. 5d is input to each signal terminal of the shift register circuit shown in fig. 4, the effective level time length of the input signal terminal is shortened by three unit time lengths compared with the timing shown in fig. 5 a.

The operation process in the time period T1-T4 is the same as the operation process in the time period T1-T4 shown in FIG. 5c, and further description thereof is omitted.

In the period T5, Input is 1, CK is 0, CKB is 1, M1 is turned on, a1 is 1, and thus, the tenth transistor M10 is turned off; since the third capacitor C3 holds a2 equal to 0, the ninth transistor M9 is turned on, and the Output signal terminal Output receives the high level potential of the high level signal terminal (Output equal to 1). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 1), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 0, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 0).

In the first half of the period T6, Input is 0, CK is 0, and CKB is 1. Since CK is 0, both the first transistor M1 and the second transistor M2 are turned on; since M1 is turned on and Input is 0, a1 is 0, the tenth transistor M10 is turned on, and the Output signal terminal Output receives the low level potential of the low level signal terminal (Output is 0). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 0, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1). In the second half of the period T6, Input is 0, CK is 1, CKB is 1, M1 and M2 are both off, no new signal is Input, and since the first capacitor C1 holds a1 which is 0, the tenth transistor M10 is turned on, and the Output signal terminal Output inputs the low-level potential of the low-level signal terminal (Output is 0). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 1, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1).

In the first half of the T7 period and the T8 period, Input is 0, CK is 1, and CKB is 0. Since CKB is equal to 0, the first capacitor further pulls the potential of the node a1 low, so that the tenth transistor M10 is turned on, and the Output signal terminal Output outputs the low level potential of the low level signal terminal VGL (Output is equal to 0). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 0, a1 is 0), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 1, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 1). In the second half of the period T8, Input is 0, CK is 1, CKB is 1, and no new signal is Input, and a1 is 0, so the tenth transistor M10 is turned on and the Output signal terminal Output outputs the low-level potential of the low-level signal terminal VGL (Output is 0).

It can be seen from the above description of the operation process of the shift register corresponding to fig. 5d that when the duration of the effective level of the input signal is shortened by three unit durations, the duration of the effective level of the output signal is shortened by one unit duration, but when the output signal is used as the input signal of the next stage of shift register, the operation process shown in fig. 5b is repeated, and the next stage of shift register cannot adjust the duration with the effective level of the input signal. This causes different display time of each row of pixels, resulting in non-uniform brightness.

When the signal shown in fig. 5e is input to each signal terminal of the shift register circuit shown in fig. 4, the effective level time length of the input signal terminal is shortened by four unit time lengths compared with the timing shown in fig. 5 a.

The operation process in the time period T1-T5 is the same as the operation process in the time period T1-T5 shown in FIG. 5d, and further description thereof is omitted.

In the first half of the period T6, Input is 1, CK is 0, CKB is 1, M1 and M2 are on, A3 is 0, and thus M6 is on and a4 is 1. Since the third capacitor C3 holds a2 equal to 0, the ninth transistor M9 is turned on, and the Output signal terminal Output receives the high level potential of the high level signal terminal (Output equal to 1). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 1), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 0, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 0). In the second half of the period T6, Input is 1, CK is 1, CKB is 1, M1 and M2 are both off, no new signal is Input, and since the third capacitor C3 holds a2 equal to 0, the ninth transistor M9 is turned on, and the Output signal terminal Output inputs the high-level potential of the high-level signal terminal (Output is 1). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 1, a1 is 1), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 0, a4 is 1), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 0).

In the first half of the T7 period and the T8 period, Input is 0, CK is 1, and CKB is 0. Since CKB is equal to 0 and A3 is equal to 0, M6 and M7 are turned on, a4 is equal to a2 is equal to 0, the ninth transistor M9 is turned on, and the Output signal terminal Output inputs the high level potential of the high level signal terminal (Output is equal to 1). At this time, the potential across the first capacitor C1 is the potential of CKB and a1 (CKB is 0, a1 is 1), the potential across the second capacitor C2 is the potential of nodes A3 and a4 (A3 is 0, a4 is 0), and the potential across the third capacitor C3 is the potential of VGH and a2 (VGH is 1, a2 is 0). In the second half of the period T8, Input is 0, CK is 1, CKB is 1, and no new signal is Input, and a2 is 0, so that the ninth transistor M9 is turned on and the Output signal terminal Output outputs the high-level potential of the high-level signal terminal VGH (Output is 1).

In the period T9, Input is 0, CK is 0, CKB is 1, M1 is turned on, and a1 is 0, so that the tenth transistor M10 is turned on and the Output signal terminal Output inputs the low level potential of the low level signal terminal VGL (Output is 0).

It can be seen from the above description of the operation process of the shift register corresponding to fig. 5e that, when the effective level duration of the input signal is shortened by four unit durations, the effective level duration of the output signal is also shortened by four unit durations, so that, when the shift register is used as a first stage shift register and the input signal end is a start signal end, the same effective level duration can be adjusted by the output signal of each stage of shift register by using 4 unit durations as the effective level duration of the frame start signal of the step start signal end, thereby adjusting the light emitting time of each row of pixels.

Further, according to the above-mentioned working process, it can be concluded that when the duration of the effective level of the input signal of the shift register is increased or shortened by an integral multiple of 4 unit durations, the duration of the effective level of the output signal thereof is also correspondingly increased or shortened by the same duration, and when the duration of the increase or the shortening of the duration of the effective level of the input signal is not an integral multiple of 4 unit durations, the output signal cannot be changed therewith, or the output signal of the shift register of the next stage cannot be changed therewith. Therefore, the effective level time length of the frame start signal of the first-stage shift register is adjusted by taking 4N unit time lengths as adjustment steps, so that the brightness of the display panel can be smoothly adjusted, and the problems of uneven brightness and step-type rising or falling of the brightness are avoided. And when 4 unit time lengths are adopted as the adjusting step length, the adjusting precision of the shift registers at all levels can reach the highest, and in practical application, the adjusting step length can be selected according to needs, and is not limited herein.

Based on the same inventive concept, the embodiment of the invention further provides a display panel, which comprises any one of the light-emitting control circuits. The output signals of each stage of shift register in the light-emitting control circuit included in the display panel can drive at least one row of pixels to emit light. The light-emitting control circuit shown in fig. 4 can control the light-emitting time length of each row of pixels by adopting the adjusting manner shown in fig. 5a and 5 e. Fig. 5a and 5e show the driving manner of the output signals of the shift registers of each stage to drive the two rows of result lines to emit light.

In another practical way, each stage of the shift register can drive only one row of pixels to emit light. Still taking the specific circuit of the shift register shown in fig. 4 as an example, when the output signal of the shift register drives a row of pixels to emit light, the shift register can be respectively disposed at two sides of each row of pixels, and the odd row and the even row of pixels are respectively controlled.

Specifically, the timing control diagram of the shift register of the first stage is shown in fig. 6a, wherein the Input signal is the frame start signal, and the clock signal terminals are divided into a first clock signal terminal CK left and a second clock signal terminal CKB left on the left of the display panel, and a first clock signal terminal CK right and a second clock signal terminal CKB right on the right of the display panel. The clock signal terminal on the left side of the display panel is only used for controlling the shift register on the left side, and the output signal of the shift register on the left side can be used for driving the pixels in the odd rows (or even rows) to emit light; the clock signal terminal on the right side of the display panel is only used for controlling the shift register on the right side, and the output signal of the shift register on the right side can be used for driving the pixels on the even rows (or the odd rows) to emit light.

Further, when the signal shown in fig. 6a is Input to each signal terminal of the shift register circuit shown in fig. 4, the Input signal of the shift register on the left side corresponds to the first two unit durations of the Input signal (i.e., corresponds to the T1 and T2 periods); the Input signal to the shift register on the right corresponds to the last two cell durations of the Input signal (i.e., to the T2 and T3 periods). The operation of the shift register circuit on the left side in the period T1-T8 is the same as that in the period T1-T8 in FIG. 5 a; the operation of the right electromechanical shift register circuit in the time period T2-T9 is the same as the operation in the time period T1-T8 in fig. 5a, and further description thereof is omitted. As can be seen from the timing chart shown in fig. 6a, the output signal of the shift register on the right side is delayed by one unit time length from the output signal of the corresponding shift register on the left side, whereby individual driving of pixels of two adjacent rows can be realized.

When the duration of the effective level of the input signal to the shift register is sequentially changed, as shown in fig. 6b to 6e, the duration of the effective level of the input signal is sequentially shortened by 1 to 4 unit durations, in the corresponding working process, the working processes of the shift register circuits on the left side at T1 to T8 can be referred to as the working processes of T1 to T8 in fig. 5b to 5e, and the working processes of the shift register circuits on the right side at T2 to T9 can be referred to as the working processes of T1 to T8 in fig. 5b to 5e, which are not repeated herein.

Because no matter the shift registers at all levels drive two lines of pixels to emit light or drive one line of pixels to emit light, only when the effective level duration of the input signal is adjusted by taking 4N unit durations as step lengths, the output signals of the shift registers at all levels can correspondingly adjust the same duration, so that when the effective level duration of the frame starting signal is adjusted by taking 4N unit durations as the step lengths, the step-type change of the brightness of the display panel can be avoided, the brightness adjustment of the display panel is smoother, and the display brightness is more uniform.

In addition, an embodiment of the present invention further provides a display device, including any one of the display panels described above, where the display device may be a display device such as an OLED panel, an OLED display, an OLED television, or electronic paper, or may also be a mobile device such as a mobile phone or a smart phone. Fig. 7 is a top view of the display device provided in the embodiment of the present invention in a smart phone, wherein the display screen may adopt any one of the display panels, and may include any one of the structures of the light-emitting control circuit, and the brightness of the display panel is adjusted by using the driving method provided in the embodiment of the present invention, which is not limited herein.

The embodiment of the invention provides a light-emitting control circuit, a driving method thereof, a display panel and a display device, wherein the light-emitting control circuit comprises: the input signal end of the first stage of shift register is connected with the initial signal end; the start signal terminal inputs a frame start signal having an active level of a set duration to the first stage shift register. When the brightness of the display panel is adjusted, the effective level duration of the frame starting signal is prolonged or shortened on the basis of the current frame starting signal by taking 4N unit durations as step lengths, so that the light-emitting control signals output by the shift registers at all levels correspondingly prolong or shorten the same effective level duration. When the effective level of the frame starting signal is adjusted by taking 4N unit time lengths as step lengths, the step-type change of the brightness of the display panel can be avoided, so that the brightness adjustment of the display panel is smoother, and the display brightness is more uniform.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.