CN107658298A - Recessed channel Nonvolatile semiconductor memory device and its manufacture method - Google Patents

本发明揭露一种凹入式通道半导体非易失性存储装置。凹入式通道MOSFET装置是通过蚀刻深入硅基板来形成装置通道，已经应用于先进的DRAM工艺世代，本发明利用该凹入式通道MOSFET装置的相同蚀刻工艺以形成该凹入式通道半导体非易失性存储装置。在凹入式通道洞蚀刻工艺之后，穿隧氧化层便形成于硅表面。电荷储存物质沉积嵌入该凹入式通道洞，而耦合介电层形成于该电荷储存物质的顶部。之后，再沉积与蚀刻栅极材料以形成控制栅。因为凹入式通道嵌入于硅基板的下方，可大幅降低半导体非易失性存储器的缩放挑战，如通道长度、浮动栅干扰、栅极堆叠蚀刻的高外观比以及形成栅极的机械稳定性。

The invention discloses a recessed channel semiconductor non-volatile memory device. The recessed channel MOSFET device is formed by etching deep into the silicon substrate to form the device channel, which has been applied in the advanced DRAM process generation. The present invention utilizes the same etching process of the recessed channel MOSFET device to form the recessed channel semiconductor non-easy volatile storage device. After the recessed channel etch process, a tunnel oxide layer is formed on the silicon surface. A charge storage material is deposited and embedded in the recessed channel hole, and a coupling dielectric layer is formed on top of the charge storage material. Afterwards, gate material is deposited and etched to form a control gate. Because the recessed channel is embedded beneath the silicon substrate, scaling challenges for semiconductor nonvolatile memory such as channel length, floating gate interference, high aspect ratio of gate stack etch, and mechanical stability of formed gates are greatly reduced.

凹入式通道半导体非易失性存储装置及其制造方法Recessed channel semiconductor non-volatile memory device and manufacturing method thereof

技术领域technical field

本发明是有关半导体非易失性存储装置(semiconductor non-volatile memorydevice)及其制造方法，特别地，该半导体非易失性存储装置的通道凹陷(recessed)于硅基板(substrate)表面之下。The present invention relates to a semiconductor non-volatile memory device and a manufacturing method thereof. In particular, the channel of the semiconductor non-volatile memory device is recessed below the surface of a silicon substrate.

背景技术Background technique

半导体非易失性存储器，特别是电子可抹除可规划唯读存储器(EEPROM)在电子设备方面，从电脑、电信至消费者电器，具备广泛的可应用性。一般而言，EEPROM在非易失性存储器领域的利基是在电力关闭时具有储存固件与数据的机制，并在有需要时可改变固件与数据。快闪EEPROM被视为一特别规划的(configured)EEPROM，只能整个被抹除或逐扇区(sector by sector)被抹除。Semiconductor non-volatile memory, especially Electronically Erasable Programmable Read-Only Memory (EEPROM) has wide applicability in electronic equipment, from computers, telecommunications to consumer appliances. Generally speaking, the niche of EEPROM in the field of non-volatile memory is to have a mechanism to store firmware and data when the power is off, and to change the firmware and data when needed. The flash EEPROM is regarded as a specially configured EEPROM, which can only be erased entirely or sector by sector.

根据装置单元阵列(cell array)组态，EEPROM快闪装置分为NOR型快闪装置及NAND型快闪装置。一般而言，NOR型快闪装置及NAND型快闪装置的单元尺寸(cell size)分别是9～10F²及4～5F²，其中，F表示一工艺技术世代(process technology node)的特征尺寸(feature size)。由于工艺技术的进步，最小工艺特征尺寸已被按比例缩小至大约20nm世代或以下。而持续将半导体非易失性存储器单元装置按比例缩小至20nm世代以下对单元装置设计与工艺技术形成重大的挑战。这些挑战包含装置短通道长度、浮动栅(floatinggate)单元对单元的干扰(interference)、栅极(gate)形成工艺的高外观比(aspectratio)以及蚀刻后栅极堆叠(after-etched gate stack)远离崩溃的稳定性。According to the device cell array configuration, EEPROM flash devices are classified into NOR flash devices and NAND flash devices. Generally, the cell sizes of NOR flash devices and NAND flash devices are 9-10F ² and 4-5F ² , respectively, where F represents the feature size of a process technology node. (feature size). Due to advances in process technology, the minimum process feature size has been scaled down to approximately 20nm generations or below. The continued scaling down of semiconductor non-volatile memory unit devices to below the 20nm generation poses a major challenge to unit device design and process technology. These challenges include device short channel length, floating gate cell-to-cell interference, high aspect ratio of gate formation process, and after-etched gate stack away from crash stability.

在DRAM按比例缩小的过程中，也遭遇过类似短通道长度的问题，为解决此问题，凹入式栅极晶体管架构已成功地应用于DRAM单元，例如揭露于美国专利第7,164,170号、第7,378,312号、第8,268,690号(上述专利的内容在此被整体引用作为本说明书内容的一部分)的技术。图1显示成对存取(access)晶体管的剖面图。请参考图1，成对存取晶体管110a、110b的凹入式通道111a、111b沿着硅基板凹陷表面的底部而形成，并且N型共源极(source)/漏极(drain)区104c、104a与104b形成于硅基板上或上方。于P型硅基板的P型杂质形成通道区102、井(well)区以及基板本质(intrinsic)区100。之后，栅极物质沉积生长于硅基板凹陷区内氧化层105的顶部，以形成晶体管栅极106。在一存储器阵列中的多个成对存取晶体管110a、110b之间是以硅基板内的浅沟槽隔离区(shallow trench isolation)103来隔离。因此，相较于使用与图1相同最小特征世代工艺的现有平面型(planar)晶体管，该些成对存取晶体管110a、110b的凹入式通道111a、111b的通道长度会增加。将凹入式通道应用于DRAM的存取晶体管，通过减少存取晶体管的“截止(off)状态”漏电流(leakagecurrent)，已有效改善储存电容器(storage capacitor)的电荷滞留(charge retention)时间，并且DRAM工艺的可缩放性(scalability)可往下延伸至20nm世代。另一方面，应用浮动栅凹入式通道晶体管，可解决半导体非易失性存储器的缩放问题，如通道长度、浮动栅干扰、以及高外观比。首先，如同先进DRAM工艺技术世代的存取晶体管110a、110b，浮动栅凹入式通道晶体管通过将通道凹陷于硅基板内来增加通道长度。第二，浮动栅并没有暴露于硅表面上，而是设置于具接地电位的硅基板之内部，并且浮动栅彼此间的单元对单元临界电压干扰也减到最低。第三，在硅基板中，将浮动栅凹陷以对应半导体非易失性存储器的凹入式通道，可解决穿隧介电层(tunneling dielectrics)/多晶硅(poly-silicon)/耦合介电层/金属膜(film)堆叠的高外观栅极蚀刻比的问题。同时，由于栅极膜堆叠固定于硅基板内部，高瘦型栅极的保持强度(holding strength)也会增加。A similar short channel length problem has been encountered during DRAM scaling down. To solve this problem, recessed gate transistor architectures have been successfully applied to DRAM cells, as disclosed in US Pat. Nos. 7,164,170, 7,378,312 No. 8,268,690 (the contents of the above-mentioned patents are hereby cited in their entirety as a part of the contents of this specification). FIG. 1 shows a cross-sectional view of a pair of access transistors. Please refer to FIG. 1, the recessed channels 111a, 111b of the pair of access transistors 110a, 110b are formed along the bottom of the recessed surface of the silicon substrate, and the N-type common source (source) / drain (drain) region 104c, 104a and 104b are formed on or over the silicon substrate. The P-type impurities in the P-type silicon substrate form the channel region 102 , the well region and the substrate intrinsic region 100 . Afterwards, the gate material is deposited and grown on the top of the oxide layer 105 in the recessed region of the silicon substrate to form the transistor gate 106 . Pairs of access transistors 110a, 110b in a memory array are isolated by shallow trench isolation 103 in the silicon substrate. Therefore, the channel lengths of the recessed channels 111a, 111b of the paired access transistors 110a, 110b are increased compared to existing planar transistors using the same minimum feature generation process as in FIG. 1 . Applying the recessed channel to the DRAM access transistor has effectively improved the charge retention time of the storage capacitor by reducing the "off state" leakage current of the access transistor. And the scalability (scalability) of the DRAM process can be extended down to the 20nm generation. On the other hand, the application of floating gate recessed channel transistors can solve the scaling problems of semiconductor nonvolatile memory, such as channel length, floating gate interference, and high aspect ratio. First, like the access transistors 110a, 110b of the advanced DRAM process technology generation, the floating gate recessed channel transistor increases the channel length by recessing the channel into the silicon substrate. Second, the floating gate is not exposed on the silicon surface, but is disposed inside the silicon substrate with ground potential, and the cell-to-cell threshold voltage interference between the floating gates is also minimized. Third, in the silicon substrate, the floating gate is recessed to correspond to the recessed channel of the semiconductor non-volatile memory, which can solve the tunneling dielectric layer (tunneling dielectrics)/polysilicon (poly-silicon)/coupling dielectric layer/ The problem of high apparent gate etch ratio for metal film stacks. At the same time, since the gate film stack is fixed inside the silicon substrate, the holding strength of the tall thin gate will also increase.

发明内容Contents of the invention

本发明实施例提供一种凹入式通道半导体非易失性存储装置及其制造方法，以大幅降低半导体非易失性存储器的缩放(scaling)挑战，如通道长度、浮动栅干扰、栅极堆叠蚀刻的高外观比以及形成栅极的机械稳定性。Embodiments of the present invention provide a recessed channel semiconductor non-volatile memory device and a manufacturing method thereof, so as to greatly reduce the scaling challenges of semiconductor non-volatile memory, such as channel length, floating gate interference, and gate stacking. High aspect ratio of etching and mechanical stability of gate formation.

为了实现上述目的，本发明提供一种非易失性存储装置，包括：In order to achieve the above object, the present invention provides a non-volatile storage device, comprising:

一基板，具有一个主动区，所述主动区被一场隔离结构所定义，所述主动区上具有一凹入式通道洞；A substrate having an active area, the active area is defined by a field isolation structure, and a recessed channel hole is formed on the active area;

一穿隧氧化层，形成于所述凹入式通道洞的内壁上与所述主动区的表面上；a tunnel oxide layer formed on the inner wall of the recessed channel hole and the surface of the active region;

一电荷储存结构，填满所述凹入式通道洞以及形成于位在所述凹入式通道洞内部分的所述穿隧氧化层上；a charge storage structure filling the recessed channel hole and formed on the tunnel oxide layer at the portion inside the recessed channel hole;

一耦合介电层，形成于所述电荷储存结构与所述场隔离结构上；a coupling dielectric layer formed on the charge storage structure and the field isolation structure;

一控制栅，形成于所述耦合介电层上；以及a control gate formed on the coupling dielectric layer; and

一源极区及一漏极区，形成于所述主动区的上方且邻近所述电荷储存结构。A source region and a drain region are formed above the active region and adjacent to the charge storage structure.

一实施例中，所述穿隧氧化层的厚度介于60埃至100埃之间。In one embodiment, the thickness of the tunnel oxide layer is between 60 angstroms and 100 angstroms.

一实施例中，所述凹入式通道洞成圆形以避免尖锐的硅棱角。In one embodiment, the recessed via holes are rounded to avoid sharp silicon corners.

一实施例中，所述源极区及所述漏极区位在所述非易失性存储装置的装置通道区的上方，以及所述非易失性存储装置的装置通道区是沿着位在所述穿隧氧化层下方的所述凹入式通道洞的外壁而形成。In one embodiment, the source region and the drain region are located above the device channel region of the non-volatile memory device, and the device channel region of the non-volatile memory device is located along the The outer wall of the recessed channel hole under the tunnel oxide layer is formed.

一实施例中，所述电荷储存结构是导电浮动栅、电荷陷阱物质、以及嵌入氧化层的纳米粒子的其中之一。In one embodiment, the charge storage structure is one of a conductive floating gate, a charge trap material, and nanoparticles embedded in an oxide layer.

一实施例中，当所述非易失性存储装置为一导电浮动栅非易失性存储器且无电荷储存于所述电荷储存结构时，一浮动栅电压V_f由以下数学关系式来表示：V_f＝V_cg×C_c/(C_c+C_mos)，其中C_c代表所述电荷储存结构与所述控制栅之间的电容值、C_mos代表所述电荷储存结构与其装置通道之间的电容值、以及V_cg是一施加的控制栅电压。In one embodiment, when the nonvolatile memory device is a conductive floating gate nonvolatile memory and no charge is stored in the charge storage structure, a floating gate voltage V _f is represented by the following mathematical relationship: V _f =V _cg ×C _c /(C _c +C _mos ), wherein C _c represents the capacitance between the charge storage structure and the control gate, and C _mos represents the capacitance between the charge storage structure and its device channel The capacitance value of , and V _cg is an applied control gate voltage.

一实施例中，当所述非易失性存储装置为一导电浮动栅非易失性存储装置时，偏离所述非易失性存储装置的本质临界电压的一临界电压偏移量，由以下数学关系式来表示：V_th＝-Q/C_c，其中，Q是储存于所述电荷储存结构的总电荷以及C_c代表所述电荷储存结构与所述控制栅之间的电容值。In one embodiment, when the nonvolatile storage device is a conductive floating gate nonvolatile storage device, a threshold voltage offset from the intrinsic threshold voltage of the nonvolatile storage device is determined by the following The mathematical relationship is: V _th =-Q/C _c , where Q is the total charge stored in the charge storage structure and C _c represents the capacitance between the charge storage structure and the control gate.

一实施例中，所述场隔离结构至少包含一浅沟槽隔离区。In one embodiment, the field isolation structure at least includes a shallow trench isolation region.

一实施例中，所述电荷储存结构包含：In one embodiment, the charge storage structure includes:

一第一部分，用以充填所述凹入式通道洞；以及a first portion for filling the recessed access hole; and

一第二部分，从所述基板表面凸出。A second portion protrudes from the surface of the substrate.

一实施例中，所述凹入式通道洞的宽度实质上等于所述主动区的宽度。In one embodiment, the width of the recessed channel hole is substantially equal to the width of the active region.

为了实现上述目的，本发明提供一种非易失性存储装置的制造方法，包含：In order to achieve the above object, the present invention provides a method for manufacturing a non-volatile memory device, comprising:

在一基板上，形成一场隔离结构，所述场隔离结构定义一主动区；On a substrate, a field isolation structure is formed, and the field isolation structure defines an active area;

在所述主动区的第一部分，形成一凹入式通道洞；In the first part of the active area, a recessed channel hole is formed;

于所述凹入式通道洞的内壁上与所述主动区的表面上，形成一穿隧氧化层；forming a tunnel oxide layer on the inner wall of the recessed channel hole and the surface of the active region;

在所述穿隧氧化层上，沉积一电荷储存层，以填满所述凹入式通道洞；depositing a charge storage layer on the tunnel oxide layer to fill up the recessed channel hole;

于所述电荷储存层上，沉积一耦合介电层；depositing a coupling dielectric layer on the charge storage layer;

于所述耦合介电层上，形成一金属栅极层；forming a metal gate layer on the coupling dielectric layer;

蚀刻去除部分所述金属栅极层、部分所述耦合介电层以及部分所述电荷储存层，以形成一控制栅以及一电荷储存结构，其中所述耦合介电层介于所述控制栅以及所述电荷储存结构之间；以及Etching and removing part of the metal gate layer, part of the coupling dielectric layer and part of the charge storage layer to form a control gate and a charge storage structure, wherein the coupling dielectric layer is interposed between the control gate and the charge storage layer. between said charge storage structures; and

于邻近所述电荷储存结构的所述主动区的第二部分，形成一源极区及一漏极区。A source region and a drain region are formed in a second portion of the active region adjacent to the charge storage structure.

一实施例中，所述形成所述凹入式通道洞的步骤包含：In one embodiment, the step of forming the recessed channel hole includes:

蚀刻去除所述主动区的第一部分至一蚀刻深度，以形成所述基板上的所述凹入式通道洞，以致于所述凹入式通道洞的宽度实质上等于所述主动区的宽度；以及etching away a first portion of the active region to an etching depth to form the recessed channel hole on the substrate, such that a width of the recessed channel hole is substantially equal to a width of the active region; as well as

使所述凹入式通道洞形成圆形，以避免尖锐的硅棱角。The recessed via holes are rounded to avoid sharp silicon corners.

一实施例中，所述穿隧氧化层的厚度介于60埃至100埃。In one embodiment, the tunnel oxide layer has a thickness ranging from 60 angstroms to 100 angstroms.

一实施例中，所述形成所述源极区及所述漏极区的步骤包含：In one embodiment, the step of forming the source region and the drain region includes:

于邻近所述电荷储存结构的所述主动区的第二部分以及所述非易失性存储装置的装置通道的上方，形成所述源极区及所述漏极区。The source region and the drain region are formed adjacent to the second portion of the active region of the charge storage structure and over a device channel of the nonvolatile memory device.

一实施例中，所述电荷储存结构是导电浮动栅、电荷陷阱物质、以及嵌入氧化层的纳米粒子的其中之一。In one embodiment, the charge storage structure is one of a conductive floating gate, a charge trap material, and nanoparticles embedded in an oxide layer.

一实施例中，所述形成所述场隔离结构的步骤包含：In one embodiment, the step of forming the field isolation structure includes:

在所述基板上，形成至少一浅沟槽隔离区，其中所述至少一浅沟槽隔离区定义所述主动区。On the substrate, at least one shallow trench isolation region is formed, wherein the at least one shallow trench isolation region defines the active region.

一实施例中，所述蚀刻去除的步骤更包含：In one embodiment, the step of etching and removing further includes:

形成所述电荷储存结构，其中所述电荷储存结构包含：forming the charge storage structure, wherein the charge storage structure comprises:

一第一部分，用以充填所述凹入式通道洞；以及a first portion for filling the recessed access hole; and

一第二部分，从所述基板表面凸出。A second portion protrudes from the surface of the substrate.

一实施例中，所述形成所述源极区及所述漏极区的步骤包含：In one embodiment, the step of forming the source region and the drain region includes:

使杂质扩散进入所述主动区的第二部分，以形成邻近所述电荷储存结构的所述源极区及所述漏极区。Impurities are diffused into a second portion of the active region to form the source region and the drain region adjacent to the charge storage structure.

一实施例中，所述形成所述源极区及所述漏极区的步骤包含：In one embodiment, the step of forming the source region and the drain region includes:

对所述主动区的第二部分，布植杂质以形成邻近所述电荷储存结构的所述源极区及所述漏极区。For a second portion of the active region, impurities are implanted to form the source region and the drain region adjacent to the charge storage structure.

本发明可以大幅降低半导体非易失性存储器的缩放挑战，如通道长度、浮动栅干扰、栅极堆叠蚀刻的高外观比以及形成栅极的机械稳定性。The present invention can greatly reduce the scaling challenges of semiconductor non-volatile memory, such as channel length, floating gate disturbance, high aspect ratio of gate stack etch, and mechanical stability of gate formation.

附图说明Description of drawings

为更好地理解本发明及其具体实施方式，下面将参考本发明实施例的附图，对本发明实施例中的技术方案进行清楚、完整地描述，其中：In order to better understand the present invention and its specific implementation, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention, wherein:

图1显示现有凹入式通道晶体管的剖面图，该现有凹入式通道晶体管在DRAM存储器单元中作为存取晶体管。FIG. 1 shows a cross-sectional view of a conventional recessed access transistor used as an access transistor in a DRAM memory cell.

图2显示本发明凹入式通道半导体NVM装置的示意图。FIG. 2 shows a schematic diagram of a recessed channel semiconductor NVM device of the present invention.

图3显示本发明一实施例的浮动栅型凹入式通道半导体NVM装置的等效电路的示意图。FIG. 3 shows a schematic diagram of an equivalent circuit of a floating gate recessed channel semiconductor NVM device according to an embodiment of the present invention.

图4a与图4b分别显示图2凹入式通道半导体NVM装置的两个程序化(programming)方法：通道热电子注入方法以及傅勒-诺得翰穿隧方法。4a and 4b respectively show two programming methods of the recessed channel semiconductor NVM device of FIG. 2: the channel hot electron injection method and the Führer-Nordheim tunneling method.

图5a与图5b分别显示图2凹入式通道半导体NVM装置的两个抹除(erase)方法：傅勒-诺得翰穿隧方法以及带间热电子注入方法。5a and 5b respectively show two erasing methods of the recessed channel semiconductor NVM device of FIG. 2: the Führer-Nordheim tunneling method and the interband hot electron injection method.

图6显示本发明一实施例的NAND型单元阵列的凹入式通道半导体NVM装置的示意图。FIG. 6 shows a schematic diagram of a recessed channel semiconductor NVM device of a NAND cell array according to an embodiment of the present invention.

图7显示图6中NAND型单元阵列的凹入式通道半导体NVM装置的俯视图。FIG. 7 shows a top view of the recessed channel semiconductor NVM device of the NAND cell array in FIG. 6 .

图8a显示一反向的(reverse)控制栅遮罩，是使用于图6中NAND型单元阵列的凹入式通道洞蚀刻工艺(process)。FIG. 8a shows a reverse control gate mask, which is used for the recessed channel hole etching process of the NAND cell array in FIG. 6 .

图8b与图8c分别显示，在图6中NAND型单元阵列实施浅沟槽隔离区工艺及凹入式通道洞蚀刻工艺之后，线AA’与线BB’(其位置如图7所示)的剖面图。Figure 8b and Figure 8c respectively show that after the shallow trench isolation region process and the recessed channel hole etching process are implemented in the NAND cell array in Figure 6, the line AA' and the line BB' (its position is shown in Figure 7) Sectional view.

图9a显示使用于图6的NAND型单元阵列的第一多晶硅遮罩。FIG. 9 a shows a first polysilicon mask used in the NAND cell array of FIG. 6 .

图9b与图9c分别显示，在图6中NAND型单元阵列实施第一多晶硅蚀刻工艺之后，线AA’与线BB’(其位置如图7所示)的剖面图。9b and 9c respectively show cross-sectional views of lines AA' and BB' (positions shown in FIG. 7 ) after the first polysilicon etching process is performed on the NAND cell array in FIG. 6 .

图10a显示使用于图6的NAND型单元阵列的控制栅遮罩。FIG. 10 a shows a control gate mask used in the NAND cell array of FIG. 6 .

图10b与图10c分别显示，在图6中NAND型单元阵列实施控制栅蚀刻工艺之后，线AA’与线BB’(其位置如图7所示)的剖面图。FIG. 10b and FIG. 10c respectively show cross-sectional views of line AA' and line BB' (the positions of which are shown in FIG. 7 ) after the control gate etching process is performed on the NAND cell array in FIG. 6 .

图11a与图11b分别显示进行N型杂质离子布植以形成图6中NAND型单元阵列的源极/漏极电极。11a and 11b respectively show the implantation of N-type impurity ions to form the source/drain electrodes of the NAND cell array in FIG. 6 .

图12显示本发明另一实施例的NOR型单元阵列的凹入式通道半导体NVM装置的示意图。FIG. 12 shows a schematic diagram of a recessed channel semiconductor NVM device of a NOR cell array according to another embodiment of the present invention.

图13显示图12中NOR型单元阵列的凹入式通道半导体NVM装置的俯视图。FIG. 13 shows a top view of the recessed channel semiconductor NVM device of the NOR cell array in FIG. 12 .

图14a显示一反向的控制栅遮罩(mask)，使用于图13中NOR型单元阵列的凹入式通道洞蚀刻工艺中。FIG. 14a shows an inverted control gate mask used in the recessed channel hole etching process for the NOR cell array in FIG. 13 .

图14b与图14c分别显示，在图12中NOR型单元阵列实施浅沟槽隔离区工艺及凹入式通道洞蚀刻工艺之后，线AA’与线BB’(其位置如图13所示)的剖面图。Figure 14b and Figure 14c respectively show that after the shallow trench isolation region process and the recessed channel hole etching process are implemented in the NOR cell array in Figure 12, the line AA' and the line BB' (its position is shown in Figure 13) Sectional view.

图15a显示使用于图13的NOR型单元阵列的第一多晶硅遮罩。FIG. 15a shows a first polysilicon mask used in the NOR cell array of FIG. 13 .

图15b与图15c分别显示，在图12中NOR型单元阵列实施第一多晶硅蚀刻工艺之后，线AA’与线BB’(其位置如图13所示)的剖面图。15b and 15c respectively show cross-sectional views of line AA' and line BB' (the positions of which are shown in FIG. 13 ) after the first polysilicon etching process is performed on the NOR cell array in FIG. 12 .

图16a显示使用于图13的NOR型单元阵列的控制栅遮罩。FIG. 16a shows a control gate mask used in the NOR cell array of FIG. 13 .

图16b与图16c分别显示，在图12中NOR型单元阵列实施控制栅蚀刻工艺之后，线AA’与线BB’(其位置如图13所示)的剖面图。FIG. 16b and FIG. 16c respectively show cross-sectional views of line AA' and line BB' (the positions of which are shown in FIG. 13 ) after the control gate etching process is implemented in the NOR cell array in FIG. 12 .

图17a与图17b分别显示进行N型杂质离子布植以形成图12中NOR型单元阵列的源极/漏极电极。FIG. 17a and FIG. 17b respectively show the implantation of N-type impurity ions to form the source/drain electrodes of the NOR-type cell array in FIG. 12 .

100 基板本质区100 Substrate Intrinsic Region

102 通道区102 access area

103 浅沟槽隔离区103 shallow trench isolation

104a、104b、104c N型共源极/漏极区104a, 104b, 104c N-type common source/drain regions

105 氧化层105 oxide layer

106 晶体管栅极106 Transistor gate

110a、110b 存取晶体管110a, 110b access transistors

111a、111b 凹入式通道111a, 111b Recessed channel

118、1720 N型源极/漏极电极118, 1720 N-type source/drain electrodes

200 凹入式通道半导体非易失性存储装置200 recessed channel semiconductor non-volatile memory device

201 源极电极201 Source electrode

202 漏极电极202 Drain electrode

203 电荷储存物质203 Charge storage substances

204 控制栅204 control grid

205 凹入式通道205 Recessed Channel

206 穿隧介电层206 tunnel dielectric layer

207 耦合介电层207 Coupling Dielectric Layer

300 浮动栅NVM装置300 Floating Gate NVM Devices

303 浮动栅303 floating gate

304 控制栅304 control grid

305 MOSFET通道305 MOSFET channels

310 浮动栅凹入式通道MOSFET装置310 Floating Gate Recessed Channel MOSFET Device

600 NAND型单元阵列600 NAND cell array

601 凹入式通道半导体NVM装置601 Recessed channel semiconductor NVM device

602 位线选择晶体管602 bit line select transistors

603 共源极晶体管603 common source transistor

610 NAND串610 NAND strings

630 垂直位线630 vertical bit lines

640 水平共源极位线640 horizontal common source bit lines

702、1302 正方形图案区702, 1302 square pattern area

800、1400 阵列P井800, 1400 array P wells

801、1401 主动区801, 1401 active area

802、1402 场隔离氧化区802, 1402 field isolation oxidation area

803、1403 凹入式通道洞803, 1403 Recessed Access Hole

825、1425 反向的控制栅遮罩825, 1425 inverted control grid mask

910、1510 穿隧氧化物910, 1510 tunnel oxide

920、1520 第一多晶硅层920, 1520 first polysilicon layer

925、1525 第一多晶硅遮罩925, 1525 first polysilicon mask

1001、1601 高k耦合介电膜堆叠1001, 1601 High-k coupling dielectric film stack

1002 栅极材料1002 Gate material

1005、1625 控制栅遮罩1005, 1625 Control grid mask

1100、1710 N型杂质1100, 1710 N-type impurities

1200 NOR型单元阵列1200 NOR cell array

1210 NOR对装置1210 NOR pair device

1220 共源极线1220 common source line

1230 字线1230 word line

1240 位线1240 bit line

1602 第二金属栅极材料1602 Second metal gate material

具体实施方式Detailed ways

以下详细说明仅为示例，而非限制。应了解的是，可使用其他实施例，且对结构可进行各种变形或变更，均应落入本发明请求项的范围。而且，应了解的是，本说明书使用的语法及术语仅为进行说明，而不应被视为限制。熟悉本领域者应可理解，本说明书中方法及示意图的实施例仅为示例，而非限制。因本说明书的揭露而了解本发明精神之熟悉本领域者，可使用其他实施例，均应落入本发明请求项的范围。The following detailed descriptions are examples only, not limitations. It should be understood that other embodiments can be used, and various modifications or changes can be made to the structure, all of which should fall within the scope of the claims of the present invention. Also, it is to be understood that the grammar and terminology used in this specification are for description only and should not be regarded as limiting. Those skilled in the art should understand that the methods and schematic diagrams in this specification are only examples, not limitations. Those skilled in the art who understand the spirit of the present invention due to the disclosure of this specification can use other embodiments, which should fall within the scope of the claims of the present invention.

图2为本发明凹入式通道半导体非易失性存储器(NVM)装置200的示意图。请参考图2，凹入式通道半导体NVM装置200的源极电极201与漏极电极202设在装置通道205的上方，电荷储存物质203沿着凹入式通道半导体NVM装置200的凹入式通道205嵌入形成于穿隧介电层206的顶部。用以储存非易失性电荷的电荷储存物质203可以是导电浮动栅(如多晶硅或金属)、电荷陷阱(trap)物质(如氮化物(nitride)或二氧化铪(hafnium oxide))、或嵌入氧化层的纳米粒子(nano-particles)。控制栅(control gate)204沿着沉积在电荷储存物质203表面的耦合介电层207而被包覆。工艺完成后，半导体NVM装置200形成的金氧半场效晶体管(MOSFET)具有电荷储存物质位在控制栅及凹入式通道之间。当施加电压至控制栅204时，施加的电场通过电荷储存物质203的电容耦合而被传输至凹入式通道205。图3是假设浮动栅303内没有多余的电荷的情况下，显示一导电浮动栅NVM装置300的串联电容器等效电路。在导电浮动栅303上的电压V_f＝V_cg×C_c/(C_c+C_mos)，其中，C_c是控制栅304与浮动栅303之间的电容值、C_mos是浮动栅303与MOSFET通道305之间的电容值、及V_cg是施加的控制栅电压。当浮动栅电压V_f大于浮动栅凹入式通道MOSFET装置310的临界电压时，半导体NVM装置300的凹入式通道会被反向(inverted)，如同DRAM中凹入式通道MOSFET装置的类似切换特性。通过施加控制栅电压的电容耦合，浮动栅电压V_f大于及小于浮动栅凹入式通道MOSFET装置310的临界电压可分别导通(turn on)及关闭(turn off)凹入式通道NVM装置300。因此，凹入式通道浮动栅NVM装置300的源极-漏极电流特性对控制栅电压的关系取决于控制栅-浮动栅电压关系V_f＝V_cg×C_c/(C_c+C_mos)以及用浮动栅电压V_f替代浮动栅凹入式通道MOSFET装置310的栅极电压。FIG. 2 is a schematic diagram of a recessed channel semiconductor non-volatile memory (NVM) device 200 of the present invention. Please refer to FIG. 2, the source electrode 201 and the drain electrode 202 of the recessed channel semiconductor NVM device 200 are arranged above the device channel 205, and the charge storage material 203 is along the recessed channel of the recessed channel semiconductor NVM device 200. An embedding 205 is formed on top of the tunneling dielectric layer 206 . The charge storage material 203 used to store non-volatile charges can be a conductive floating gate (such as polysilicon or metal), a charge trap (trap) material (such as nitride (nitride) or hafnium oxide (hafnium oxide)), or embedded Oxide layer of nanoparticles (nano-particles). The control gate (control gate) 204 is coated along the coupling dielectric layer 207 deposited on the surface of the charge storage material 203 . After the process is completed, the semiconductor NVM device 200 forms a metal oxide semiconductor field effect transistor (MOSFET) with a charge storage material located between the control gate and the recessed channel. When a voltage is applied to the control gate 204 , the applied electric field is transmitted to the recessed channel 205 through the capacitive coupling of the charge storage material 203 . FIG. 3 shows a series capacitor equivalent circuit of a conductive floating gate NVM device 300 assuming that there is no excess charge in the floating gate 303 . The voltage V _f on the conductive floating gate 303 =V _cg ×C _c /(C _c +C _mos ), where C _c is the capacitance between the control gate 304 and the floating gate 303, and C _mos is the capacitance between the floating gate 303 and the floating gate 303. The capacitance between MOSFET channels 305, and V _cg is the applied control gate voltage. When the floating gate voltage _Vf is greater than the threshold voltage of the floating gate recessed channel MOSFET device 310, the recessed channel of the semiconductor NVM device 300 will be inverted (inverted), just like the similar switching of the recessed channel MOSFET device in DRAM characteristic. By applying the capacitive coupling of the control gate voltage, the floating gate voltage V _f is greater than and less than the threshold voltage of the floating gate recessed channel MOSFET device 310 to turn on (turn on) and turn off (turn off) the recessed channel NVM device 300 respectively. . Therefore, the source-drain current characteristic versus control gate voltage of the recessed channel floating gate NVM device 300 depends on the control gate-floating gate voltage relationship V _f =V _cg ×C _c /(C _c +C _mos ) And replacing the gate voltage of the floating gate recessed channel MOSFET device 310 with the floating gate voltage _Vf .

根据装置通道与栅极之间的电荷守恒定律，当负电荷的电子被注入凹入式通道NVM装置200的电荷储存物质203时，凹入式通道NVM装置200的临界电压会移动至较正/高的临界电压；当电子从电荷储存物质中被移除或注入正电荷的电洞时，凹入式通道NVM装置200的临界电压会移动至较低的临界电压。如图3所示之浮动栅NVM装置300的串联电容器等效电路的理想导电浮动栅303，偏离凹入式通道NVM装置本质临界电压V_thin(定义为无净电荷的浮动栅303(电性中立)之临界电压)之一临界电压偏移量以数学关系式表示为ΔV_th＝-Q/C_c，其中，Q是储存于导电浮动栅303的净电荷。在将凹入式通道半导体NVM装置300曝露于紫外线下以释出陷入浮动栅303与通道介电层(未显示)内的额外残留电荷之后，通过量测其临界电压，可得到凹入式通道半导体NVM装置300的本质临界电压V_thin。程序化/抹除后的凹入式通道NVM装置的电气特性确实地从本质临界电压V_thin平行移开，而具有的临界电压等于V_th＝V_thin+ΔV_th，因为程序化/抹除动作之后，陷入浮动栅303与通道介电层内的极少数电荷是可忽视的。关于凹入式通道半导体NVM装置200的应用，凹入式通道半导体NVM装置200的临界电压状态可用来代表数位数据，例如，凹入式通道半导体NVM装置200的高临界电压状态可用来代表数位值0，而凹入式通道半导体NVM装置200的低临界电压状态可用来代表数位值1。通过施加一控制栅电压至凹入式通道半导体NVM装置200所得到的回应的导通/截止(on/off)电流，来分辨凹入式通道半导体NVM装置200的临界电压状态。用来改变装置临界电压并且储存在凹入式通道半导体NVM装置的电荷储存物质中的电荷须维持至少十年，而无须再更新(refresh)，以致于在可操作的生命周期期间，半导体NVM装置的临界电压只有些微改变。换言之，在可操作的生命周期期间，以凹入式通道半导体NVM装置的临界电压来代表的储存数据是非易失性的。According to the law of conservation of charge between the device channel and the gate, when negatively charged electrons are injected into the charge storage material 203 of the recessed channel NVM device 200, the threshold voltage of the recessed channel NVM device 200 will move to a more positive/ High threshold voltage; when electrons are removed from the charge storage material or injected into positively charged holes, the threshold voltage of the recessed channel NVM device 200 shifts to a lower threshold voltage. The ideal conductive floating gate 303 of the series capacitor equivalent circuit of the floating gate _NVM device 300 shown in FIG. ) of the threshold voltage) is represented by a mathematical relationship as ΔV _th =−Q/C _c , where Q is the net charge stored in the conductive floating gate 303 . The recessed channel can be obtained by measuring the threshold voltage after exposing the recessed channel semiconductor NVM device 300 to ultraviolet light to release the extra residual charge trapped in the floating gate 303 and the channel dielectric layer (not shown). Intrinsic threshold voltage V _thin of the semiconductor NVM device 300 . The electrical characteristics of the program/erase recessed channel NVM device are indeed parallel shifted from the intrinsic threshold voltage _Vthin with a threshold voltage equal to _Vth = _Vthin + _ΔVth , because the program/erase action Afterwards, the very small amount of charge trapped in the floating gate 303 and the channel dielectric layer is negligible. Regarding the application of the recessed channel semiconductor NVM device 200, the threshold voltage state of the recessed channel semiconductor NVM device 200 can be used to represent digital data, for example, the high threshold voltage state of the recessed channel semiconductor NVM device 200 can be used to represent digital values 0, while the low threshold voltage state of the recessed channel semiconductor NVM device 200 can be used to represent a digital value of 1. The threshold voltage state of the recessed channel semiconductor NVM device 200 can be determined by applying a control gate voltage to the recessed channel semiconductor NVM device 200 to obtain a corresponding on/off current. The charge used to change the threshold voltage of the device and stored in the charge storage material of the recessed channel semiconductor NVM device must be maintained for at least ten years without refreshing (refresh), so that during the operational life cycle, the semiconductor NVM device The threshold voltage of the only slightly changed. In other words, the stored data represented by the threshold voltage of the recessed channel semiconductor NVM device is non-volatile during the operational lifetime.

程序化(programming)一凹入式通道半导体NVM装置200就是将电子注入凹入式通道半导体NVM装置200的电荷储存物质。两个主要程序化该凹入式通道半导体NVM装置200的方法：图4a显示的现有通道热电子注入(Channel Hot Electron Injection)法以及图4b显示的现有傅勒-诺得翰穿隧(Fowler-Nordheim tunneling)法。带间(band-to-band)热电子穿隧方法也适用于程序化P型NVM装置。抹除操作则是将电子从该凹入式通道半导体NVM装置的电荷储存物质中移除或注入少量电洞，图5a显示的傅勒-诺得翰穿隧法以及图5b显示的带间热电子注入法是两个主要方法，用来移除或消灭位在该凹入式通道半导体NVM装置200的电荷储存物质中的电子。根据MOSFET操作机制的相同物理定律，适用于平面型半导体NVM装置的程序化方法及抹除方法，也适用于本发明凹入式通道半导体NVM装置200。Programming a recessed channel semiconductor NVM device 200 is to inject electrons into the charge storage material of the recessed channel semiconductor NVM device 200 . There are two main methods of programming the recessed channel semiconductor NVM device 200: the existing channel hot electron injection (Channel Hot Electron Injection) method shown in FIG. 4a and the existing Fowler-Nordheim tunneling ( Fowler-Nordheim tunneling) method. The band-to-band hot electron tunneling approach is also suitable for programming P-type NVM devices. The erasing operation is to remove electrons from the charge storage material of the recessed channel semiconductor NVM device or inject a small number of holes, the Fowler-Nordheim tunneling method shown in Figure 5a and the interband heat shown in Figure 5b Electron injection methods are two main methods used to remove or destroy electrons located in the charge storage material of the recessed channel semiconductor NVM device 200 . The programming and erasing methods applicable to planar semiconductor NVM devices are also applicable to the recessed channel semiconductor NVM device 200 of the present invention according to the same physical laws of MOSFET operation mechanism.

根据本发明一实施例，图6显示由多个凹入式通道半导体NVM装置601组成的m×n的NAND型单元阵列600的示意图。该NAND型单元阵列600包含多个NAND串(string)610，各NAND串610通过其位线(bitline)选择晶体管602，电连接至其对应的垂直位线630，并通过其共源极(common source)晶体管603，电连接至其对应的水平共源极位线CS 640。一行(row)凹入式通道半导体NVM装置601的控制栅连接形成字线620，而一行位线选择晶体管602的栅极以及一行共源极晶体管603的栅极分别连接形成一位线选择线Sel 650以及一共源极选择线SC 660。如图6所示，该m×n的NAND型单元阵列600被规划为具有n条字线、m条位线、一条共源极位线CS、一条位线选择线Sel、一条共源极选择线SC。为说明NAND型快闪存储器阵列600的凹入式通道半导体NVM装置601的工艺，图7显示图6的NAND型快闪存储器阵列的俯视图。相关工艺遮罩以及与其工艺步骤对应的线AA’与线BB’的剖面图如下:(1)对单元阵列600的硅基板分别布植P型杂质与N型杂质以分别形成图8b及图8c中的阵列P井(well)800与深N井(图未示)。(2)实施具主动区(active area)遮罩的浅沟槽隔离工艺模组以将主动区801与场隔离氧化区802分离，如图8b及图8c所示。(3)施加一反向的(reverse)控制栅遮罩(mask)825(如图8a所示)以利用选择式的(selective)反应性离子蚀刻(reactive ionetch，RIE)工艺来蚀刻凹入式通道洞。该选择式RIE工艺蚀刻暴露的基板区以形成多个凹入式通道洞803，而不会蚀刻到单元阵列的场隔离氧化区802。在蚀刻工艺后，单元阵列中的凹入式通道洞803位在正方形图案区702上，如图7的俯视图所示。凹入式通道洞803的宽度(width)实质上等于暴露的主动区801的宽度。进一步，将凹入式通道洞803形成圆形以避免尖锐的硅棱角(corner)产生机械性应力(mechanical stress)以及高电场。图8b(AA’)与图8c(BB’)分别显示实施凹入式通道洞蚀刻工艺之后的最终剖面图。(4)显示于图9b与图9c的穿隧氧化物(tunneling oxide)910，其厚度介于60埃(angstrom)至100埃之间，沿着凹入式通道硅表面而生长在硅表面上。通过化学汽相沉积法(chemical vapor deposition，CVD)，沉积第一多晶硅层920以充填该凹入式通道洞。如图9a所示，利用第一多晶硅遮罩925覆盖住NVM单元阵列主动区(长条型的正方形图案区)，在第一多晶硅蚀刻工艺期间，可以避免在单元阵列的主动区上的第一多晶硅被移除。结果，在第一多晶硅蚀刻工艺完成后，覆盖住单元阵列的场区(field area)以及在单元阵列的范围之外的区域的第一多晶硅完全被移除。图9b与图9c分别显示实施第一多晶硅蚀刻工艺之后，线AA’与线BB’的剖面图。(5)将高-k(介电系数(electrical permittivity))耦合介电膜堆叠(coupling dielectricfilm stack)1001(包含氮化物、氧化铝、二氧化铪(hafnium oxide)、或氧化锆(zirconiumoxide))沉积于第一多晶硅层920的顶部，以形成一薄氧化衬层(liner)，之后，再沉积一第二金属栅极材料1002(如硅化物多晶硅(silicided-polysilicon)、钨多晶硅(tungsten-polysilicon)、氮化钛(titanium nitride)、氮化钽(tantalumnitride)、钽、或铝)于耦合介电膜堆叠1001的顶部。为进行自我对准(selfaligned)栅极蚀刻工艺，利用图10a的控制栅遮罩1005，来蚀刻去除在该阵列主动区上的该栅极材料1002与剩余的第一多晶硅层920，以形成多个控制栅(字线)，如图10b(AA’)与图10c(BB’)分别显示的剖面图。一实施例中，每一个电荷储存结构920(在自我对准栅极蚀刻工艺之后)具有一第一部分，用以充填该凹入式通道洞803，以及一第二部分，从基板表面或主动区801的表面凸出，如图10c所示。为形成MOSFET晶体管栅极(包含存取晶体管栅极Sel及SC)，利用另一个遮罩(图未示)来蚀刻去除该栅极材料以形成一般的晶体管栅极。(6)对硅基板进行N型杂质1100(如砷(arsenic)离子或磷(phosphorous)离子)布植或扩散，以形成N型源极/漏极电极118，如图11a与图11b所示。(7)之后，利用一间隔物(spacer)工艺模组以形成多个MOSFET间隔物。在杂质活化(activation)后，就完成了工艺前端的装置结构，并继续进行布线(wiring)连接的金属化后端工艺。According to an embodiment of the present invention, FIG. 6 shows a schematic diagram of an m×n NAND cell array 600 composed of a plurality of recessed channel semiconductor NVM devices 601 . The NAND cell array 600 includes a plurality of NAND strings (string) 610, each NAND string 610 is electrically connected to its corresponding vertical bit line 630 through its bit line (bitline) selection transistor 602, and through its common source (common source) transistor 603, electrically connected to its corresponding horizontal common source bit line CS 640. The control gates of a row of recessed channel semiconductor NVM devices 601 are connected to form a word line 620, and the gates of a row of bit line selection transistors 602 and the gates of a row of common source transistors 603 are respectively connected to form a bit line selection line Sel 650 and a common source select line SC 660 . As shown in FIG. 6, the m×n NAND cell array 600 is planned to have n word lines, m bit lines, one common source bit line CS, one bit line selection line Sel, one common source selection line Line SC. To illustrate the process of the recessed channel semiconductor NVM device 601 of the NAND flash memory array 600 , FIG. 7 shows a top view of the NAND flash memory array of FIG. 6 . The cross-sectional views of the relevant process mask and the line AA' and line BB' corresponding to the process steps are as follows: (1) P-type impurities and N-type impurities are respectively implanted on the silicon substrate of the cell array 600 to form Figures 8b and 8c respectively. Array P wells (well) 800 and deep N wells (not shown). (2) Implement a shallow trench isolation process module with an active area mask to separate the active area 801 from the field isolation oxide area 802, as shown in FIG. 8b and FIG. 8c. (3) Apply a reverse (reverse) control gate mask (mask) 825 (as shown in FIG. passage hole. The selective RIE process etches the exposed substrate area to form a plurality of recessed channel holes 803 without etching the field isolation oxide region 802 of the cell array. After the etching process, the recessed channel hole 803 in the cell array is located on the square pattern area 702 , as shown in the top view of FIG. 7 . The width of the recessed channel hole 803 is substantially equal to the width of the exposed active region 801 . Further, the concave channel hole 803 is rounded to avoid mechanical stress and high electric field generated by sharp silicon corners. 8b (AA') and FIG. 8c (BB') respectively show the final cross-sectional views after performing the recessed channel hole etching process. (4) The tunneling oxide (tunneling oxide) 910 shown in FIG. 9b and FIG. 9c has a thickness between 60 Angstroms ( angstrom) to 100 Angstroms, grown on the silicon surface along the recessed channel silicon surface. A first polysilicon layer 920 is deposited by chemical vapor deposition (CVD) to fill the recessed channel hole. As shown in Figure 9a, the NVM cell array active area (elongated square pattern area) is covered by the first polysilicon mask 925, during the first polysilicon etching process, the active area of the cell array can be avoided on the first polysilicon is removed. As a result, after the first polysilicon etching process is completed, the first polysilicon covering the field area of the cell array and the area outside the range of the cell array is completely removed. 9b and 9c respectively show cross-sectional views of line AA' and line BB' after performing the first polysilicon etching process. (5) A high-k (electrical permittivity) coupling dielectric film stack (coupling dielectric film stack) 1001 (including nitride, aluminum oxide, hafnium oxide, or zirconium oxide) Deposited on top of the first polysilicon layer 920 to form a thin oxide liner (liner), and then deposit a second metal gate material 1002 (such as silicided-polysilicon, tungsten polysilicon (tungsten -polysilicon), titanium nitride, tantalumnitride, tantalum, or aluminum) on top of the coupling dielectric film stack 1001. To perform a self-aligned gate etch process, the gate material 1002 and the remaining first polysilicon layer 920 on the active region of the array are etched away using the control gate mask 1005 of FIG. A plurality of control gates (word lines) are formed, as shown in the cross-sectional views of FIG. 10b (AA') and FIG. 10c (BB'), respectively. In one embodiment, each charge storage structure 920 (after the self-aligned gate etch process) has a first portion for filling the recessed channel hole 803, and a second portion for removing from the substrate surface or active area. The surface of 801 is convex, as shown in Figure 10c. To form the MOSFET transistor gate (including the access transistor gate Sel and SC), another mask (not shown) is used to etch and remove the gate material to form a general transistor gate. (6) Implant or diffuse N-type impurities 1100 (such as arsenic (arsenic) ions or phosphorous (phosphorous) ions) on the silicon substrate to form N-type source/drain electrodes 118, as shown in FIG. 11a and FIG. 11b . (7) After that, a spacer process module is used to form a plurality of MOSFET spacers. After impurity activation, the device structure of the front-end process is completed, and the metallization back-end process of wiring connection is continued.

根据本发明另一实施例，图12及图13分别显示由多个凹入式通道半导体NVM装置组成的NOR型单元阵列1200的示意图与俯视图。规划(configure)多个NOR对(NOR-pair)装置1210以形成图12的NOR型单元阵列1200。一行NOR对装置1210的共用源极电极形成一共源极线1220，而一行NOR对装置1210的控制栅极形成一字线1230，一列(column)NOR对装置1210的漏极电极形成一位线1240。该m×n的NOR型单元阵列1200被规划为m列及n行的凹入式通道NVM装置，具有n条字线1230、m条位线1240、n/2条共源极位线1220。为说明NOR型单元阵列1200之凹入式通道半导体NVM装置的工艺，请参考图13的遮罩图以及线AA’与线BB’的剖面图，与以下对应的工艺步骤:(1)对硅基板分别布植P型杂质与N型杂质以分别形成图14b及图14c中的阵列P井1400与深N井(图未示)。(2)实施具主动区遮罩的浅沟槽隔离工艺模组以将主动区1401与场隔离氧化区1402分离，如图14b及图14c所示。(3)施加一反向的控制栅遮罩1425(如图14a所示)以利用选择式的反应性离子蚀刻(RIE)工艺来蚀刻凹入式通道洞1403。该选择式RIE工艺蚀刻暴露的基板区至一个深度，而不会蚀刻到单元阵列的场隔离氧化区1402。在蚀刻工艺后，单元阵列中的凹入式通道洞1403位在正方形图案区1302上，如图13的俯视图所示。凹入式通道洞1403的宽度实质上等于暴露的主动区1401的宽度。进一步，将凹入式通道洞1403形成圆形以避免尖锐的硅棱角产生机械性应力以及高电场。图14b(AA’)与图14c(BB’)分别显示实施凹入式通道洞蚀刻工艺之后的剖面图。(4)显示于图15b与图15c的穿隧氧化物(tunneling oxide)1510，其厚度介于60埃至100埃之间，沿着凹入式通道硅表面而生长在硅表面上。通过化学汽相沉积法(CVD)，沉积第一多晶硅层1520以充填该凹入式通道洞1403。如图15a所示，利用第一多晶硅遮罩1525覆盖住NVM单元阵列主动区(正方形图案)，在第一多晶硅蚀刻工艺期间，可以避免在单元阵列的主动区上的第一多晶硅被移除。结果，在第一多晶硅蚀刻工艺完成后，覆盖住单元阵列的场区(field area)以及在单元阵列的范围之外的区域的第一多晶硅完全被移除。图15b与图15c分别显示实施第一多晶硅蚀刻工艺之后，线AA’与线BB’的剖面图。(5)将高-k(介电系数)耦合介电膜堆叠1601(包含氮化物、氧化铝、二氧化铪、或氧化锆)沉积于第一多晶硅层1520的顶部，以形成一薄氧化衬层，之后，再沉积一第二金属栅极材料1602(如硅化物多晶硅、钨多晶硅、氮化钛、氮化钽、钽、或铝)于耦合介电膜堆叠1501的顶部。为进行自我对准栅极蚀刻工艺，利用图16a的控制栅遮罩1625，来蚀刻去除在该阵列主动区上的该栅极材料1602与剩余的第一多晶硅层1520，以形成多个控制栅(字线)，如图16b(AA’)与图16c(BB’)分别显示的剖面图。一实施例中，每一个电荷储存结构1520(在自我对准栅极蚀刻工艺之后)具有一第一部分，用以充填该凹入式通道洞1403，以及一第二部分，从基板表面或主动区1401的表面凸出，如图16c所示。为形成MOSFET晶体管栅极，利用另一个遮罩(图未示)来蚀刻去除该栅极材料以形成一般的晶体管栅极。(6)对硅基板进行N型杂质1710(如砷离子或磷离子)布植或扩散，以形成N型源极/漏极电极1720，如图17a与图17b所示。(7)之后，利用一间隔物工艺模组以形成多个MOSFET间隔物。在杂质活化后，就完成了工艺前端的装置结构，并继续进行布线连接的金属化后端工艺。According to another embodiment of the present invention, FIG. 12 and FIG. 13 respectively show a schematic diagram and a top view of a NOR cell array 1200 composed of a plurality of recessed channel semiconductor NVM devices. A plurality of NOR-pair devices 1210 are configured to form the NOR cell array 1200 of FIG. 12 . A row of NOR pairs forms a common source line 1220 for the common source electrode of device 1210, while a row of NOR pairs forms a word line 1230 for the control gate of device 1210, and a column of NOR pairs forms a bit line 1240 for the drain electrode of device 1210. . The m×n NOR cell array 1200 is planned as a recessed channel NVM device with m columns and n rows, and has n word lines 1230 , m bit lines 1240 , and n/2 common source bit lines 1220 . In order to illustrate the process of the recessed channel semiconductor NVM device of the NOR cell array 1200, please refer to the mask diagram of FIG. The substrate is respectively implanted with P-type impurities and N-type impurities to form the array P wells 1400 and deep N wells (not shown) in FIG. 14b and FIG. 14c respectively. (2) Implement a shallow trench isolation process module with an active area mask to separate the active area 1401 from the field isolation oxide area 1402, as shown in FIG. 14b and FIG. 14c. (3) Apply a reverse control gate mask 1425 (as shown in FIG. 14a ) to etch the recessed via hole 1403 using a selective reactive ion etching (RIE) process. The selective RIE process etches the exposed substrate regions to a depth without etching the field isolation oxide region 1402 of the cell array. After the etching process, the recessed channel hole 1403 in the cell array is located on the square pattern area 1302 , as shown in the top view of FIG. 13 . The width of the recessed channel hole 1403 is substantially equal to the width of the exposed active region 1401 . Further, the concave channel hole 1403 is rounded to avoid mechanical stress and high electric field generated by sharp silicon corners. Figure 14b (AA') and Figure 14c (BB') respectively show cross-sectional views after performing the recessed channel hole etching process. (4) The tunneling oxide 1510 shown in FIG. 15b and FIG. 15c has a thickness between 60 angstroms and 100 angstroms grown on the silicon surface along the recessed channel silicon surface. A first polysilicon layer 1520 is deposited to fill the recessed via hole 1403 by chemical vapor deposition (CVD). As shown in FIG. 15a, by using a first polysilicon mask 1525 to cover the NVM cell array active area (square pattern), during the first polysilicon etching process, the first polysilicon on the active area of the cell array can be avoided. The crystalline silicon is removed. As a result, after the first polysilicon etching process is completed, the first polysilicon covering the field area of the cell array and the area outside the range of the cell array is completely removed. 15b and 15c respectively show cross-sectional views of line AA' and line BB' after performing the first polysilicon etching process. (5) Deposit a high-k (permittivity) coupling dielectric film stack 1601 (including nitride, aluminum oxide, hafnium oxide, or zirconium oxide) on top of the first polysilicon layer 1520 to form a thin The liner layer is oxidized, and then a second metal gate material 1602 (such as silicide polysilicon, tungsten polysilicon, titanium nitride, tantalum nitride, tantalum, or aluminum) is deposited on top of the coupling dielectric film stack 1501 . For the self-aligned gate etching process, the gate material 1602 and the remaining first polysilicon layer 1520 on the active area of the array are etched away using the control gate mask 1625 of FIG. The control gate (word line) is a cross-sectional view shown in FIG. 16b (AA') and FIG. 16c (BB'), respectively. In one embodiment, each charge storage structure 1520 (after the self-aligned gate etch process) has a first portion for filling the recessed channel hole 1403, and a second portion for removing from the substrate surface or active area. The surface of 1401 is convex, as shown in Figure 16c. To form the MOSFET transistor gate, another mask (not shown) is used to etch away the gate material to form a general transistor gate. (6) Implant or diffuse N-type impurities 1710 (such as arsenic ions or phosphorus ions) on the silicon substrate to form N-type source/drain electrodes 1720 , as shown in FIG. 17 a and FIG. 17 b . (7) After that, a spacer process module is used to form a plurality of MOSFET spacers. After impurity activation, the device structure at the front end of the process is completed, and the metallization back-end process of wiring connection is continued.

以上提供的较佳实施例仅用以说明本发明，而非要限定本发明至一明确的类型或示范的实施例。因此，本说明书应视为说明性，而非限制性。显然地，包含长度与宽度的几何形状、栅极物质或穿隧介电层的各种变形或变更，对熟悉本领域者是显而易见的。以上提供的较佳实施例是为了有效说明本发明之要旨及其最佳模式可实施应用，藉以让熟悉本领域者了解本发明之各实施例及各种变更，以适应于特定使用或实施目的。本发明之范围由后附的请求项及其相等物(equivalent)来定义，其中所有的名称(term)皆意指最广泛合理的涵义，除非另有特别指明。因此，「本发明」等类似的用语，并未限缩请求项的范围至一特定实施例，而且，本发明特定较佳实施例的任何参考文献并不意味着限制本发明，以及没有如此的限制会被推定。本发明仅被后附的请求项的范围及精神来定义。依据法规的要求而提供本发明的摘要，以便搜寻者能从本说明书核准的任何专利快速确认此技术揭露书的主题(subject matter)，并非用来诠释或限制请求项的范围及涵义。任何优点及益处可能无法适用于本发明所有的实施例。应了解的是，该行业者可进行各种变形或变更，均应落入后附请求项所定义的本发明之范围。再者，本说明书中的所有元件及构件(component)都没有献给大众的意图，无论后附的请求项是否列举该些元件及构件。The preferred embodiments provided above are only used to illustrate the present invention, but not to limit the present invention to a specific type or exemplary embodiment. Accordingly, the specification is to be regarded as illustrative rather than restrictive. Obviously, various modifications or changes in geometry, gate material or tunneling dielectric, including length and width, will be apparent to those skilled in the art. The preferred embodiments provided above are to effectively illustrate the gist of the present invention and its best mode for implementation and application, so that those familiar with the field can understand the various embodiments and various changes of the present invention, so as to adapt to specific uses or implementation purposes . The scope of the present invention is defined by the appended claims and their equivalents, where all terms are given the broadest reasonable meaning unless specifically indicated otherwise. Accordingly, terminology such as "the present invention" does not limit the scope of the claims to a specific embodiment, and any reference to a specific preferred embodiment of the invention is not meant to limit the invention, and no such Limits will be presumed. The present invention is defined only by the scope and spirit of the appended claims. The abstract of the present invention is provided in accordance with the requirements of laws and regulations, so that searchers can quickly confirm the subject matter of this technical disclosure from any patents approved in this specification, and it is not used to interpret or limit the scope and meaning of the claims. Any advantages and benefits may not apply to all embodiments of the invention. It should be understood that various modifications or changes may be made by those in the industry, all of which shall fall within the scope of the present invention as defined by the appended claims. Furthermore, all elements and components in this specification are not intended to be dedicated to the public, regardless of whether the appended claims list such elements and components.