CN107689377A - Electrical programming memory of three-dimensional containing separation address/data converter - Google Patents

The present invention proposes a kind of electrical programming memory of three-dimensional of separation（3D‑OTP）50, it contains an at least three-dimensional array chip 30 and an at least address/data converter chip 40.Three-dimensional array chip 30 contains multiple 3D OTP storage members being stacked with.At least an address/data converter is located in address/data converter chip 40, rather than in three-dimensional array chip 30.Three-dimensional array chip 30 and address/data converter chip 40 have different rear ends（BEOL）Structure.

含有分离地址/数据转换器的三维一次电编程存储器Three-dimensional one-time electrically programmable memory with separate address/data converters

技术领域technical field

本发明涉及集成电路存储器领域，更确切地说，涉及三维一次电编程存储器(3D-OTP)。The present invention relates to the field of integrated circuit memory, more specifically, to three-dimensional one-time electrically programmable memory (3D-OTP).

背景技术Background technique

三维存储器(3D-M)是一种单体(monolithic)半导体存储器，它含有多个相互堆叠的存储元。3D-M包括三维只读存储器(3D-ROM)和三维随机读取存储器(3D-RAM)。3D-ROM可以进一步划分为三维掩膜编程只读存储器(3D-MPROM)和三维电编程只读存储器(3D-EPROM)。基于它能电编程的次数，3D-EPROM可以进一步分为三维一次电编程存储器(3D-OTP)和三维多次电编程存储器(3D-MTP)。3D-OTP可以是3D-memristor、三维阻变存储器(3D-RRAM或3D-ReRAM)、三维相变存储器(3D-PCM)、3D-PMM(programmable metallizationmemory)、或3D-CBRAM(conductive-bridging random-access memory)等。Three-dimensional memory (3D-M) is a monolithic semiconductor memory that contains multiple memory cells stacked on top of each other. 3D-M includes three-dimensional read-only memory (3D-ROM) and three-dimensional random access memory (3D-RAM). 3D-ROM can be further divided into three-dimensional mask programmed read-only memory (3D-MPROM) and three-dimensional electrically programmed read-only memory (3D-EPROM). Based on the number of times it can be electrically programmed, 3D-EPROM can be further classified into three-dimensional one-time electrically programmable memory (3D-OTP) and three-dimensional multiple-time electrically programmable memory (3D-MTP). 3D-OTP can be 3D-memristor, three-dimensional resistive memory (3D-RRAM or 3D-ReRAM), three-dimensional phase change memory (3D-PCM), 3D-PMM (programmable metallization memory), or 3D-CBRAM (conductive-bridging random -access memory), etc.

美国专利5,835,396(发明人：张国飙；授权日：1998年11月3日)披露了一种3D-ROM，尤其是3D-OTP。如图1A所示，3D-OTP芯片20含有一衬底电路层0K及多个堆叠于衬底电路层0K上并相互堆叠的存储层16A、16B。衬底电路层0K含有晶体管0t及其互连线0i。晶体管0t形成在半导体衬底0中。在这个例子中，衬底互连线0i含有金属层0M1、0M2。在本说明书中，衬底互连线0i采用的金属层0M1、0M2被称为衬底金属层，衬底互连线0i采用材料被称为衬底互连材料。US Patent 5,835,396 (inventor: Guobiao Zhang; date of authorization: November 3, 1998) discloses a 3D-ROM, especially a 3D-OTP. As shown in FIG. 1A , the 3D-OTP chip 20 includes a substrate circuit layer OK and a plurality of storage layers 16A, 16B stacked on the substrate circuit layer OK and mutually stacked. The substrate circuit layer OK contains transistors Ot and their interconnections Oi. A transistor 0t is formed in a semiconductor substrate 0 . In this example, substrate interconnect 0i contains metal layers 0M1, 0M2. In this specification, the metal layers 0M1 and 0M2 used by the substrate interconnection line 0i are referred to as substrate metal layers, and the material used by the substrate interconnection line 0i is referred to as substrate interconnection material.

存储层16A、16B堆叠在衬底电路层0K之上，它们通过接触通道孔(如1av)与衬底0耦合。每个存储层(如16A)含有多条顶地址线(如2a)、底地址线(如1a)和存储元(如1aa)。存储元可以采用二极管、晶体管或别的器件。在各种存储元中，采用二极管的存储元具有最小面积，仅为～4F²(F为最小特征尺寸)。二极管存储元一般形成在顶地址线和底地址线的交叉点处，从而构成一交叉点(cross-point)阵列。这里，二极管泛指任何具有如下特征的二端器件：当其外加电压的数值小于读电压或外加电压的方向与读电压相反时，其电阻远大于其在读电压下的电阻。二极管的例子包括半导体二极管(如p-i-n硅二极管等)和金属氧化物二极管(如氧化钛二极管、氧化镍二极管等)等。The storage layers 16A, 16B are stacked on the substrate circuit layer OK, and they are coupled with the substrate 0 through contact via holes (eg, lav). Each storage layer (eg, 16A) contains a plurality of top address lines (eg, 2a), bottom address lines (eg, 1a) and storage elements (eg, 1aa). The storage element can use diodes, transistors or other devices. Among various memory cells, memory cells employing diodes have the smallest area, only ~4F ² (F is the smallest feature size). Diode memory cells are generally formed at intersections of top and bottom address lines, thereby forming a cross-point array. Here, a diode generally refers to any two-terminal device with the following characteristics: when the value of the applied voltage is smaller than the read voltage or the direction of the applied voltage is opposite to the read voltage, its resistance is much greater than its resistance under the read voltage. Examples of diodes include semiconductor diodes (such as pin silicon diodes, etc.), metal oxide diodes (such as titanium oxide diodes, nickel oxide diodes, etc.), and the like.

存储层16A、16B构成至少一3D-OTP阵列16，而衬底电路层0K则含有3D-OTP阵列16的周边电路。其中，一部分周边电路位于3D-OTP阵列下方，它们被称为阵列下周边 电路；另一部分周边电路位于3D-OTP阵列外边，它们被称为阵列外周边电路18。由于阵列外周边电路18比3D-OTP阵列16含有更少的后端(back-end-of-line，简称为BEOL)薄膜层，阵列外周边电路18上方的空间17不含有存储元，该空间实际上被浪费了。在本说明书中，一个后端薄膜层是指在衬底之上结构中的一个导线层，如存储层16A、16B中的一个地址线层、或互连线0i中的一个互连线层。在图1A中，3D-OTP阵列16含有6个后端薄膜层，包括2个互连线层0M1、0M2、第一存储层16A中的2个地址线层1a、2a、以及第二存储层16B中的地址线层3a、4a；而阵列外周边电路18只含有2个后端薄膜层，包括互连线层0M1、0M2。The storage layers 16A, 16B constitute at least one 3D-OTP array 16 , and the substrate circuit layer OK contains peripheral circuits of the 3D-OTP array 16 . Wherein, a part of peripheral circuits are located below the 3D-OTP array, and they are called peripheral circuits under the array; Since the array peripheral circuit 18 contains fewer back-end-of-line (BEOL) film layers than the 3D-OTP array 16, the space 17 above the array peripheral circuit 18 does not contain memory elements. effectively wasted. In this specification, a back-end film layer refers to a wire layer in the structure above the substrate, such as an address line layer in the memory layers 16A, 16B, or an interconnection layer in the interconnection line 0i. In FIG. 1A, the 3D-OTP array 16 contains 6 back-end film layers, including 2 interconnection layers 0M1, 0M2, 2 address line layers 1a, 2a in the first storage layer 16A, and the second storage layer The address line layers 3a, 4a in 16B; and the peripheral circuit 18 outside the array only contains two back-end thin film layers, including interconnection line layers 0M1, 0M2.

美国专利7,388,476(发明人：Crowley等；授权日：2008年6月3日)披露了一种集成3D-OTP芯片，其三维阵列及其周边电路都集成在同一芯片内。这种集成方式被称为全集成。如图1B所示，该集成3D-OTP芯片20含有三维阵列区域22和周边电路区域28。三维阵列区域22含有多个3D-OTP阵列(如22aa、22ay)及其解码器(如24、24G)。这些解码器24包括本地解码器24和整体解码器24G。其中，本地解码器24对单个3D-OTP阵列的地址/数据进行解码，整体解码器24G将整体地址/数据25解码至单个3D-OTP阵列中。US Patent 7,388,476 (inventor: Crowley et al.; date of authorization: June 3, 2008) discloses an integrated 3D-OTP chip, the three-dimensional array and its peripheral circuits are integrated in the same chip. This kind of integration is called full integration. As shown in FIG. 1B , the integrated 3D-OTP chip 20 includes a three-dimensional array area 22 and a peripheral circuit area 28 . The three-dimensional array area 22 contains multiple 3D-OTP arrays (such as 22aa, 22ay) and their decoders (such as 24, 24G). These decoders 24 include a local decoder 24 and a global decoder 24G. Among them, the local decoder 24 decodes the address/data of a single 3D-OTP array, and the global decoder 24G decodes the overall address/data 25 into a single 3D-OTP array.

周边电路区域28含有让集成3D-OTP芯片20完成基本存储功能的所有周边电路组件，它在三维阵列区域22与主机(即直接使用该芯片20的设备)之间实现电压、数据、地址转换。周边电路28含有读/写电压产生器21和地址/数据转换器29。其中，读/写电压产生器21将电源电压23转换成读电压V_R或/和写(编程)电压V_W；地址/数据转换器29将逻辑地址/数据27与物理地址/数据25相互转换。在本说明书中，逻辑地址/数据27是主机使用的地址/数据；而物理地址/数据25是3D-OTP阵列使用的地址/数据。Peripheral circuit area 28 contains all peripheral circuit components that allow integrated 3D-OTP chip 20 to complete basic storage functions, and it realizes voltage, data, and address conversion between three-dimensional array area 22 and the host (that is, the device that directly uses the chip 20). The peripheral circuit 28 includes a read/write voltage generator 21 and an address/data converter 29 . Wherein, read/write voltage generator 21 converts power supply voltage 23 into read voltage _{VR or/and write (program) voltage VW ;} Address/data converter 29 converts logical address/data 27 and physical address/data 25 . In this specification, the logical address/data 27 is the address/data used by the host; and the physical address/data 25 is the address/data used by the 3D-OTP array.

现有技术的主流观点是：集成降低成本。不幸的是，该观点对3D-OTP不成立。对于3D-OTP来说，由于3D-OTP阵列16采用了繁复的后端工艺，而周边电路18的后端工艺较简单，因此盲目地将3D-OTP阵列16和周边电路18集成的直接结果就是不得不用制造3D-OTP阵列16的昂贵工艺流程来制造周边电路18，这不仅不能降低成本，反而会增加成本。此外，由于周边电路18只能采用与3D-OTP阵列16同样数目的互连线层(如仅为两层)，故周边电路18的设计比较麻烦、性能较差、且所需的芯片面积较大。最后，由于3D-OTP存储元一般会经过高温工艺，周边电路18需要采用耐高温的互连线材料，如钨(W)等，这些材料会使3D-OTP的整体性能下降。The mainstream view in the prior art is: integration reduces costs. Unfortunately, this view does not hold for 3D-OTP. For 3D-OTP, since the 3D-OTP array 16 uses a complicated back-end process, and the back-end process of the peripheral circuit 18 is relatively simple, the direct result of blindly integrating the 3D-OTP array 16 and the peripheral circuit 18 is The peripheral circuit 18 has to be manufactured in an expensive process flow for manufacturing the 3D-OTP array 16, which not only does not reduce the cost, but increases the cost. In addition, because the peripheral circuit 18 can only use the same number of interconnection layers as the 3D-OTP array 16 (for example, only two layers), the design of the peripheral circuit 18 is more troublesome, the performance is poor, and the required chip area is relatively large. big. Finally, since the 3D-OTP storage element generally undergoes a high-temperature process, the peripheral circuit 18 needs to use a high-temperature-resistant interconnection material, such as tungsten (W), which will degrade the overall performance of the 3D-OTP.

发明内容Contents of the invention

本发明的主要目的是提供一种整体价格更为廉价的三维一次电编程存储器(3D-OTP)。The main purpose of the present invention is to provide a three-dimensional one-time electrically programmable memory (3D-OTP) with a lower overall price.

本发明的另一目的是提供一种整体性能更为优异的3D-OTP。Another object of the present invention is to provide a 3D-OTP with better overall performance.

本发明的另一目的是提供一种体积更小的3D-OTP。Another object of the present invention is to provide a 3D-OTP with a smaller volume.

为了实现这些以及别的目的，本发明遵从如下指导原则：将3D-OTP电路及其周边电路分离到不同芯片，以便将它们分别优化。例如说，3D-OTP阵列(三维电路)和至少一周边电路组件(二维电路)被分离成两个芯片—三维阵列芯片和周边电路芯片。相应地，本发明提出一种分离的3D-OTP，它含有一三维阵列芯片和至少一周边电路芯片。三维阵列芯片构建在三维空间中并含有多个功能(存储)层，它含有3D-OTP阵列的第一周边电路组件(该组件被称为芯片中周边电路组件)；周边电路芯片构建在二维空间中并只含有一个功能层，它含有3D-OTP阵列的第二周边电路组件(该组件被称为芯片外周边电路组件)。芯片外周边电路组件是3D-OTP的必须组件，它可以为3D-OTP实现电压、数据和/或地址转换。如果3D-OTP没有芯片外周边电路组件，则它不能独立完成基本存储功能。To achieve these and other objects, the present invention follows the guiding principle of separating the 3D-OTP circuit and its peripheral circuits into different chips so that they can be optimized separately. For example, a 3D-OTP array (three-dimensional circuit) and at least one peripheral circuit component (two-dimensional circuit) are separated into two chips—a three-dimensional array chip and a peripheral circuit chip. Correspondingly, the present invention proposes a separate 3D-OTP, which includes a three-dimensional array chip and at least one peripheral circuit chip. The three-dimensional array chip is built in three-dimensional space and contains multiple functional (storage) layers. It contains the first peripheral circuit component of the 3D-OTP array (this component is called the peripheral circuit component in the chip); the peripheral circuit chip is built in two-dimensional The space does not contain only one functional layer, which contains the second peripheral circuit component of the 3D-OTP array (this component is called an off-chip peripheral circuit component). The peripheral circuit components outside the chip are necessary components for 3D-OTP, which can realize voltage, data and/or address conversion for 3D-OTP. If 3D-OTP has no peripheral circuit components outside the chip, it cannot independently complete the basic storage function.

由于它们被分别设计和制造，分离3D-OTP中的三维阵列芯片和周边电路芯片具有不同的后端(BEOL)结构。周边电路芯片的后端结构可以独立优化，使阵列外周边电路具有更低的成本、更好的性能和较小的面积。总的说来，分离3D-OTP比集成3D-OTP具有更低的整体成本、更好的整体性能和较小的整体面积。Since they are designed and manufactured separately, the three-dimensional array chip and the peripheral circuit chip in the separate 3D-OTP have different back-end (BEOL) structures. The back-end structure of the peripheral circuit chip can be optimized independently, so that the peripheral circuit outside the array has lower cost, better performance and smaller area. Overall, split 3D-OTP has lower overall cost, better overall performance, and smaller overall area than integrated 3D-OTP.

分离的周边电路芯片可以在三个方面与三维阵列芯片不同。首先，周边电路芯片的后端薄膜层的数目要比三维阵列芯片少很多。由于晶圆成本基本和后端薄膜层的数目成正比，周边电路芯片的晶圆成本将远低于三维阵列芯片。在一个实施例中，三维阵列芯片的后端薄膜层数是周边电路芯片的互连线层数的至少两倍。在另一个实施例中，三维阵列芯片的地址线层数远大于周边电路芯片的互连线层数。这些层数的巨大差距可以保证芯片成本差大于采用分离结构后导致的额外封装成本。因此，分离3D-OTP的整体成本低于集成3D-OTP。Separate peripheral circuit chips can differ from three-dimensional array chips in three respects. First of all, the number of back-end film layers of peripheral circuit chips is much less than that of three-dimensional array chips. Since the wafer cost is basically proportional to the number of back-end film layers, the wafer cost of the peripheral circuit chip will be much lower than that of the three-dimensional array chip. In one embodiment, the number of thin film layers at the back end of the three-dimensional array chip is at least twice the number of interconnection wire layers of the peripheral circuit chip. In another embodiment, the number of layers of address lines of the three-dimensional array chip is much greater than the number of layers of interconnection lines of peripheral circuit chips. The large difference in the number of these layers can ensure that the chip cost difference is greater than the additional packaging cost caused by the separation structure. Therefore, the overall cost of separating 3D-OTP is lower than integrating 3D-OTP.

其次，分离3D-OTP中的周边电路芯片比三维阵列芯片含有更多的互连线层，芯片外周边电路的设计更加简单、性能更为优异、芯片面积也更小。因此，分离3D-OTP的整体性能和整体面积优于集成3D-OTP。与集成3D-OTP类似，三维阵列芯片的互连线不包含任何存储结构，其互连线层数是阵列下周边电路和阵列外周边电路中互连线层数较大的那个。注意到，虽然周边电路芯片的互连线层数希望较大，但仍不能超过三维阵列芯片的后端薄膜层数。一个优选的模式是：周边电路芯片的的互连线层数大于三维阵列芯片的互连线层数，但远小于三维阵列芯片的后端薄膜层数。Secondly, the peripheral circuit chip in the separated 3D-OTP contains more interconnection layers than the three-dimensional array chip, the design of the peripheral circuit outside the chip is simpler, the performance is better, and the chip area is smaller. Therefore, the overall performance and overall area of the separated 3D-OTP is better than that of the integrated 3D-OTP. Similar to the integrated 3D-OTP, the interconnection lines of the three-dimensional array chip do not contain any storage structure, and the number of interconnection line layers is the one with the larger number of interconnection line layers in the lower peripheral circuit of the array and the outer peripheral circuit of the array. It should be noted that although the number of layers of interconnection wires in peripheral circuit chips is expected to be large, it still cannot exceed the number of back-end thin film layers of the three-dimensional array chip. A preferred mode is: the number of interconnection layers of the peripheral circuit chip is greater than the number of interconnection layers of the three-dimensional array chip, but much smaller than the number of back-end film layers of the three-dimensional array chip.

最后，周边电路芯片和三维阵列芯片含有不同的互连线材料。周边电路芯片的互连线可以使用高速互连线材料，如铜(Cu)或高k介质等，而三维阵列芯片只能采用高温互连线材料(如钨或氧化硅)等。高速互连线材料比高温互连线材料速度高，这能提高3D-OTP的整体性能。Finally, peripheral circuit chips and 3D array chips contain different interconnect materials. The interconnection of peripheral circuit chips can use high-speed interconnection materials, such as copper (Cu) or high-k dielectric, while the three-dimensional array chip can only use high-temperature interconnection materials (such as tungsten or silicon oxide). High-speed interconnect materials have higher speeds than high-temperature interconnect materials, which can improve the overall performance of 3D-OTP.

附图说明Description of drawings

图1A是一种现有技术中3D-OTP的截面图；图1B是一种集成3D-OTP芯片(现有技术)的电路框图；图1C是一种未编程3D-OTP存储元的截面图；图1D是一种已编程3D-OTP存储元的截面图。Fig. 1A is a sectional view of 3D-OTP in a kind of prior art; Fig. 1B is a kind of circuit block diagram of integrated 3D-OTP chip (prior art); Fig. 1C is a kind of sectional view of unprogrammed 3D-OTP storage element ; Figure 1D is a cross-sectional view of a programmed 3D-OTP memory cell.

图2A-图2D是四种分离3D-OTP的电路框图。2A-2D are circuit block diagrams of four separate 3D-OTPs.

图3A-图3B是两种分离3D-OTP中三维阵列芯片的截面图。3A-3B are cross-sectional views of three-dimensional array chips in two separate 3D-OTPs.

图4A-图4B是两种分离3D-OTP中周边电路芯片的截面图。4A-4B are cross-sectional views of peripheral circuit chips in two separate 3D-OTPs.

图5A-图5B是第一种分离3D-OTP的分配模式。Fig. 5A-Fig. 5B are the distribution modes of the first split 3D-OTP.

图6A-图6B是第二种分离3D-OTP的分配模式。Fig. 6A-Fig. 6B are the distribution modes of the second split 3D-OTP.

图7A-图7C是第三种分离3D-OTP的分配模式。Fig. 7A-Fig. 7C are the distribution mode of the third split 3D-OTP.

图8A-图8B是第四种分离3D-OTP的分配模式。Fig. 8A-Fig. 8B are the distribution mode of the fourth split 3D-OTP.

图9A-图9B是两种支持多三维阵列芯片的周边电路芯片之电路框图。9A-9B are circuit block diagrams of two peripheral circuit chips supporting multiple three-dimensional array chips.

图10A－图10C是三种分离3D-OTP封装(或模块)的截面图。10A-10C are cross-sectional views of three separate 3D-OTP packages (or modules).

图11A-图11C是三种电压产生器的电路框图。11A-11C are circuit block diagrams of three voltage generators.

图12A是一种地址转换器的电路框图；图12B是一种数据转换器的电路框图。Fig. 12A is a circuit block diagram of an address converter; Fig. 12B is a circuit block diagram of a data converter.

注意到，这些附图仅是概要图，它们不按比例绘图。为了显眼和方便起见，图中的部分尺寸和结构可能做了放大或缩小。在不同实施例中，相同的符号一般表示对应或类似的结构。Note that these drawings are schematic diagrams only and they are not drawn to scale. For the sake of conspicuousness and convenience, some sizes and structures in the drawings may be enlarged or reduced. In different embodiments, like symbols generally indicate corresponding or similar structures.

具体实施方式detailed description

在本发明中，“/”表示“和”或“或”的关系。例如，读/写电压表示读电压、或写电压、或读电压和写电压；地址/数据表示地址、或数据、或地址和电压。In the present invention, "/" represents the relationship of "and" or "or". For example, read/write voltage means read voltage, or write voltage, or read voltage and write voltage; address/data means address, or data, or address and voltage.

图1C和图1D分别表示两种3D-OTP存储元1aa、1ab。其中，存储元1aa未编程，而存储元1ab已编程。存储元1aa和1ab均含有上电极1a(即第一地址线层)、二极管膜1*、反熔丝膜1**和下电极(即第二地址线层)。二极管膜1*的功能与二极管(也被称为转向元件或选择元件)类似。反熔丝膜1**在编程前具有大电阻。在一个实施例中，反熔丝膜1**含有一层氧化硅薄膜。在经过一个编程电压和编程电流后，反熔丝膜1**被击穿，存储 元1ab具有低电阻。FIG. 1C and FIG. 1D show two kinds of 3D-OTP storage cells 1aa and 1ab respectively. Among them, the memory cell 1aa is not programmed, and the memory cell 1ab is programmed. Both memory cells 1aa and 1ab contain an upper electrode 1a (ie, a first address line layer), a diode film 1*, an antifuse film 1**, and a lower electrode (ie, a second address line layer). The function of the diode film 1* is similar to that of a diode (also called steering element or selection element). Antifuse 1** has high resistance before programming. In one embodiment, the antifuse film 1** contains a silicon oxide film. After a programming voltage and a programming current, the antifuse film 1** is broken down, and the memory cell 1ab has low resistance.

图2A-图2D是四种分离3D-OTP的电路框图。分离3D-OTP 50包括一能与各种主机实现物理连接、并按照一种通讯标准通讯的接口54。接口54包括多个接触端52a、52b、54a－54d，它们能与主机插口对应的接触端耦合。例如，主机分别通过电源端52a和接地端52b为分离3D-OTP 50提供电源电压V_DD和接地电压V_SS；主机通过信号端54a－54d与分离3D-OTP50交换地址/数据。由于这些地址/数据直接被主机使用，它们是逻辑地址/数据。2A-2D are circuit block diagrams of four separate 3D-OTPs. The separate 3D-OTP 50 includes an interface 54 capable of physically connecting with various hosts and communicating according to a communication standard. The interface 54 includes a plurality of contacts 52a, 52b, 54a-54d, which can be coupled with corresponding contacts of the host socket. For example, the host provides the power supply voltage V _DD and the ground voltage V _SS to the separate 3D-OTP 50 through the power terminal 52a and the ground terminal 52b respectively; the host exchanges address/data with the separate 3D-OTP 50 through the signal terminals 54a-54d. Since these addresses/data are directly used by the host, they are logical addresses/data.

分离3D-OTP 50含有一三维阵列芯片30和至少一周边电路芯片40/40*。3D-OTP的至少一芯片外周边电路组件位于周边电路芯片40/40*，而非位于三维阵列芯片30。芯片外周边电路组件是3D-OTP的必须组件，它可以为3D-OTP实现电压、数据和/或地址转换。如果三维阵列芯片没有该芯片外周边电路组件，则它不能独立完成基本存储功能。The separate 3D-OTP 50 includes a three-dimensional array chip 30 and at least one peripheral circuit chip 40/40*. At least one peripheral circuit component of the 3D-OTP is located on the peripheral circuit chip 40 / 40 * instead of the three-dimensional array chip 30 . The peripheral circuit components outside the chip are necessary components for 3D-OTP, which can realize voltage, data and/or address conversion for 3D-OTP. If the three-dimensional array chip does not have the peripheral circuit components outside the chip, it cannot independently complete the basic storage function.

图2A中的分离3D-OTP 50是一3D-OTP存储卡，其周边电路芯片40含有一读/写电压产生器。读/写电压产生器从主机处获取电源电压V_DD，将其转换成读/写电压，并通过电源总线56向三维阵列芯片30提供该读/写电压。这里，读/写电压可以是仅为读电压V_R、或仅为写电压V_W、或同时为读电压V_R和写电压V_W，它与电源电压V_DD具有不同的数值。在本实施例种，读/写电压包括一个读电压V_R和两个写电压V_W1、V_W2。在别的实施例中，读/写电压可以包括不止一个读电压或两个写电压。The separate 3D-OTP 50 in FIG. 2A is a 3D-OTP memory card, and its peripheral circuit chip 40 includes a read/write voltage generator. The read/write voltage generator obtains the power supply voltage V _DD from the host, converts it into a read/write voltage, and provides the read/write voltage to the three-dimensional array chip 30 through the power bus 56 . Here, the read/write voltage can be only the read voltage _{VR, or only the write voltage VW ,} or both the read voltage _{VR and the write voltage VW ,} which have different values from the power supply voltage _VDD . In this embodiment, the read/write voltages include one read voltage _VR and two write voltages V _W1 , V _W2 . In other embodiments, the read/write voltages may include more than one read voltage or two write voltages.

图2B中的分离3D-OTP 50是一3D-OTP存储卡，其周边电路芯片40含有一地址/数据转换。地址/数据转换器将外部总线57(包括来自接触端54a－54d上的信号)上的逻辑地址与内部总线58上的物理地址相互转换；也可以将外部总线57上的逻辑数据与内部总线58上的物理数据相互转换。这里，地址/数据转换器40*可以仅实现地址转换、或仅实现数据转换、或同时实现地址和数据转换。The separate 3D-OTP 50 in FIG. 2B is a 3D-OTP memory card, and its peripheral circuit chip 40 contains an address/data conversion. The address/data converter converts the logical address on the external bus 57 (comprising signals from the contact terminals 54a-54d) and the physical address on the internal bus 58; Physical data on the mutual conversion. Here, the address/data converter 40* can implement only address conversion, or only data conversion, or both address and data conversion.

图2C中的分离3D-OTP 50仍是一3D-OTP存储卡，它含有两个周边电路芯片40和40*。其中，周边电路芯片40含有一芯片外读/写电压产生器、周边电路芯片40*则含有一芯片外地址/数据转换器。The split 3D-OTP 50 in FIG. 2C is still a 3D-OTP memory card, which contains two peripheral circuit chips 40 and 40*. Wherein, the peripheral circuit chip 40 includes an off-chip read/write voltage generator, and the peripheral circuit chip 40* includes an off-chip address/data converter.

图2D中的分离3D-OTP 50是一大容量3D-OTP存储卡或一3D-OTP固态硬盘。它含有两个周边电路芯片40和40*、以及多个三维阵列芯片30a、30b...30w。其中，周边电路芯片40含有一芯片外读/写电压产生器、周边电路芯片40*则含有一芯片外地址/数据转换器。这些三维阵列芯片组成两个通道：A和B。通道A中，来自周边电路芯片40*的内部总线58A为三维阵列芯片30a、30b…30i提供物理地址/数据，通道B中，来自周边电路芯片40*的内部总线58B为三维阵列芯片30r、30s…30w提供物理地址/数据。同时，来自周边 电路芯片40的电源总线56为维阵列芯片30a、30b…30w提供读/写电压。虽然本实施例仅有两个通道，对于熟悉本专业的人士来说，大容量3D-OTP存储卡和3D-OTP固态硬盘可以含有更多通道。The separated 3D-OTP 50 in FIG. 2D is a large-capacity 3D-OTP memory card or a 3D-OTP solid state drive. It contains two peripheral circuit chips 40 and 40*, and a plurality of three-dimensional array chips 30a, 30b...30w. Wherein, the peripheral circuit chip 40 includes an off-chip read/write voltage generator, and the peripheral circuit chip 40* includes an off-chip address/data converter. These three-dimensional array chips are organized into two channels: A and B. In channel A, the internal bus 58A from the peripheral circuit chip 40* provides physical addresses/data for the three-dimensional array chips 30a, 30b...30i, and in channel B, the internal bus 58B from the peripheral circuit chip 40* provides the three-dimensional array chips 30r, 30s ...30w provides physical address/data. At the same time, the power bus 56 from the peripheral circuit chip 40 provides read/write voltage for the dimensional array chips 30a, 30b...30w. Although there are only two channels in this embodiment, for those familiar with this profession, a large-capacity 3D-OTP memory card and a 3D-OTP solid-state hard disk may contain more channels.

图3A表示一种分离3D-OTP中的三维阵列芯片30。该三维阵列芯片30含有至少一3D-OTP阵列36和芯片内周边电路组件38。3D-OTP阵列36形成在三维空间中，并含有多个存储层16A-16D。每个存储层(如16A)含有多个介于上地址线(如2a)和下地址线(如1a)之间的3D-OTP存储元(如1aa)。在本说明书中，处于同一层次的地址线组成一个地址线层。注意到，本实施例是一种层间隔离的3D-OTP，即相邻存储层由绝缘介质隔离开。相应地，在三维阵列芯片30中，地址线层数为8，即1a-8a(地址线层3a-6a未画出)；存储层数为4，即16A-16D(存储层16B、16C未画出)。FIG. 3A shows a three-dimensional array chip 30 in a split 3D-OTP. The three-dimensional array chip 30 includes at least one 3D-OTP array 36 and on-chip peripheral circuit components 38. The 3D-OTP array 36 is formed in a three-dimensional space and includes a plurality of storage layers 16A-16D. Each storage layer (such as 16A) contains a plurality of 3D-OTP storage elements (such as 1aa) between the upper address line (such as 2a) and the lower address line (such as 1a). In this specification, address lines at the same layer constitute one address line layer. Note that this embodiment is a 3D-OTP with interlayer isolation, that is, adjacent storage layers are separated by an insulating medium. Correspondingly, in the three-dimensional array chip 30, the number of address line layers is 8, that is, 1a-8a (the address line layers 3a-6a are not shown); the number of storage layers is 4, that is, 16A-16D (the storage layers 16B, 16C are not shown). draw).

芯片内周边电路38含有晶体管0t及其互连线0iA。三维阵列芯片30的互连线不包含任何存储结构，其互连线层数是阵列下周边电路和阵列外周边电路中互连线层数较大的那个。在此实施例中，三维阵列芯片30的互连线层数为2，即互连线层0M1、0M2。The on-chip peripheral circuit 38 contains a transistor 0t and its interconnection 0iA. The interconnection lines of the three-dimensional array chip 30 do not contain any storage structure, and the number of interconnection line layers is the one with the larger number of interconnection line layers in the lower peripheral circuit of the array and the outer peripheral circuit of the array. In this embodiment, the number of interconnect layers of the three-dimensional array chip 30 is two, that is, the interconnect layers 0M1 and 0M2.

由于3D-OTP阵列36形成在芯片内周边电路38上方，该三维阵列芯片30的后端薄膜层数为地址线层数和互连线层数之和。在该实施例中，三维阵列芯片30的后端薄膜层数为10，包括8个地址线层和2个互连线层。Since the 3D-OTP array 36 is formed above the peripheral circuit 38 in the chip, the number of film layers at the back end of the three-dimensional array chip 30 is the sum of the number of address line layers and the number of interconnection line layers. In this embodiment, the number of film layers at the back end of the three-dimensional array chip 30 is 10, including 8 address line layers and 2 interconnection line layers.

图3B表示另一种分离3D-OTP 50中的三维阵列芯片30。它是一种层间交错的3D-OTP，即相邻存储层共享地址线层。如存储层16A*和存储层从16B*共享地址线层2a。相应地，总地址线层数只比总存储层数多1。在该实施例中，地址线层数为9，即1a-9a(地址线层3a-8a未画出)；存储层数为8，即16A*-16H*(存储层16C*-16G*未画出)。总的说来，三维阵列芯片30的后端薄膜层数为11，包括9个地址线层和2个互连线层。FIG. 3B shows another three-dimensional array chip 30 in a separate 3D-OTP 50 . It is a 3D-OTP interleaved between layers, that is, adjacent storage layers share address line layers. For example, the storage layer 16A* and the storage layer 16B* share the address line layer 2a. Correspondingly, the total number of address line layers is only 1 more than the total number of storage layers. In this embodiment, the number of address line layers is 9, that is, 1a-9a (the address line layers 3a-8a are not shown); the number of storage layers is 8, that is, 16A*-16H* (storage layers 16C*-16G* are not shown). draw). In general, the back-end film layers of the three-dimensional array chip 30 are 11, including 9 address line layers and 2 interconnection line layers.

虽然图3A-图3B中的截面图类似图1A，但是图1A中的周边电路包括所有周边电路组件，而图3A-图3B中的周边电路不含一些3D-OTP必须的周边电路组件，如读/写电压发生器或地址/数据转换器。其细节将在图5A-图8B中披露。Although the cross-sectional view in Figure 3A-Figure 3B is similar to Figure 1A, the peripheral circuit in Figure 1A includes all peripheral circuit components, while the peripheral circuit in Figure 3A-Figure 3B does not contain some peripheral circuit components necessary for 3D-OTP, such as read/write voltage generator or address/data converter. Its details will be disclosed in Figures 5A-8B.

图4A-图4B表示两种分离3D-OTP 50中的周边电路芯片40(或40*)。周边电路芯片40形成在二维平面上，它只含一个功能层，即衬底电路0K’。衬底电路0K’含有晶体管0t’及其互连线0t’。由于周边电路芯片40不含任何存储结构，其后端薄膜层数为其互连线层数。在图4A的实施例中，后端薄膜层数为2，即互连线0M1’-0M2’；在图4B的实施例中，后端薄膜层数为4，即互连线0M1’-0M4’。4A-4B show peripheral circuit chips 40 (or 40*) in two separate 3D-OTPs 50 . The peripheral circuit chip 40 is formed on a two-dimensional plane and includes only one functional layer, that is, the substrate circuit OK'. The substrate circuit OK' contains a transistor 0t' and its interconnection 0t'. Since the peripheral circuit chip 40 does not contain any memory structure, the number of film layers at the back end is the number of interconnection wire layers. In the embodiment of FIG. 4A, the number of back-end film layers is 2, that is, interconnection lines 0M1'-0M2'; in the embodiment of FIG. 4B, the number of back-end film layers is 4, that is, interconnection lines 0M1'-0M4 '.

在图3A-图4B的实施例中，周边电路芯片40的后端薄膜层的数目(2或4)要比三 维阵列芯片40(10或11)少很多。一个更严格的要求是三维阵列芯片40的后端薄膜层数是周边电路芯片30互连线层数的至少两倍。由于晶圆成本基本和后端薄膜层的数目成正比，周边电路芯片40的晶圆成本将远低于三维阵列芯片30。因此，分离3D-OTP的整体成本将低于集成3D-OTP。In the embodiment shown in FIG. 3A-FIG. 4B, the number of back-end film layers of the peripheral circuit chip 40 (2 or 4) is much less than that of the three-dimensional array chip 40 (10 or 11). A more stringent requirement is that the number of film layers at the back end of the three-dimensional array chip 40 is at least twice the number of interconnection layers of the peripheral circuit chip 30 . Since the wafer cost is basically proportional to the number of back-end film layers, the wafer cost of the peripheral circuit chip 40 will be much lower than that of the three-dimensional array chip 30 . Therefore, the overall cost of separating 3D-OTP will be lower than integrating 3D-OTP.

此外，在图4B中，周边电路芯片40的互连线层数(4)比三维阵列芯片30的互连线层数(2)更多，芯片外周边电路的设计更加简单、性能更为优异、芯片面积也更小。因此，分离3D-OTP的整体性能和整体面积优于集成3D-OTP。注意到，周边电路芯片40的互连线层数(4)仍远小于三维阵列芯片30的后端薄膜层数(10或11)。In addition, in FIG. 4B, the number of interconnection layers (4) of the peripheral circuit chip 40 is more than the number of interconnection layers (2) of the three-dimensional array chip 30, and the design of the peripheral circuit outside the chip is simpler and the performance is more excellent. , The chip area is also smaller. Therefore, the overall performance and overall area of the separated 3D-OTP is better than that of the integrated 3D-OTP. Note that the number of interconnection layers (4) of the peripheral circuit chip 40 is still much smaller than the number of back-end film layers (10 or 11) of the three-dimensional array chip 30 .

另外，由于周边电路芯片40的互连线不需要经受高温工艺步骤，它可以使用高速互连线材料，如铜(Cu)或高k介质等；而三维阵列芯片40中的互连线需要经受高温工艺步骤，它只能采用高温互连线材料(如钨或氧化硅)等。高速互连线材料能提高周边电路40乃至3D-OTP的整体性能。In addition, since the interconnection lines of the peripheral circuit chip 40 do not need to stand high-temperature process steps, it can use high-speed interconnection line materials, such as copper (Cu) or high-k dielectrics, etc.; and the interconnection lines in the three-dimensional array chip 40 need to withstand High-temperature process steps, it can only use high-temperature interconnect materials (such as tungsten or silicon oxide) and the like. The high-speed interconnect material can improve the overall performance of the peripheral circuit 40 and even the 3D-OTP.

对于传统的二维存储器(指存储元分布在二维平面上，如传统的闪存)来说，其存储阵列和周边电路具有类似的后端结构。虽然把它们分离到不同芯片上在技术上是可行的，但是由于存储阵列和周边电路的晶圆成本接近，分离后并不能在芯片成本上有所降低，加上多余的封装成本，将二维存储的存储阵列和周边电路分离会增加成本，这和三维存储器有很大差别。For a traditional two-dimensional memory (meaning that storage elements are distributed on a two-dimensional plane, such as a traditional flash memory), its storage array and peripheral circuits have a similar back-end structure. Although it is technically feasible to separate them into different chips, since the wafer cost of the memory array and peripheral circuits is close, the cost of the chip cannot be reduced after separation. The separation of the memory array and the peripheral circuit of the storage will increase the cost, which is very different from the three-dimensional memory.

与集成3D-OTP 20不同，在分离3D-OTP 50中，至少一周边电路组件位于周边电路芯片40，而不位于三维阵列芯片30。换句话说，周边电路组件在三维阵列芯片30和周边电路芯片40之间进行了分配。图5A-图9B披露了几种分配模式。Different from the integrated 3D-OTP 20 , in the separated 3D-OTP 50 , at least one peripheral circuit component is located on the peripheral circuit chip 40 instead of the three-dimensional array chip 30 . In other words, peripheral circuit components are allocated between the three-dimensional array chip 30 and the peripheral circuit chip 40 . Figures 5A-9B disclose several allocation modes.

图5A-图5B是第一种分离3D-OTP 50的分配模式。三维阵列芯片30含有多个3D-OTP阵列22aa、2ay及其解码器，以及一芯片内读/写电压产生器41(图5A)。周边电路芯片40至少含有一芯片外地址/数据转换器49(图5B)。由于三维阵列芯片40不含有该转换器49，三维阵列芯片40不能独立完成基本存储功能，但具有较高的阵列效率。另外一种模式是，三维阵列芯片40含有芯片外地址/数据转换器，但不含有读/写电，但具有较大的阵列效率压产生器。周边电路芯片40含有读/写电压产生器。类似地，三维阵列芯片40不能独立完成基本存储功能，但具有较高的阵列效率。5A-5B are the distribution modes of the first split 3D-OTP 50 . The three-dimensional array chip 30 includes a plurality of 3D-OTP arrays 22aa, 2ay and their decoders, and an on-chip read/write voltage generator 41 (FIG. 5A). The peripheral circuit chip 40 includes at least one off-chip address/data converter 49 (FIG. 5B). Since the three-dimensional array chip 40 does not contain the converter 49, the three-dimensional array chip 40 cannot independently perform basic storage functions, but has relatively high array efficiency. Another mode is that the three-dimensional array chip 40 contains off-chip address/data converters, but does not contain read/write power, but has a larger array efficiency voltage generator. The peripheral circuit chip 40 contains a read/write voltage generator. Similarly, the three-dimensional array chip 40 cannot independently perform basic storage functions, but has relatively high array efficiency.

图6A-图6B是第二种分离3D-OTP 50的分配模式。它含有三维阵列芯片30和周边电路芯片40。三维阵列芯片30含有多个3D-OTP阵列22aa、2ay及其解码器(图6A)。周边电路芯片40至少含有一读/写电压产生器41和一地址/数据转换器49(图6B)。由于三维 阵列芯片40不含有读/写电压产生器41和地址/数据转换器49，三维阵列芯片40不能独立完成基本存储功能，但具有更高的阵列效率。6A-6B are the second split 3D-OTP 50 distribution modes. It contains a three-dimensional array chip 30 and a peripheral circuit chip 40 . The three-dimensional array chip 30 contains multiple 3D-OTP arrays 22aa, 2ay and their decoders (FIG. 6A). The peripheral circuit chip 40 at least includes a read/write voltage generator 41 and an address/data converter 49 (FIG. 6B). Since the three-dimensional array chip 40 does not contain the read/write voltage generator 41 and the address/data converter 49, the three-dimensional array chip 40 cannot independently perform basic storage functions, but has higher array efficiency.

图7A-图7C是第三种分离3D-OTP 50的分配模式。它含有三维阵列芯片30和两个周边电路芯片40、40*。三维阵列芯片30含有多个3D-OTP阵列22aa、2ay及其解码器(图7A)。第一周边电路芯片40至少含有一读/写电压产生器41(图7B)。第二周边电路芯片40*至少含有一地址/数据转换器49(图7C)。类似地，由于三维阵列芯片40不含有读/写电压产生器41和地址/数据转换器49，三维阵列芯片40不能独立完成基本存储功能，但具有更高的阵列效率。同时，第一周边电路芯片40可按照模拟电路优化，而第二周边电路芯片40*可按照数码电路优化。7A-7C are the distribution modes of the third split 3D-OTP 50 . It contains a three-dimensional array chip 30 and two peripheral circuit chips 40, 40*. The three-dimensional array chip 30 contains multiple 3D-OTP arrays 22aa, 2ay and their decoders (FIG. 7A). The first peripheral circuit chip 40 at least includes a read/write voltage generator 41 (FIG. 7B). The second peripheral circuit chip 40* includes at least one address/data converter 49 (FIG. 7C). Similarly, since the three-dimensional array chip 40 does not contain the read/write voltage generator 41 and the address/data converter 49, the three-dimensional array chip 40 cannot independently perform basic storage functions, but has higher array efficiency. Meanwhile, the first peripheral circuit chip 40 can be optimized according to an analog circuit, and the second peripheral circuit chip 40* can be optimized according to a digital circuit.

图8A-图8B是第四种分离3D-OTP的分配模式。它类似图6A-图6B的实施例。唯一的差别是三维阵列芯片30还含有一个串行-并行转换器(SerDes)(图8A)，它将芯片30内部的并行数码信号(如地址/数据/指令等)转换成芯片30外的串行数码信号；同时，周边电路芯片40也含有一串行-并行转换器(图8B)，它将芯片40内部的并行数码信号(如地址/数据/指令等)转换成芯片40外的串行数码信号。通过这种转换，封装时需要增加的引线数目会降低很多，这能降低封装成本。Fig. 8A-Fig. 8B are the distribution mode of the fourth split 3D-OTP. It is similar to the embodiment of Figures 6A-6B. The only difference is that the three-dimensional array chip 30 also contains a serial-parallel converter (SerDes) (FIG. 8A), which converts the parallel digital signals (such as address/data/command, etc.) inside the chip 30 into serial signals outside the chip 30. line digital signal; at the same time, the peripheral circuit chip 40 also contains a serial-parallel converter (Fig. 8B), which converts the parallel digital signal (such as address/data/command, etc.) digital signal. Through this conversion, the number of leads that need to be increased during packaging will be greatly reduced, which can reduce packaging costs.

图9A-图9B是两种支持多三维阵列芯片的周边电路芯片40之电路框图。图9A的周边电路芯片40含有多个地址/数据转换器49a、49b…49w(或读/写电压产生器)。每个地址/数据转换器(如49a)为相应的三维阵列芯片(如30a)转换地址/数据。图9B的周边电路芯片40还含有多个读/写电压产生器41a、41b…41w。每个读/写电压产生器(如41a)为相应的三维阵列芯片(如30a)提供读/写电压。9A-9B are circuit block diagrams of two peripheral circuit chips 40 supporting multiple three-dimensional array chips. The peripheral circuit chip 40 of FIG. 9A includes a plurality of address/data converters 49a, 49b...49w (or read/write voltage generators). Each address/data converter (such as 49a) converts address/data for the corresponding three-dimensional array chip (such as 30a). The peripheral circuit chip 40 in FIG. 9B also includes a plurality of read/write voltage generators 41a, 41b...41w. Each read/write voltage generator (such as 41a) provides a read/write voltage for the corresponding three-dimensional array chip (such as 30a).

图10A－图10C是三种分离3D-OTP封装(或模块)60的截面图。图10A－图10B中的分离3D-OTP 60是一种多芯片封装(MCP)。其中，图10A中的3D-OTP多芯片封装60含有两个单独的芯片：一三维阵列芯片30和一周边电路芯片40。其中，芯片30堆叠在芯片40上方，并位于同一封装壳61中。引线(bond wire)65为芯片30和40提供电连接。除了引线，还可以采用焊球(solder bump)等。为了保证数据安全，芯片30和40最好封装在一模塑料(moldingcompound)57内。10A-10C are cross-sectional views of three separate 3D-OTP packages (or modules) 60 . The split 3D-OTP 60 in FIGS. 10A-10B is a multi-chip package (MCP). Wherein, the 3D-OTP multi-chip package 60 in FIG. 10A contains two separate chips: a three-dimensional array chip 30 and a peripheral circuit chip 40 . Wherein, the chip 30 is stacked above the chip 40 and located in the same package 61 . Bond wires 65 provide electrical connections for chips 30 and 40 . Instead of wires, solder bumps or the like may be used. To ensure data security, the chips 30 and 40 are preferably packaged in a molding compound 57 .

图10B中的3D-OTP多芯片封装60含有三个单独的芯片：两个三维阵列芯片30a、30b和周边电路芯片40。在本实施例中，芯片30a、30b堆叠在芯片40之上。在其它实施例中，芯片40可以堆叠在芯片30a、30b上，或芯片40与芯片30a、30b面对面地堆叠在一起，或芯片40和芯片30a、30b并列放置。The 3D-OTP multi-chip package 60 in FIG. 10B contains three separate chips: two three-dimensional array chips 30 a , 30 b and a peripheral circuit chip 40 . In this embodiment, chips 30 a , 30 b are stacked on top of chip 40 . In other embodiments, the chips 40 may be stacked on the chips 30a, 30b, or the chips 40 and the chips 30a, 30b are stacked face to face, or the chips 40 and the chips 30a, 30b are placed side by side.

图10C中的分离3D-OTP是一3D-OTP多芯片模块(MCM)60，它含有一个框架76。该框架76含有两个单独的封装：三维阵列封装72和周边电路封装74。其中，三维阵列封装72含有两个三维阵列芯片30a、30b，而周边电路封装64含有周边电路芯片40。框架76还为三维阵列封装72和周边电路封装74提供电连接(未画出)。The split 3D-OTP in FIG. 10C is a 3D-OTP multi-chip module (MCM) 60 that includes a frame 76 . The frame 76 contains two separate packages: a three-dimensional array package 72 and a peripheral circuit package 74 . Among them, the three-dimensional array package 72 contains two three-dimensional array chips 30 a, 30 b, and the peripheral circuit package 64 contains the peripheral circuit chip 40 . Frame 76 also provides electrical connections (not shown) for 3D array package 72 and peripheral circuit package 74 .

图11A－图11C是三种读/写电压产生器41的电路图。读/写电压产生器41最好使用直流－直流变换器(DC-DC converter)。直流－直流变换器包括升压器和降压器。升压器的输出电压比输入电压高，降压器的输入电压比输入电压低。升压器的例子包括电荷泵(charge pump，图11A)和Boost变换器(Boost converter，图11B)等。降压器的例子包括低压降稳压器(low dropout，图11C)和Buck变换器(Buck converter)等。11A-11C are circuit diagrams of three read/write voltage generators 41 . The read/write voltage generator 41 preferably uses a DC-DC converter (DC-DC converter). A DC-DC converter consists of a booster and a buck. The output voltage of the booster is higher than the input voltage, and the input voltage of the buck is lower than the input voltage. Examples of the booster include a charge pump (charge pump, FIG. 11A ) and a Boost converter (Boost converter, FIG. 11B ). Examples of bucks include low dropout regulators (low dropout, Figure 11C) and Buck converters (Buck converter).

图11A中的读/写电压产生器41包括一电荷泵71，其输出电压V_out大于输入电压V_in。一般说来，电荷泵71还含有一个或多个电容。图11B中的读/写电压产生器41包括一高频Boost变换器73，其输出电压V_out大于输入电压V_in。Boost变换器73还含有电感。该电感最好是一薄电感，以满足存储卡或固态硬盘对厚度的要求。图11C中的读/写电压产生器41包括一低压降稳压器75，其输出电压V_out小于输入电压V_in。一般说来，低压降稳压器75还含有一个或多个电容。The read/write voltage generator 41 in FIG. 11A includes a charge pump 71 whose output voltage V _out is greater than the input voltage V _in . Generally speaking, the charge pump 71 also includes one or more capacitors. The read/write voltage generator 41 in FIG. 11B includes a high frequency boost converter 73 whose output voltage V _out is greater than the input voltage V _in . Boost converter 73 also includes an inductor. The inductor is preferably a thin inductor to meet the thickness requirements of memory cards or solid state disks. The read/write voltage generator 41 in FIG. 11C includes a low dropout regulator 75 whose output voltage V _out is smaller than the input voltage V _in . Typically, low dropout regulator 75 also includes one or more capacitors.

图12A－图12B分别表示地址/数据转换器49的两个组件：地址转换器43和数据转换器45。图12A表示一种地址转换器43。它将来自主机的逻辑地址57A转换成三维阵列芯片30的物理地址58A。地址转换器43含有一个处理器92和一存储器94。存储器94存储一地址映射表82和一故障块表84。这些状态表82、84平时存储在只读存储器(ROM)中。在使用时被加载到随机存取存储器(RAM)中。这里，只读存储器可以一种非易失性存储器(NVM)，如快闪存储器。对于一个支持多三维阵列芯片(如图2D中的30a、30b…30w)的地址/数据转换器49来说，存储器94为所有三维阵列芯片30a、30b…30w存储状态表82、84、86，它被所有三维阵列芯片30a、30b…30w共享。12A-12B show two components of the address/data converter 49: the address converter 43 and the data converter 45, respectively. FIG. 12A shows an address converter 43. As shown in FIG. It converts the logical address 57A from the host into the physical address 58A of the three-dimensional array chip 30 . Address translator 43 includes a processor 92 and a memory 94 . The memory 94 stores an address mapping table 82 and a faulty block table 84 . These state tables 82, 84 are usually stored in a read-only memory (ROM). Loaded into random access memory (RAM) when in use. Here, the read-only memory may be a non-volatile memory (NVM), such as a flash memory. For an address/data converter 49 that supports multiple three-dimensional array chips (such as 30a, 30b...30w in Figure 2D), the memory 94 stores state tables 82, 84, 86 for all three-dimensional array chips 30a, 30b...30w, It is shared by all three-dimensional array chips 30a, 30b...30w.

在存储器94的各种状态表82、84中，地址映射表82存储逻辑地址和物理地址之间的映射；故障块表84存储三维存储阵列中有故障的存储块之地址。这里，“存储块”是指存储器的分配单元，其大小可以从一个存储元到一个三维存储阵列中的所有存储元。Among the various state tables 82, 84 of the memory 94, the address mapping table 82 stores the mapping between logical addresses and physical addresses; the fault block table 84 stores the addresses of faulty memory blocks in the three-dimensional memory array. Here, "storage block" refers to an allocation unit of memory, and its size can range from one storage element to all storage elements in a three-dimensional memory array.

在读过程中，一旦处理器92接收到需要读出的存储块之逻辑地址57A，它从地址映射表82中获取相应的物理地址58A。在写过程中，一旦处理器92接收到需要写入的存储块之逻辑地址57A，它从地址映射表82和故障块表84中选择一未占用、无故障以及较少使用的存储块来写入数据。该被选存储块的地址即为物理地址。During the read process, once the processor 92 receives the logical address 57A of the memory block to be read, it obtains the corresponding physical address 58A from the address mapping table 82 . In the write process, once the processor 92 receives the logical address 57A of the storage block that needs to be written, it selects an unoccupied, non-faulty and less used storage block from the address mapping table 82 and the fault block table 84 to write input data. The address of the selected memory block is the physical address.

图12B表示一种数据转换器45。它将来自主机的逻辑数据57D转换成三维阵列芯片30的物理数据58D，或者将三维阵列芯片30的物理数据58D转换成输出至主机的逻辑数据57D。数据转换器45含有一错误检验校正(ECC)编码器96和一ECC解码器98。ECC编码器96将输入的逻辑数据57D转换成要存储到三维存储阵列的物理数据58D。ECC解码器98将从三维存储阵列中读出的物理数据58D转换成要被输出的逻辑数据57D。在该过程中，物理数据58D中的错误位被检验和校正。适合3D-OTP的ECC编码算法包括Reed-Solomon码、Golay码、BCH码、多维奇偶码和汉明码等。FIG. 12B shows a data converter 45 . It converts logical data 57D from the host into physical data 58D of the three-dimensional array chip 30, or converts physical data 58D of the three-dimensional array chip 30 into logical data 57D output to the host. Data converter 45 includes an error checking correction (ECC) encoder 96 and an ECC decoder 98 . ECC encoder 96 converts incoming logical data 57D into physical data 58D to be stored in the three-dimensional memory array. The ECC decoder 98 converts the physical data 58D read out from the three-dimensional memory array into logical data 57D to be output. During this process, erroneous bits in the physical data 58D are checked and corrected. ECC coding algorithms suitable for 3D-OTP include Reed-Solomon codes, Golay codes, BCH codes, Dovec even codes, and Hamming codes.

应该了解，在不远离本发明的精神和范围的前提下，可以对本发明的形式和细节进行改动，这并不妨碍它们应用本发明的精神。因此，除了根据附加的权利要求书的精神，本发明不应受到任何限制。It should be understood that changes may be made in form and detail of the invention without departing from the spirit and scope of the invention, which does not prevent them from applying the spirit of the invention. The invention, therefore, should not be restricted except in accordance with the spirit of the appended claims.