CN107689787B - A high-voltage side gate driver circuit for a half-bridge structure - Google Patents
- ️Tue Aug 25 2020
CN107689787B - A high-voltage side gate driver circuit for a half-bridge structure - Google Patents
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- CN107689787B CN107689787B CN201710675218.0A CN201710675218A CN107689787B CN 107689787 B CN107689787 B CN 107689787B CN 201710675218 A CN201710675218 A CN 201710675218A CN 107689787 B CN107689787 B CN 107689787B Authority
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Abstract
一种用于半桥结构的高压侧栅驱动电路，其中的脉冲滤波电路包括两条信号通路，两条通路均设有缓冲电路、倒相器单元和整形电路，两个倒相器单元均有四个端口，两个倒相器单元的第一端口为输入端，两个倒相器单元的第二端口分别为输出端，两个倒相器单元的第三端口为固定电位端，两个倒相器单元的第四端口为浮动电位端；若第一端口和第四端口的电压差的绝对值高于倒相器单元阈值电压VTH，第四端口的电信号可以通过第一倒相器单元或第二倒相器单元传递至第二端口；若第一端口和第四端口的电压差绝对值不高于倒相器单元阈值电压VTH，则第四端口的电信号无法通过第一倒相器单元或第二倒相器单元传递至第二端口。
A high-voltage side gate drive circuit for a half-bridge structure, wherein the pulse filter circuit includes two signal paths, both paths are provided with a buffer circuit, an inverter unit and a shaping circuit, and the two inverter units have Four ports, the first port of the two inverter units is the input end, the second port of the two inverter units is the output end, the third port of the two inverter units is the fixed potential end, the two The fourth port of the inverter unit is a floating potential terminal; if the absolute value of the voltage difference between the first port and the fourth port is higher than the inverter unit threshold voltage VTH, the electrical signal of the fourth port can pass through the first inverter. The unit or the second inverter unit is transmitted to the second port; if the absolute value of the voltage difference between the first port and the fourth port is not higher than the inverter unit threshold voltage VTH, the electrical signal of the fourth port cannot pass through the first inverter. The inverter unit or the second inverter unit communicates to the second port.
Description
技术领域technical field
本发明涉及高压驱动技术，特别涉及一种具有高抗噪声能力，用于半桥结构的高压浮栅驱动电路，属于集成电路技术领域。The invention relates to a high-voltage driving technology, in particular to a high-voltage floating gate driving circuit with high anti-noise capability and used in a half-bridge structure, belonging to the technical field of integrated circuits.
背景技术Background technique
高压侧栅驱动电路是一种以低压信号控制高压功率开关器件开启与关断的集成电路，因其可以有效地控制桥式连接的功率开关器件，所以被广泛应用于电机驱动与谐振电源等领域。The high-voltage side gate drive circuit is an integrated circuit that controls the turn-on and turn-off of high-voltage power switching devices with low-voltage signals. Because it can effectively control bridge-connected power switching devices, it is widely used in motor drives and resonant power supplies. .
高压侧栅驱动电路常被用于驱动半桥结构中的高侧开关器件，而半桥结构中的低侧开关器件由低压侧栅驱动电路驱动。其基本拓扑结构如图1所示，MH、ML分别为半桥结构的高侧功率开关器件与低侧功率开关器件，半桥拓扑外接高压母线电压和HV，半桥驱动电路(100)包含高压侧栅驱动电路(101)和低压栅驱动电路(102)，高压侧栅驱动电路(101)的输出信号HO驱动高侧功率开关器件MH，低压侧栅驱动电路(102)的输出信号LO驱动低侧功率开关器件ML。为了提高电源的利用效率，半桥驱动电路(100)采用单电源供电模式，低压侧栅驱动电路(102)和高压侧栅驱动电路(101)中的低压区电路采用低侧固定电源VCC供电，VCC通过自举二极管DB和自举电容CB对高压侧栅驱动电路(101)中的高压区电路进行供电，高压侧栅驱动电路(101)中的高压区电路的电源电压VB和参考地VS为浮动电压，当高压侧栅驱动电路(101)的输出信号HO为高电平(VB)并且低压侧栅驱动电路(102)的输出LO为低电平(COM)时，高侧功率开关器件MH导通，低侧功率开关器件ML关断，VS电压升高，VB电压也随VS电压升高而升高；反之，当HO为低电平而LO为高电平时，MH截止，ML导通，VS和VB电压下降。在高压侧栅驱动电路(101)中，为了减小功耗并提高电路的可靠性，常采用双窄脉冲控制高压功率开关器件的方式以实现高压电平移位，即将高侧输入信号转换为两路窄脉冲，分别代表高侧输入信号的上升沿和下降沿，大大减小了高压功率开关器件的导通时间。The high-side gate driver circuit is often used to drive the high-side switching device in the half-bridge structure, while the low-side switching device in the half-bridge structure is driven by the low-side gate driver circuit. Its basic topology is shown in Figure 1, where MH and ML are the high-side power switching devices and the low-side power switching devices of the half-bridge structure, respectively. A high-side gate drive circuit (101) and a low-voltage gate drive circuit (102) are included, the output signal HO of the high-side gate drive circuit (101) drives the high-side power switching device MH , and the output signal of the low-side gate drive circuit (102) The LO drives the low-side power switching device ML . In order to improve the utilization efficiency of the power supply, the half-bridge driving circuit (100) adopts a single power supply mode, and the low-voltage area circuits in the low-voltage side gate driving circuit (102) and the high-voltage side gate driving circuit (101) are powered by a low-side fixed power supply VCC, VCC supplies power to the high voltage area circuit in the high voltage side gate driving circuit (101) through the bootstrap diode DB and the bootstrap capacitor C B , and the power supply voltage VB of the high voltage area circuit in the high voltage side gate drive circuit (101) and the reference ground VS is a floating voltage, when the output signal HO of the high-side gate driver circuit (101) is high level (VB) and the output LO of the low-side gate driver circuit (102) is low level (COM), the high-side power switch The device MH is turned on, the low-side power switching device ML is turned off, the VS voltage increases, and the VB voltage also increases with the increase of the VS voltage; conversely, when HO is low and LO is high, MH Cut off, ML is turned on, and the VS and VB voltages drop. In the high-voltage side gate drive circuit (101), in order to reduce power consumption and improve the reliability of the circuit, the high-voltage power switching device is often controlled by double narrow pulses to achieve high-voltage level shifting, that is, the high-side input signal is converted into The two narrow pulses represent the rising edge and falling edge of the high-side input signal respectively, which greatly reduces the on-time of the high-voltage power switching device.
如图2a所示，一种高压侧栅驱动电路(101)，包括窄脉冲产生电路(200)、高压电平移位电路(201)、脉冲滤波电路(202)、RS触发器(203)和栅驱动电路(204)。其中，窄脉冲产生电路(200)分别将高侧输入信号HIN的上升沿和下降沿转换为两路窄脉冲信号SET和RESET，SET和RESET分别控制高压电平移位电路(201)中的高压功率开关器件LDM1和LDM2，高压电平移位电路(201)的两路输出信号与脉冲滤波电路(202)的两个输入信号相连接，脉冲滤波电路(202)的两个输出信号分别作为RS触发器(203)的置位输入端
如图2b，由于高压栅驱动电路(101)采用浮动电源供电，VS电压的变化产生dV/dt应力，并通过自举电容(CB)耦合到浮动电源VB端，在高压侧栅驱动电路(101)中产生内部噪声，可能会造成HO状态变化，并引起MH的误关断或误开启。VS电压上升期间，即正dV/dt应力产生的内部噪声通常会比较容易造成MH的误关断或误开启。As shown in Fig. 2b, since the high-voltage gate drive circuit (101) is powered by a floating power supply, the change of VS voltage generates dV/dt stress, which is coupled to the floating power supply VB terminal through the bootstrap capacitor ( CB ), and the high-voltage side gate drive circuit ( 101), internal noise is generated, which may cause the HO state to change and cause the MH to turn off or turn on incorrectly. During the rising period of the VS voltage, that is, the internal noise generated by the positive dV /dt stress is usually more likely to cause the false turn-off or false turn-on of the MH.
传统解决dV/dt噪声问题的方法是采用RC滤波形式，如图3所示，脉冲滤波电路(202a)由倒相器、电阻和电容组成，其作用是将低于一定脉冲宽度的输入信号(VDS、VDR)滤除，尤其是dV/dt噪声产生的共模噪声信号。这种电路虽然可以一定程度上减小dV/dt噪声的影响，但是存在着抗dV/dt能力、抗VS负偏压能力和通道传输延时互相制约的矛盾。The traditional method to solve the dV/dt noise problem is to use RC filtering. As shown in Figure 3, the pulse filtering circuit (202a) is composed of an inverter, a resistor and a capacitor, and its function is to filter the input signal ( VDS, VDR) filter, especially the common mode noise signal generated by dV/dt noise. Although this kind of circuit can reduce the influence of dV/dt noise to a certain extent, there is a contradiction that the anti-dV/dt ability, the anti-VS negative bias ability and the channel transmission delay mutually restrict each other.
发明内容SUMMARY OF THE INVENTION
针对高压侧栅驱动电路的现有技术中，抗dV/dt能力、抗VS负偏压能力和通道传输延时不能兼顾的问题，本发明提出一种用于半桥结构的高压侧栅驱动电路，其中的采用的脉冲滤波电路具有很高的抗dV/dt噪声能力和抗VS负偏压能力，并且通道具有很小的传输延时，另外电路结构小巧，节约了版图面积。Aiming at the problem that the anti-dV/dt capability, the anti-VS negative bias capability and the channel transmission delay cannot be taken into account in the prior art of the high-voltage side gate drive circuit, the present invention proposes a high-voltage side gate drive circuit for a half-bridge structure , the pulse filter circuit used has high anti-dV/dt noise ability and anti-VS negative bias ability, and the channel has a small transmission delay. In addition, the circuit structure is small and the layout area is saved.
本发明所采用的技术方案为：The technical scheme adopted in the present invention is:
一种用于半桥结构的高压侧栅驱动电路，包括依次连接的窄脉冲产生电路、高压电平移位电路、脉冲滤波电路、RS触发器和栅驱动电路，窄脉冲产生电路将高压侧输入信号HIN的上升沿和下降沿分别转换成两路窄脉冲信号SET和RESET输出给高压电平移位电路，高压电平移位电路将低压区电路的两路窄脉冲信号SET和RESET转换为高压区电路信号VDS和VDR去分别控制高压电平移位电路中的两个高压功率开关器件，高压电平移位电路的两路输出信号与脉冲滤波电路的两个输入信号端相连接，脉冲滤波电路的两个输出信号分别连接RS触发器的置位输入端
所述脉冲滤波电路包括两条信号通路，第一通路包含第一缓冲电路、第一倒相器单元和第一整形电路，第二通路包含第二缓冲电路、第二倒相器单元和第二整形电路，第一缓冲电路的输入连接高压区电路信号VDS，第二缓冲电路的输入连接高压区电路信号VDR，第一倒相器单元和第二倒相器单元均设有四个端口，分别为第一端口、第二端口、第三端口和第四端口，两个倒相器单元的第一端口分别为两个倒相器单元的输入端，两个倒相器单元的第二端口分别为两个倒相器单元的输出端，两个倒相器单元的第三端口分别为两个倒相器单元的固定电位端，两个倒相器单元的第四端口分别为两个倒相器单元的的浮动电位端；第一缓冲电路的输出连接第一倒相器单元的第一端口和第二倒相器单元的第四端口，第二缓冲电路的输出连接第二倒相器单元的第一端口和第一倒相器单元的第四端口，第一倒相器单元的输出连接第一整形电路的输入端，第一整形电路的输出端连接RS触发器的置位输入端
所述第一倒相器单元和第二倒相器单元的第三端口连接供电电源信号或连接地信号，第一倒相器单元和第二倒相器单元的内部结构均包括至少一个倒相器或多个倒相器构成的倒相器链。The third ports of the first inverter unit and the second inverter unit are connected to a power supply signal or a ground signal, and the internal structures of the first inverter unit and the second inverter unit both include at least one inverter. inverter or inverter chain composed of multiple inverters.
所述第一缓冲电路包括倒相器500，倒相器500的输入端连接高压区电路信号VDS，倒相器500的输出连接第一倒相器单元的第一端口和第二倒相器单元的第四端口，第一倒相器单元包括PMOS管502和NMOS管503，PMOS管502的栅极和NMOS管503的栅极互连作为第一倒相器单元的第一端口，PMOS管502的漏极和NMOS管503的漏极互连作为第一倒相器单元的的第二端口连接第一整形电路，PMOS管502的源极作为第一倒相器单元的第三端口，NMOS管503的源极作为第一倒相器单元的第四端口；第二缓冲电路包括倒相器501，倒相器501的输入端连接高压区电路信号VDR，倒相器501的输出连接第二倒相器单元的第一端口和第一倒相器单元的第四端口，第二倒相器单元包括PMOS管504和NMOS管505，PMOS管504的栅极和NMOS管505的栅极互连作为第二倒相器单元的第一端口并与第一倒相器单元的第四端口和倒相器501的输出端连接，PMOS管504的漏极和NMOS管505的漏极互连作为第二倒相器单元的第二端口连接第二整形电路，PMOS管504的源极作为第二倒相器单元的第三端口并与第一倒相器单元的第三端口互连，NMOS管505的源极作为第二倒相器单元的第四端口连接第一倒相器单元的第一端口；第一整形电路包括倒相器507和倒相器509串联，倒相器507的输入端连接第一倒相器单元的的第二端口，倒相器509的输出连接RS触发器的置位输入端
所述第一缓冲电路也可以包括倒相器600和倒相器602串联，倒相器600的输入端连接高压区电路信号VDS，第一倒相器单元包括PMOS管604和NMOS管605，PMOS管604的栅极和NMOS管605的栅极互连作为第一倒相器单元的第一端口，PMOS管604的漏极和NMOS管605的漏极互连作为第一倒相器单元的的第二端口连接第二整形电路，PMOS管604的源极作为第一倒相器单元的第三端口，NMOS管605的源极作为第一倒相器单元的第四端口；第二缓冲电路包括倒相器601和倒相器603串联，倒相器601的输入端连接高压区电路信号VDR，第二倒相器单元包括PMOS管606和NMOS管607，PMOS管606的栅极和NMOS管607的栅极互连作为第二倒相器单元的第一端口连接第一倒相器单元的第三端口和倒相器602的输出端，PMOS管606的漏极和NMOS管607的漏极互连作为第二倒相器单元的的第二端口连接第一整形电路，PMOS管606的源极作为第二倒相器单元的第三端口连接第一倒相器单元的第一端口和倒相器603的输出端，NMOS管607的源极作为第二倒相器单元的第四端口并与第一倒相器单元的第四端口互连；第一整形电路包括倒相器608，倒相器608的输入端连接第二倒相器单元的第二端口，倒相器608的输出端连接RS触发器的置位输入端
所述窄脉冲产生电路将高压侧输入信号HIN的上升沿和下降沿分别转换成两路窄脉冲信号SET和RESET，窄脉冲信号RESET产生电路包括一个单脉冲产生电路，该单脉冲产生电路包括PMOS管801、NMOS管802、电阻RG、电容CG、施密特触发器803、倒相器804和或非门805，PMOS管801的栅极与NMOS管802的栅极互连作为输入端连接或非门805的一个输入端和高压侧输入信号HIN的下降沿，PMOS管801的源极连接低压侧固定电源VCC，PMOS管801的漏极连接电阻RG的一端，电阻RG的另一端与NMOS管802的漏极、电容CG的一端和施密特触发器803的输入端连接在一起，施密特触发器803的输出端连接倒相器804的输入端，倒相器804的输出端连接或非门805的另一个输入端，NMOS管802的源极和电容CG的另一端连接地信号COM，或非门805的输出为窄脉冲信号RESET；窄脉冲信号SET产生电路包括一个倒相器806和一个与窄脉冲信号RESET产生电路中结构完全相同的单脉冲产生电路，倒相器806的输入端连接高压侧输入信号HIN的上升沿，倒相器806的输出端连接单脉冲产生电路的输入端，单脉冲产生电路的输出为窄脉冲信号SET。The narrow pulse generation circuit converts the rising edge and the falling edge of the high-voltage side input signal HIN into two narrow pulse signals SET and RESET respectively, the narrow pulse signal RESET generation circuit includes a single pulse generation circuit, and the single pulse generation circuit includes PMOS A transistor 801, an NMOS transistor 802, a resistor RG, a capacitor CG , a Schmitt trigger 803, an inverter 804 and a NOR gate 805, the gate of the PMOS transistor 801 and the gate of the NMOS transistor 802 are interconnected as an input terminal One input terminal of the NOR gate 805 is connected to the falling edge of the high-voltage side input signal HIN, the source of the PMOS transistor 801 is connected to the low-voltage side fixed power supply VCC, the drain of the PMOS transistor 801 is connected to one end of the resistor RG , and the other end of the resistor RG is connected. One end is connected to the drain of the NMOS transistor 802, one end of the capacitor CG and the input end of the Schmitt trigger 803. The output end of the Schmitt trigger 803 is connected to the input end of the inverter 804. The inverter 804 The output end of the NOR gate 805 is connected to the other input end of the NOR gate 805, the source of the NMOS transistor 802 and the other end of the capacitor CG are connected to the ground signal COM, and the output of the NOR gate 805 is the narrow pulse signal RESET; the narrow pulse signal SET generating circuit It includes an inverter 806 and a single pulse generation circuit with the same structure as the narrow pulse signal RESET generation circuit. The input end of the inverter 806 is connected to the rising edge of the high-voltage side input signal HIN, and the output end of the inverter 806 is connected to The input end of the single-pulse generating circuit, and the output of the single-pulse generating circuit is the narrow pulse signal SET.
所述高压电平移位电路用于将低压区电路两路窄脉冲信号SET和RESET转换为高压区电路窄脉冲信号VDS和VDR，完成低压到高压的电平移位；包括高压功率开关器件LDM1和LDM2，均为LDMOS器件，负载电阻RL1和RL2，齐纳管Z1和Z2；高压功率开关器件LDM1的栅极连接窄脉冲信号SET，高压功率开关器件LDM2的栅极连接窄脉冲信号RESET，高压功率开关器件LDM1的漏极连接电阻RL1的一端和齐纳管Z1的正端并作为高压区电路信号VDS的输出端连接脉冲滤波电路的一个输入端，高压功率开关器件LDM2的漏极连接电阻RL2的一端和齐纳管Z2的正端并作为高压区电路信号VDR的输出端连接脉冲滤波电路的另一个输入端，高压功率开关器件LDM1的源极和高压功率开关器件LDM2的源极均连接地信号COM，负载电阻RL1和RL2的另一端以及齐纳管Z1和Z2的负端均连接高侧浮动电源VB。The high voltage level shift circuit is used to convert the two narrow pulse signals SET and RESET of the low voltage area circuit into the narrow pulse signals VDS and VDR of the high voltage area circuit to complete the level shift from low voltage to high voltage; including high voltage power switching devices LDM1 and LDM2, both of which are LDMOS devices, load resistors R L1 and R L2 , Zener transistors Z1 and Z2; the gate of the high-voltage power switching device LDM1 is connected to the narrow pulse signal SET, and the gate of the high-voltage power switching device LDM2 is connected to the narrow pulse signal RESET, The drain of the high-voltage power switching device LDM1 is connected to one end of the resistor RL1 and the positive end of the Zener Z1, and is connected to an input end of the pulse filter circuit as the output end of the high-voltage circuit signal VDS, and the drain of the high-voltage power switching device LDM2 is connected to One end of the resistor R L2 and the positive end of the Zener tube Z2 are connected to the other input end of the pulse filter circuit as the output end of the high voltage area circuit signal VDR, the source electrode of the high voltage power switching device LDM1 and the source electrode of the high voltage power switching device LDM2 Both are connected to the ground signal COM, the other ends of the load resistors R L1 and R L2 and the negative ends of the Zener tubes Z1 and Z2 are all connected to the high-side floating power supply VB.
所述RS触发器的作用是将置位输入端
所述栅驱动电路的作用是提高高压侧栅驱动电路的输出驱动能力，并且尽量减小高压侧浮动电源VB直接通过寄生通道泄放的电荷量，以保证高压侧浮动电源VB较长时间维持在适当的电压水平；包括倒相器702、倒相器703、PMOS管704和NMOS管705，倒相器702的输入端与倒相器703的输入端互连并连接RS触发器的输出端Q，倒相器702的输出连接PMOS管704的栅极，倒相器703的输出连接NMOS管705的栅极，PMOS管704的漏极与NMOS管705的漏极互连并作为栅驱动电路的输出端输出驱动高压侧功率开关器件的信号HO，PMOS管704的源极连接高压侧浮动电源VB，NMOS管705的源极连接浮动电压VS为参考地。The function of the gate drive circuit is to improve the output drive capability of the high-voltage side gate drive circuit, and to minimize the amount of charge discharged by the high-voltage side floating power supply VB directly through the parasitic channel, so as to ensure that the high-voltage side floating power supply VB is maintained at the high-voltage side for a long time. Appropriate voltage level; including inverter 702, inverter 703, PMOS transistor 704 and NMOS transistor 705, the input terminal of inverter 702 is interconnected with the input terminal of inverter 703 and connected to the output terminal Q of the RS flip-flop , the output of the inverter 702 is connected to the gate of the PMOS transistor 704, the output of the inverter 703 is connected to the gate of the NMOS transistor 705, and the drain of the PMOS transistor 704 is interconnected with the drain of the NMOS transistor 705 and serves as a gate driver circuit. The output terminal outputs a signal HO for driving the high-side power switch device, the source of the PMOS transistor 704 is connected to the high-side floating power supply VB, and the source of the NMOS transistor 705 is connected to the floating voltage VS as a reference ground.
与现有技术相比，本发明采用的技术方案具有如下优点和显著效果：Compared with the prior art, the technical solution adopted in the present invention has the following advantages and remarkable effects:
(1)本发明克服了高压栅驱动电路的抗dV/dt噪声能力、抗VS负偏压能力、通道传输延时互相制约的矛盾，极大地提高了高压栅驱动电路的抗dV/dt噪声能力和抗VS负偏压能力；(1) The present invention overcomes the contradiction that the anti-dV/dt noise capability, the anti-VS negative bias capability and the channel transmission delay of the high-voltage gate drive circuit are mutually restricted, and greatly improves the anti-dV/dt noise capability of the high-voltage gate drive circuit and anti-VS negative bias capability;
(2)本发明避免了使用R(电阻)C(电容)滤波电路结构，从而降低了电路通道的延时，提升了信号反应速度；(2) The present invention avoids the use of the R (resistance) C (capacitor) filter circuit structure, thereby reducing the delay of the circuit channel and improving the signal response speed;
(3)本发明可以容许一定的工艺偏差，而dV/dt噪声不会对高侧输出信号造成影响，进一步提升了抗dV/dt噪声能力和电路的可靠性；(3) The present invention can tolerate a certain process deviation, and the dV/dt noise will not affect the high-side output signal, further improving the anti-dV/dt noise capability and the reliability of the circuit;
(4)本发明电路结构简单、版图面积小。(4) The circuit structure of the present invention is simple and the layout area is small.
附图说明Description of drawings
图1是半桥驱动电路驱动外部功率管的基本拓扑结构；Figure 1 is the basic topology of the half-bridge drive circuit driving an external power tube;
图2a是高压侧栅驱动电路的结构图；2a is a structural diagram of a high-voltage side gate drive circuit;
图2b是高压侧栅驱动电路关键信号波形图；Figure 2b is a waveform diagram of key signals of the high-voltage side gate drive circuit;
图3是现有技术的一种RC脉冲滤波电路结构图；Fig. 3 is a kind of RC pulse filter circuit structure diagram of the prior art;
图4是本发明的新型脉冲滤波电路结构图；Fig. 4 is the novel pulse filter circuit structural diagram of the present invention;
图5是本发明的新型脉冲滤波电路一种实现方式；Fig. 5 is a kind of realization mode of the novel pulse filter circuit of the present invention;
图6是本发明的新型脉冲滤波电路另一种实现方式；Fig. 6 is another realization mode of the novel pulse filter circuit of the present invention;
图7是本发明的高压侧栅驱动电路的一种具体实施方式；FIG. 7 is a specific embodiment of the high-voltage side gate drive circuit of the present invention;
图8是窄脉冲产生电路的一种具体实施方式；FIG. 8 is a specific embodiment of a narrow pulse generating circuit;
图9是本发明实施案例在没有噪声干扰时的工作波形图；9 is a working waveform diagram of an embodiment of the present invention when there is no noise interference;
图10是本发明实施案例在有dV/dt噪声干扰且输出HO为高电平时的工作波形图；Fig. 10 is the working waveform diagram of the implementation case of the present invention when there is dV/dt noise interference and the output HO is a high level;
图11是本发明实施案例在有dV/dt噪声干扰且输出HO为低电平时的工作波形图。FIG. 11 is a working waveform diagram of the embodiment of the present invention when there is dV/dt noise interference and the output HO is low level.
具体实施方式Detailed ways
本发明高压侧栅驱动电路和图2a所示结构相同，包括窄脉冲产生电路200、高压电平移位电路201、脉冲滤波电路202、RS触发器203和栅驱动电路204，但其中的脉冲滤波电路与现有技术脉冲滤波电路202完全不同，且窄脉冲产生电路、高压电平移位电路、RS触发器和栅驱动电路为配合脉冲滤波电路也采用了较佳的实施电路。The high voltage side gate drive circuit of the present invention has the same structure as that shown in FIG. 2a, including a narrow pulse generation circuit 200, a high voltage level shift circuit 201, a pulse filter circuit 202, an RS flip-flop 203 and a gate drive circuit 204, but the pulse filter circuit 204 is The circuit is completely different from the pulse filter circuit 202 of the prior art, and the narrow pulse generation circuit, the high voltage level shift circuit, the RS flip-flop and the gate drive circuit also adopt better implementation circuits to match the pulse filter circuit.
如图4所示，本发明所采用的脉冲滤波电路202c包括两条信号通路，第一通路包含第一缓冲电路400、第一倒相器单元402和第一整形电路404，第二通路包含第二缓冲电路401、第二倒相器单元403和第二整形电路405，第一缓冲电路400的输入连接高压区电路信号VDS，第二缓冲电路401的输入连接高压区电路信号VDR，第一倒相器单元402和第二倒相器单元403均设有四个端口，分别为第一端口、第二端口、第三端口和第四端口，两个倒相器单元的第一端口分别为两个倒相器单元的输入端，两个倒相器单元的第二端口分别为两个倒相器单元的输出端，两个倒相器单元的第三端口分别为两个倒相器单元的固定电位端，两个倒相器单元的第四端口分别为两个倒相器单元的的浮动电位端；第一缓冲电路400的输出连接第一倒相器单元402的第一端口和第二倒相器单元403的第四端口，第二缓冲电路401的输出连接第二倒相器单元403的第一端口和第一倒相器单元402的第四端口，第一倒相器单元402的输出连接第一整形电路404的输入端，第一整形电路404的输出端连接RS触发器的置位输入端
图5是图4的一种实施电路，脉冲滤波电路202c中，第一缓冲电路包括倒相器500，倒相器500的输入端连接高压区电路信号VDS，第一倒相器单元402包括PMOS管502和NMOS管503，PMOS管502的栅极和NMOS管503的栅极互连作为第一倒相器单元402的第一端口，PMOS管502的漏极和NMOS管503的漏极互连作为第一倒相器单元402的第二端口连接第一整形电路，PMOS管502的源极作为第一倒相器单元402的第三端口，NMOS管503的源极作为第一倒相器单元402的第四端口；第二缓冲电路包括倒相器501，倒相器501的输入端连接高压区电路信号VDR，倒相器501的输出连接第二倒相器单元的第一端口和第一倒相器单元的第四端口，第二倒相器单元包括PMOS管504和NMOS管505，PMOS管504的栅极和NMOS管505的栅极互连作为第二倒相器单元403的第一端口并与第一倒相器单元402的第四端口和倒相器501的输出端连接，PMOS管504的漏极和NMOS管505的漏极互连作为第二倒相器单元403的第二端口连接第二整形电路，PMOS管504的源极作为第二倒相器单元403的第三端口并与第一倒相器单元402的第三端口互连，NMOS管505的源极作为第二倒相器单元403的第四端口连接第一倒相器单元402的第一端口；第一整形电路包括倒相器507和倒相器509串联，倒相器507的输入端连接第一倒相器单元402的的第二端口，倒相器509的输出连接RS触发器的置位输入端
图6是图4的另一种实施电路，脉冲滤波电路202c’中，第一缓冲电路包括倒相器600和倒相器602串联，倒相器600的输入端连接高压区电路信号VDS，第一倒相器单元402’包括PMOS管604和NMOS管605，PMOS管604的栅极和NMOS管605的栅极互连作为第一倒相器单元402’的第一端口，PMOS管604的漏极和NMOS管605的漏极互连作为第一倒相器单元402’的第二端口连接第二整形电路，PMOS管604的源极作为第一倒相器单元402’的第三端口，NMOS管605的源极作为第一倒相器单元402’的第四端口；第二缓冲电路包括倒相器601和倒相器603串联，倒相器601的输入端连接高压区电路信号VDR，第二倒相器单元403’包括PMOS管606和NMOS管607，PMOS管606的栅极和NMOS管607的栅极互连作为第二倒相器单元403’的第一端口连接第一倒相器单元402’的第三端口和倒相器602的输出端，PMOS管606的漏极和NMOS管607的漏极互连作为第二倒相器单元403’的的第二端口连接第一整形电路，PMOS管606的源极作为第二倒相器单元403’的第三端口连接第一倒相器单元402’的第一端口和倒相器603的输出端，NMOS管607的源极作为第二倒相器单元403’的第四端口并与第一倒相器单元402’的第四端口互连；第一整形电路包括倒相器608，倒相器608的输入端连接第二倒相器单元403’的第二端口，倒相器608的输出端连接RS触发器的置位输入端
如图7，为本发明用于半桥结构的高压浮栅驱动电路的具体实施电路图，包括窄脉冲产生电路200、高压电平移位电路201、脉冲滤波电路202、RS触发器203和栅驱动电路204。其中，窄脉冲产生电路200的输入端为HIN，窄脉冲产生电路200的输出端为SET和RESET，SET和RESET又作为高压电平移位电路201的两个输入端，高压电平移位电路201的输出端为VDS和VDR，VDS和VDR同时作为采用图5的脉冲滤波电路202c的两个输入端，脉冲滤波电路202c的两个输出端分别与RS触发器203的置位输入端
图8是图7中窄脉冲产生电路200的一种具体实施电路，该电路是由两条通路组成，通路一包含一个单脉冲产生电路800，通路二包含一个倒相器806和一个单脉冲产生电路800。单脉冲产生电路800是由电阻、电容、施密特触发器、倒相器和或非门构成，PMOS管801的栅极、NMOS管802的栅极和或非门805的一个输入端相连接，作为单脉冲产生电路800的输入端，PMOS管801的漏极与电阻RG的一端相连接，NMOS管802的漏极、RG的另一端、电容CG的一端和施密特触发器803的输入端相连接，PMOS管801的源极连接低侧固定电源VCC，NMOS管802的源极连接地信号COM，施密特触发器803的输出端连接倒相器804的输入端，倒相器804的输出连接或非门805的另一个输入端，或非门805的输出作为单脉冲产生电路800的输出端。窄脉冲产生电路200的功能是将高侧输入信号HIN转换为两路窄脉冲信号，分别代表输入信号HIN的上升沿和下降沿，高压电平移位电路(201)中的高压功率开关器件由这两路窄脉冲信号驱动。FIG. 8 is a specific implementation circuit of the narrow pulse generating circuit 200 in FIG. 7 . The circuit is composed of two paths. Path 1 includes a single-pulse generating circuit 800 , and path 2 includes an inverter 806 and a single-pulse generating circuit 800 . circuit 800. The single pulse generating circuit 800 is composed of a resistor, a capacitor, a Schmitt trigger, an inverter and a NOR gate, and the gate of the PMOS transistor 801, the gate of the NMOS transistor 802 and one input of the NOR gate 805 are connected , as the input end of the single pulse generation circuit 800, the drain of the PMOS transistor 801 is connected to one end of the resistor RG , the drain of the NMOS transistor 802, the other end of RG, one end of the capacitor CG and the Schmitt trigger The input terminal of 803 is connected to each other, the source of the PMOS transistor 801 is connected to the low-side fixed power supply VCC, the source of the NMOS transistor 802 is connected to the ground signal COM, and the output terminal of the Schmitt trigger 803 is connected to the input terminal of the inverter 804. The output of the phaser 804 is connected to the other input terminal of the NOR gate 805 , and the output of the NOR gate 805 is used as the output terminal of the single pulse generating circuit 800 . The function of the narrow pulse generation circuit 200 is to convert the high-side input signal HIN into two narrow pulse signals, which represent the rising edge and the falling edge of the input signal HIN respectively. The high-voltage power switching device in the high-voltage level shift circuit (201) is composed of These two channels are driven by narrow pulse signals.
图7中的高压电平移位电路201的实施例包含高压功率开关器件(LDM1、LDM2)、负载电阻(RL1、RL2)和齐纳管(Z1、Z2)，其中高压功率开关器件LDM1和LDM2为LDMOS器件。LDM1的栅极为SET信号，LDM2的栅极为RESET信号，LDM1的漏极连接电阻RL1和齐纳管Z1的正端，LDM2的漏极连接电阻RL2和齐纳管Z2的正端，LDM1、LDM2的源极连接地信号COM，负载电阻(RL1、RL2)和齐纳管(Z1、Z2)的负端连接高侧浮动电源VB，LDM1的漏极作为高压电平移位电路201的一个输出端VDS，LDM2的漏极作为高压电平移位电路201的另一个输出端VDR。高压电平移位电路201的作用是分别将低压区电路两路窄脉冲信号(SET和RESET)转换为高压区电路窄脉冲信号(VDS和VDR)，完成低压到高压的电平移位。The embodiment of the high voltage level shift circuit 201 in FIG. 7 includes high voltage power switching devices ( LDM1 , LDM2 ), load resistors ( R L1 , R L2 ) and zeners (Z1 , Z2 ), wherein the high voltage power switching device LDM1 and LDM2 are LDMOS devices. The gate of LDM1 is the SET signal, the gate of LDM2 is the RESET signal, the drain of LDM1 is connected to the positive end of the resistor R L1 and the Zener tube Z1, the drain of the LDM2 is connected to the positive end of the resistor R L2 and the Zener tube Z2, LDM1, The source of the LDM2 is connected to the ground signal COM, the negative terminals of the load resistors (R L1 , R L2 ) and the Zeners (Z1, Z2) are connected to the high-side floating power supply VB, and the drain of the LDM1 is used as the high-voltage level shift circuit 201. One output terminal VDS, the drain of LDM2 is used as the other output terminal VDR of the high voltage level shift circuit 201 . The function of the high voltage level shift circuit 201 is to convert the two narrow pulse signals (SET and RESET) of the low voltage area circuit into narrow pulse signals (VDS and VDR) of the high voltage area circuit respectively to complete the level shift from low voltage to high voltage.
图7中的RS触发器203的实施例包括两个与非门(700和与701)，与非门700的一个输入信号为
图7中的栅驱动电路204的实施例包括倒相器702、倒相器703的输入端与RS触发器的输出端Q相连接，倒相器702的输出端与PMOS管704的栅极相连接，倒相器703的输出端与NMOS管705的栅极相连接，PMOS管704的漏极与705的漏极相连接，并且作为高侧输出信号HO。栅驱动电路204的作用是提高高压侧栅驱动电路的输出驱动能力，以驱动高侧功率器件MH，并且尽量减小高侧浮动电源VB直接通过寄生通道泄放的电荷量，以保证VB较长时间维持在适当的电压水平。The embodiment of the gate drive circuit 204 in FIG. 7 includes an inverter 702 , the input terminal of the inverter 703 is connected to the output terminal Q of the RS flip-flop, and the output terminal of the inverter 702 is connected to the gate of the PMOS transistor 704 Connected, the output terminal of the inverter 703 is connected to the gate of the NMOS transistor 705, the drain of the PMOS transistor 704 is connected to the drain of the 705, and the high-side output signal HO is used. The function of the gate drive circuit 204 is to improve the output drive capability of the high-voltage side gate drive circuit to drive the high-side power device MH , and to minimize the amount of charge discharged by the high-side floating power supply VB directly through the parasitic channel, so as to ensure that VB is relatively high. maintain the proper voltage level for a long time.
如图9，无dV/dt噪声干扰时电路的工作波形，输入信号HIN的上升沿处产生了SET脉冲信号，SET信号使高压功率开关器件LDM1打开，VDS变为低电平，VDS脉冲信号经过脉冲滤波电路(202c或202c’)后对RS触发器(203)进行置位，Q变为高电平，HO变为高电平；输入信号HIN的下降沿产生脉冲信号RESET，RESET信号使高压功率开关器件LDM2打开，VDR脉冲信号经过新型脉冲滤波电路后对RS触发器203进行复位，Q变为低电平，HO变为低电平。As shown in Figure 9, the working waveform of the circuit when there is no dV/dt noise interference, the SET pulse signal is generated at the rising edge of the input signal HIN, the SET signal turns on the high-voltage power switching device LDM1, VDS becomes a low level, and the VDS pulse signal passes through After the pulse filter circuit (202c or 202c'), the RS flip-flop (203) is set, Q becomes a high level, and HO becomes a high level; the falling edge of the input signal HIN generates the pulse signal RESET, and the RESET signal makes the high voltage The power switching device LDM2 is turned on, the VDR pulse signal resets the RS flip-flop 203 after passing through the new pulse filter circuit, Q becomes low level, and HO becomes low level.
如图10，低侧输入(LIN)为低电平，高侧输入(HIN)由低电平变为高电平后，高侧输出HO变为高电平，所驱动的功率管MH开启，高侧浮动地VS电压上升，VS电压变化通过自举电容耦合到高侧浮动电源VB，高压功率开关器件(LDM1和LDM2)的寄生电容上产生位移电流，并在负载电阻(RL1和RL2)上产生压降，使VDS和VDR相对于VS表现为低电平，由于VDS和VDR为共模信号，可以被脉冲滤波电路消除，不会对高侧输出状态造成影响。As shown in Figure 10, the low-side input (LIN) is at a low level. After the high-side input (HIN) changes from a low level to a high level, the high-side output HO changes to a high level, and the driven power transistor MH is turned on. The high-side floating ground VS voltage rises, and the VS voltage change is coupled to the high-side floating power supply VB through the bootstrap capacitor . ) produces a voltage drop, which makes VDS and VDR appear low level relative to VS. Since VDS and VDR are common-mode signals, they can be eliminated by the pulse filter circuit and will not affect the high-side output state.
如图11，高侧输入(HIN)为低，低侧输入(LIN)由高变低后，由于感性负载电流在通过高侧功率器件体二极管的续流作用，导致VS端电压抬升，高侧浮动电源VB产生同步变化，因此负载电阻(RL1和RL2)上同样会产生压降，使VDS和VDR相对于VS表现为低电平，由于VDS和VDR为共模信号，可以被脉冲滤波电路消除，也不会对高侧输出状态造成影响。As shown in Figure 11, when the high-side input (HIN) is low, and the low-side input (LIN) changes from high to low, due to the freewheeling effect of the inductive load current through the body diode of the high-side power device, the voltage at the VS terminal rises, and the high-side The floating power supply VB changes synchronously, so there will also be a voltage drop on the load resistors (R L1 and R L2 ), so that VDS and VDR are low relative to VS. Since VDS and VDR are common mode signals, they can be pulse filtered. The circuit is eliminated, and it will not affect the high-side output state.
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