CN107911112A - A kind of low reference spur charge pump type phaselocked loop circuit of electrically charged pump correcting current technology - Google Patents

本发明公开了一种带电荷泵电流校准技术的低参考杂散电荷泵型锁相环电路，通过增加由时间放大器(TA)、时间电压转换器(TVC)和模拟数字转换器(ADC)构成的校准电路，使电荷泵输出电流匹配特性得到极大提高，从而使电荷泵型锁相环电路极大程度的降低了输出信号参考杂散，使得无线通信收发机系统的相邻信道的干扰极大减弱，可以满足高性能需求的通信系统。

The invention discloses a low-reference stray charge pump phase-locked loop circuit with a charge pump current calibration technology, which is composed of a time amplifier (TA), a time-voltage converter (TVC) and an analog-to-digital converter (ADC) The calibration circuit of the charge pump greatly improves the output current matching characteristics of the charge pump, so that the charge pump phase-locked loop circuit greatly reduces the output signal reference spurious, making the interference of the adjacent channel of the wireless communication transceiver system extremely Large attenuation, a communication system that can meet high-performance requirements.

一种带电荷泵电流校准技术的低参考杂散电荷泵型锁相环 电路A low-reference stray charge-pump phase-locked loop with charge-pump current calibration technique circuit

技术领域technical field

本发明涉及射频集成电路技术领域，尤其涉及一种带电荷泵电流校准技术的低参考杂散电荷泵型锁相环电路。The invention relates to the technical field of radio frequency integrated circuits, in particular to a low-reference stray charge pump phase-locked loop circuit with charge pump current calibration technology.

背景技术Background technique

随着集成电路的发展，关于产生时钟信号或者本振信号的锁相环的研究也日益趋于成熟，其中用作本振信号的锁相环输出信号尤其关注其参考杂散性能，因为无线通信系统中调制/解调过程的本振信号的参考杂散较大时，会在相邻信道产生串扰，降低通信系统信噪比和通信质量，限制通信系统频率的进一步增高。换言之，随着对通信系统质量和性能越来越严苛的要求，能满足系统要求的低参考杂散的锁相环也成为攻克和研究难点。With the development of integrated circuits, the research on phase-locked loops that generate clock signals or local oscillator signals is becoming more and more mature. The output signal of the phase-locked loop used as local oscillator signals is particularly concerned about its reference spurious performance, because wireless communication When the reference spur of the local oscillator signal in the modulation/demodulation process in the system is large, crosstalk will be generated in adjacent channels, which will reduce the signal-to-noise ratio and communication quality of the communication system, and limit the further increase of the frequency of the communication system. In other words, with the increasingly stringent requirements on the quality and performance of communication systems, a phase-locked loop with low reference spurs that can meet system requirements has become a difficult problem to overcome and research.

目前为止，对于电荷泵型锁相环(Charge Pump Phase-Locked Loop,PLL)的研究主要关注点在于降低占用面积、相位噪声、降低耗和参考杂散，其中参考杂散的降低近几年研究热点，已经提出的针对于降低参考杂散的方法多是改进电荷泵(Charge Pump,CP)电路结构以提高其电流匹配性，从而降低压控振荡器(Voltage-Controlled Oscillator,VCO)压控曲线上的电压纹波，以达到降低参考杂散的目的。但CP的动态电流匹配性几乎不可能做到完全匹配，因此此类方法对于参考杂散性能只能有程度较小的改善。So far, the research on Charge Pump Phase-Locked Loop (PLL) mainly focuses on reducing occupied area, phase noise, power consumption and reference spurs. The reduction of reference spurs has been studied in recent years. Hotspots, most of the proposed methods for reducing reference spurs are to improve the charge pump (Charge Pump, CP) circuit structure to improve its current matching, thereby reducing the voltage control curve of the voltage-controlled oscillator (Voltage-Controlled Oscillator, VCO) The voltage ripple on the upper, in order to achieve the purpose of reducing reference spurs. However, the dynamic current matching of CP is almost impossible to achieve a complete match, so this method can only improve the reference spurious performance to a small extent.

传统的电荷泵型锁相环电路结构如图1所示，包括：鉴频鉴相器(Phase FrequencyDetector,PFD)、电荷泵(Charge Pump,CP)、环路滤波器(Loop Filter,LP)、压控振荡器(VCO)、分频器(Divider)。其中，传统CPPLL电路参考杂散的主要来源是PFD和CP电路的非线性以及电流失配等非理想特性导致VCO压控曲线上有电压纹波，且此纹波周期与输入参考信号周期相同，从而在使输出信号频谱变现为在偏离中心频率参考信号频率处有一突出频谱。现假设纹波Vripple近似为余弦波：The structure of the traditional charge pump phase-locked loop circuit is shown in Figure 1, including: phase frequency detector (Phase Frequency Detector, PFD), charge pump (Charge Pump, CP), loop filter (Loop Filter, LP), Voltage controlled oscillator (VCO), frequency divider (Divider). Among them, the main source of reference spurs in traditional CPPLL circuits is the non-ideal characteristics of PFD and CP circuits, such as nonlinearity and current mismatch, which lead to voltage ripples on the VCO voltage control curve, and the ripple cycle is the same as the input reference signal cycle. Therefore, the frequency spectrum of the output signal appears to have a prominent frequency spectrum at the frequency of the reference signal deviated from the center frequency. Now assume that the ripple Vripple is approximated as a cosine wave:

V_ripple(t)＝V_mcos nω_reft (1)V _ripple (t) = V _m cos nω _ref t (1)

式(1)中，n＝1，2，3….。V_m为纹波幅度，ω_ref为参考信号角频率。则压控振荡器的输出为：In formula (1), n=1, 2, 3.... V _m is the ripple amplitude, and ω _ref is the angular frequency of the reference signal. Then the output of the VCO is:

V_out(t)＝V₀cos(ω₀t+K_vco∫V_c(t)dt) (2)V _out (t)＝V ₀ cos(ω ₀ t+K _vco ∫V _c (t)dt) (2)

式(2)展开得实际锁相环的输出电压为：Equation (2) expands the output voltage of the actual phase-locked loop as:

式(2)(3)中，n＝1，2，3….。V₀为振荡器振荡信号幅度，ω_ref为参考信号角频率，ω₀为振荡信号角频率，V_m为纹波幅度，K_VCO为振荡器增益系数。由式(3)可知，参考杂散的幅值随着压控振荡器上纹波幅值的增大而增大。In formula (2) (3), n=1, 2, 3.... V ₀ is the oscillation signal amplitude of the oscillator, ω _ref is the angular frequency of the reference signal, ω ₀ is the angular frequency of the oscillation signal, V _m is the ripple amplitude, and K _VCO is the oscillator gain coefficient. It can be seen from the formula (3) that the amplitude of the reference stray increases with the increase of the ripple amplitude on the voltage-controlled oscillator.

发明内容Contents of the invention

本发明的目的是提供一种低参考杂散快速锁定的电荷泵型锁相环电路，可以有效的降低参考杂散。The purpose of the present invention is to provide a charge pump type phase-locked loop circuit with low reference stray fast locking, which can effectively reduce the reference stray.

本发明的目的是通过以下技术方案实现的：一种带电荷泵电流校准技术的低参考杂散电荷泵型锁相环电路，包括鉴频鉴相器(PFD)、环路滤波器(LF)、校准电路、电荷泵(CP)、压控振荡器(VCO)、分频器(Divider)、锁定检测器(LD)；其连接关系如下：The purpose of the present invention is achieved by the following technical solutions: a low-reference stray charge-pump phase-locked loop circuit with charge-pump current calibration technology, comprising a phase-frequency detector (PFD), a loop filter (LF) , calibration circuit, charge pump (CP), voltage-controlled oscillator (VCO), frequency divider (Divider), lock detector (LD); the connections are as follows:

依次连接的鉴频鉴相器、电荷泵、校准电路、环路滤波器、压控振荡器和分频器，校准电路输入端与鉴频鉴相器输出端相连接，校准电路输出信号与电荷泵数字控制位连接；所述分频器输入端与压控振荡器输出相连，所述分频器输出端与鉴频鉴相器一端口相连，所述鉴频鉴相器另一端口与输入参考信号相连，所述锁定检测电路输出端与校准电路使能控制端相连接。A frequency and phase detector, a charge pump, a calibration circuit, a loop filter, a voltage-controlled oscillator and a frequency divider connected in sequence, the input of the calibration circuit is connected to the output of the frequency and phase detector, and the output signal of the calibration circuit is connected to the charge The digital control bit of the pump is connected; the input terminal of the frequency divider is connected with the output of the voltage controlled oscillator, the output terminal of the frequency divider is connected with one port of the frequency and phase detector, and the other port of the frequency and phase detector is connected with the input The reference signal is connected, and the output terminal of the lock detection circuit is connected with the enabling control terminal of the calibration circuit.

其中，所述校准电路包括依次连接的时间放大器、时间电压转换器和模拟数字转换器。Wherein, the calibration circuit includes a time amplifier, a time-to-voltage converter and an analog-to-digital converter connected in sequence.

其中，所述时间放大器左右对称，半边电路包运算放大器、开关S₁、S₂、电流源I_1,1，I_1,1、电容C₁和输入IN1控制开关，连接关系如下：运算放大器正极连接固定参考电压，负极与电容正极、开关S₁、S₂相连接和输入IN1控制开关相连接，输出端为输出信号端；电容负极连接至地，电流源I_1,1，I_1,1负极连接至地，正极与开关S₁、S₂相连接。Wherein, the time amplifier is left-right symmetrical, and half of the circuit includes an operational amplifier, switches S ₁ , S ₂ , current sources I _1,1 , I _1,1 , capacitor C ₁ and input IN1 to control the switch, and the connection relationship is as follows: the positive pole of the operational amplifier Connect a fixed reference voltage, the negative pole is connected to the positive pole of the capacitor, the switches S ₁ and S ₂ are connected to the input IN1 control switch, the output terminal is the output signal terminal; the negative pole of the capacitor is connected to the ground, the current source I _1,1 , I _1,1 The negative pole is connected to the ground, and the positive pole is connected to the switches S ₁ and S ₂ .

由上述本发明提供的技术方案可以看出，通过在PFD和CP之间引入时间放大器(Time Amplifier,TA)、时间电压转换器(Time to Voltage Converter,TVC)和模拟数字转换器(Analog to Digital Converter,ADC)构成的电流校准电路，以检测UP和DN信号间脉宽差，并将脉宽差转换成数字信号以用来调整电荷泵的I_UP和I_DN的大小以提高其电流匹配特性，从而使环路输出信号参考杂散性能得到大程度的优化，使得无线通信收发机系统的相邻信道的干扰极大减弱。As can be seen from the technical solution provided by the present invention above, by introducing a time amplifier (Time Amplifier, TA), a time voltage converter (Time to Voltage Converter, TVC) and an analog to digital converter (Analog to Digital Converter) between the PFD and the CP Converter, ADC) constitutes a current calibration circuit to detect the pulse width difference between UP and DN signals, and convert the pulse width difference into a digital signal to adjust the size of I _UP and I _DN of the charge pump to improve its current matching characteristics , so that the reference spurious performance of the loop output signal is optimized to a large extent, so that the interference of the adjacent channel of the wireless communication transceiver system is greatly weakened.

附图说明Description of drawings

为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他附图。In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings on the premise of not paying creative work.

图1为本发明背景技术提供的电荷泵型锁相环基本结构及非理想特性示意图；Fig. 1 is the charge pump type phase-locked loop basic structure and the non-ideal characteristic schematic diagram that background technology of the present invention provides;

图2为本发明实施例提供的一种带电荷泵电流校准技术的低参考杂散的电荷泵型锁相环电路结构示意图；2 is a schematic structural diagram of a charge pump phase-locked loop circuit with low reference spurs provided by an embodiment of the present invention with charge pump current calibration technology;

图3为本发明实施例提供的时间放大器电路示意图；3 is a schematic diagram of a time amplifier circuit provided by an embodiment of the present invention;

图4为本发明实施例提供的时间电压转换器电路示意图；FIG. 4 is a schematic diagram of a time-to-voltage converter circuit provided by an embodiment of the present invention;

图5为本发明实施例提供的带数字控制位的电荷泵晶体管级电路示意图。FIG. 5 is a schematic diagram of a charge pump transistor level circuit with digital control bits provided by an embodiment of the present invention.

具体实施方式Detailed ways

下面结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明的保护范围。The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

图2为本发明实施例提供的一种带电荷泵电流校准技术的低参考杂散的电荷泵型锁相环电路，如图2所示，其主要包括：鉴频鉴相器(PFD)、环路滤波器(LF)、校准电路、电荷泵(CP)、压控振荡器(VCO)、分频器(Divider)、锁定检测器(LD)。其连接关系为：依次连接的鉴频鉴相器、电荷泵、环路滤波器(LF)、压控振荡器和分频器，校准电路输入端与PFD输出端相连接，校准电路输出信号与CP数字控制位连接。所述Divider输入端与VCO输出相连，所述Divider输出端与PFD一端口相连，所述PFD另一端口与输入参考信号相连，所述LD输出端与校准电路使能控制端相连接。Fig. 2 is a kind of low reference stray charge-pump type phase-locked loop circuit of band charge-pump current calibration technology that the embodiment of the present invention provides, as shown in Fig. 2, it mainly comprises: phase-frequency detector (PFD), Loop Filter (LF), Calibration Circuit, Charge Pump (CP), Voltage Controlled Oscillator (VCO), Frequency Divider (Divider), Lock Detector (LD). Its connection relationship is: frequency and phase detector, charge pump, loop filter (LF), voltage controlled oscillator and frequency divider connected in sequence, the input terminal of the calibration circuit is connected with the output terminal of the PFD, and the output signal of the calibration circuit is connected with the output terminal of the PFD. CP digital control bit connection. The Divider input terminal is connected to the VCO output, the Divider output terminal is connected to one port of the PFD, the other port of the PFD is connected to the input reference signal, and the LD output terminal is connected to the calibration circuit enabling control terminal.

所述的校准电路包括依次连接的时间放大器TA，时间电压转换器TVC和模拟数字转换器ADC。The calibration circuit includes a time amplifier TA, a time-to-voltage converter TVC and an analog-to-digital converter ADC connected in sequence.

如图3所示，为所述的时间放大器电路。所述时间放大器左右对称，半边电路包运算放大器、开关S₁、S₂、电流源I_1,1，I_1,1、电容C₁和输入IN1控制开关。连接关系如下：运算放大器正极连接固定参考电压，负极与电容正极、开关S₁、S₂相连接和输入IN1控制开关相连接，输出端为输出信号端；电容负极连接至地，电流源I_1,1，I_1,1负极连接至地，正极与开关S₁、S₂相连接。As shown in Figure 3, it is the time amplifier circuit. The time amplifier is left-right symmetrical, and half of the circuit includes an operational amplifier, switches S ₁ , S ₂ , current sources I _1,1 , I _1,1 , capacitor C ₁ and input IN1 to control the switch. The connection relationship is as follows: the positive pole of the operational amplifier is connected to a fixed reference voltage, the negative pole is connected to the positive pole of the capacitor, the switches S ₁ and S ₂ are connected to the input IN1 control switch, the output terminal is the output signal terminal; the negative pole of the capacitor is connected to the ground, and the current source I _{1 ,1} , the negative pole of I _1,1 is connected to the ground, and the positive pole is connected to the switches S ₁ and S ₂ .

如图4所示，为所述校准电路1和校准电路2中采用的时间电压转换器TVC1和TVC2晶体管级电路。所述时间电压转换器TVC1包括晶体管NM1、NM2、PM1和电容C1。TVC2包括晶体管NM3、NM4、PM2和电容C2。连接关系为：NM1源极接地且漏极与NM2源极相连接，PM1源极连接至VDD，漏极与NM2漏极连接且与电容正极和输出端连接，电容负极连接至地，NM1栅极连接至VDD，NM2栅极连接至DN信号，PM1栅极连接至LD输出的锁定信号。NM4源极接地且漏极与NM3源极相连接，PM2源极连接至VDD且漏极与NM3漏极连接且与电容正极和输出端连接，电容负极连接至地，NM3栅极连接至VDD，NM4栅极连接至DN信号，PM2栅极连接至LD输出的锁定信号。As shown in FIG. 4 , it is the transistor-level circuits of the time-to-voltage converters TVC1 and TVC2 used in the calibration circuit 1 and the calibration circuit 2 . The time-to-voltage converter TVC1 includes transistors NM1, NM2, PM1 and a capacitor C1. TVC2 includes transistors NM3, NM4, PM2 and capacitor C2. The connection relationship is: the source of NM1 is grounded and the drain is connected to the source of NM2, the source of PM1 is connected to VDD, the drain is connected to the drain of NM2 and connected to the positive electrode of the capacitor and the output terminal, the negative electrode of the capacitor is connected to the ground, and the gate of NM1 Connect to VDD, NM2 gate to DN signal, PM1 gate to lock signal from LD output. The source of NM4 is grounded and the drain is connected to the source of NM3, the source of PM2 is connected to VDD and the drain is connected to the drain of NM3 and connected to the positive electrode of the capacitor and the output terminal, the negative electrode of the capacitor is connected to ground, and the gate of NM3 is connected to VDD. The gate of NM4 is connected to the DN signal, and the gate of PM2 is connected to the lock signal of the LD output.

如图5所示，为所述带3位数字控制位的电荷泵电路。其中，晶体管MN₁-MN₆和PM1-PM₄实现电流镜功能；MN_C1-MN_C3和MP_C1-MN_C3为数字控制位，以调整I_UP和I_DN的大小来提高电流匹配性。MN₁₀，MN₁₁，MP₉，MP₁₀将偏置电流镜像至电荷泵输出管MN₁₂和MP₇。As shown in Figure 5, it is the charge pump circuit with 3 digital control bits. Among them, the transistors MN ₁ -MN ₆ and PM1-PM ₄ implement the current mirror function; MN _C1 -MN _C3 and MP _C1 -MN _C3 are digital control bits to adjust the size of I _UP and I _DN to improve current matching. MN ₁₀ , MN ₁₁ , MP ₉ , MP ₁₀ mirror the bias current to the charge pump output transistors MN ₁₂ and MP ₇ .

所述电荷泵型锁相环环路未进入锁定状态时，LD电路输出为0，校准电路不工作，即CPPLL在普通锁定过程不会进行CP电流校准行为，当CPPLL环路达到锁定状态时，LD电路输出信号为1，校准电路触发进入工作状态。由于CP的电流失配和PFD延时不匹配等非理想因素造成的UP信号与DN信号脉宽不相同，TA将脉宽差进行放大以可鉴别脉宽精度，并将放大后的信号通过TVC转换为与脉宽对应的电压值，ADC将该电压值转换为3位数字信号并用于调整优化CP的电流匹配特性。例如，若UP脉宽大于DN脉宽，也即I_UP<I_DN时，ADC输出信号会使CP的I_DN增加以提高I_UP和I_DN的匹配性，UP脉宽小于DN脉宽时情况在则相反。CP和PFD非理想性因素引起的UP与DN脉宽失配将会通过本发明提出的校准技术得到大程度降低，从而有效的降低了环路输出信号的参考杂散。When the charge pump type phase-locked loop loop does not enter the locked state, the LD circuit output is 0, and the calibration circuit does not work, that is, the CPPLL will not perform the CP current calibration behavior in the ordinary locking process. When the CPPLL loop reaches the locked state, The output signal of the LD circuit is 1, and the calibration circuit is triggered to enter the working state. Due to non-ideal factors such as CP current mismatch and PFD delay mismatch, the pulse width of the UP signal is different from that of the DN signal. TA amplifies the pulse width difference to identify the pulse width accuracy, and passes the amplified signal through TVC. Converted to a voltage value corresponding to the pulse width, the ADC converts the voltage value into a 3-bit digital signal and is used to adjust and optimize the current matching characteristics of the CP. For example, if the UP pulse width is greater than the DN pulse width, that is, when I _UP <I _DN , the ADC output signal will increase the I _DN of the CP to improve the matching between I _UP and I _DN , and the situation when the UP pulse width is smaller than the DN pulse width In is the opposite. The mismatch of UP and DN pulse widths caused by the non-ideal factors of CP and PFD will be greatly reduced through the calibration technology proposed by the present invention, thereby effectively reducing the reference spurious of the loop output signal.

以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明披露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求书的保护范围为准。The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person familiar with the technical field can easily conceive of changes or changes within the technical scope disclosed in the present invention. Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.