CN108052419B - Data disaster tolerance method - Google Patents
- ️Tue Oct 26 2021
CN108052419B - Data disaster tolerance method - Google Patents
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- CN108052419B CN108052419B CN201810009406.4A CN201810009406A CN108052419B CN 108052419 B CN108052419 B CN 108052419B CN 201810009406 A CN201810009406 A CN 201810009406A CN 108052419 B CN108052419 B CN 108052419B Authority
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000005540 biological transmission Effects 0.000 claims abstract description 33
- 238000011084 recovery Methods 0.000 claims abstract description 14
- 238000012545 processing Methods 0.000 claims abstract description 6
- 238000002360 preparation method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 238000012423 maintenance Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013523 data management Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1443—Transmit or communication errors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1458—Management of the backup or restore process
- G06F11/1464—Management of the backup or restore process for networked environments
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Abstract
本发明涉及容灾领域，特别涉及一种数据容灾的方法，其主要原理为：根据数据的模块化处理并进行镜像处理，在主处理器进行数据传输的过程中同时进行RAM的虚拟传输过程，即主处理器将寄存器以及RAM中对应的实时传输完成的数据模块删除以达到虚拟传输与实时传输在未传输部分的一致，同时也能达到时间上的一致，在发生数据灾难时，主处理器可以迅速的进行数据的填补传输，达到提高主处理器对数据灾难的应对效率的目的。同时，通过虚拟以及实时传输同时进行的方法，减少了主处理器应对数据灾难的延时性问题。
The invention relates to the field of disaster recovery, in particular to a method for data disaster recovery. , that is, the main processor deletes the data module corresponding to the real-time transmission in the register and RAM to achieve the consistency between the virtual transmission and the real-time transmission in the untransmitted part, and also achieve the consistency in time. In the event of a data disaster, the main processing The processor can quickly fill in and transmit data to achieve the purpose of improving the main processor's response efficiency to data disasters. At the same time, through the simultaneous method of virtual and real-time transmission, the delay problem of the main processor in dealing with the data disaster is reduced.
Description
Technical Field
The invention relates to the field of disaster tolerance, in particular to a data disaster tolerance method.
Background
With the development of information technology, databases are more and more widely used, and particularly, when a database or a data center of the database or the data center is formed in the industries such as telecommunications, finance, electronic commerce and the like, in order to ensure that data is subjected to a serious disaster, the database or the data center does not hinder the normal operation of a service system in the industries such as telecommunications, finance, electronic commerce and the like, and must have a certain disaster tolerance capability. In the prior art, in order to improve the disaster tolerance capability of a database or a data center, the following method is generally adopted for data disaster tolerance: the first method comprises the following steps: one-to-one mirror image disaster recovery backup is realized; and carrying out disaster recovery backup by adopting the same type of disaster recovery backup database or host. The method has good disaster tolerance capability, and when one host or one database is abnormal, the other host or the database can be started immediately; however, this method has high hardware and maintenance costs, and has many limitations in subsequent data management, capacity expansion, and the like. And the second method comprises the following steps: the disaster recovery backup method based on the information such as the filing log or the redo log well solves the problem of high hardware and maintenance cost, but has the possible problems that if the data in the database stores backup data, the data can be completely restored only by manual decompression of maintenance staff, and obviously, the method has the problems of insufficient intelligence, large time delay, low efficiency and the like.
Disclosure of Invention
The purpose of the invention is as follows:
in view of the above problems, the present invention provides a method for data disaster recovery.
The technical scheme is as follows:
a data disaster tolerance method comprises the following steps:
s010: the main processor divides data into a plurality of data modules, mirrors the data modules and stores the data modules in a plurality of RAMs;
s020: the main processor sends data according to the sequence of the data modules;
s030: when a first data module reaches a first node, the main processor writes the first data module into a first register, and the first register temporarily stores the first data module;
s040: the main processor identifying a first data module temporarily stored in the first register;
s050: the main processor deletes a corresponding first data module in the first RAM according to the identified first data module in the first register;
s060: when a first data module reaches a second node, the main processor writes the first data module into a second register, and the second register temporarily stores the first data module;
s070: the main processor identifies a first data module temporarily stored in the second register;
s080: the main processor deletes the corresponding first data module in the second RAM according to the identified first data module in the second register;
s090: when a second data module reaches a first node, the main processor deletes the first data module temporarily stored in the first register and writes the second data module into the first register, wherein the first register temporarily stores the second data module;
s100: the main processor identifying a second data module temporarily stored in the first register;
s110: and the main processor deletes the corresponding second data module in the first RAM according to the identified second data module in the first register.
In a preferred embodiment of the present invention, step S060 further includes:
s061: when a first data module reaches an Nth node, the main processor writes the first data module into an Nth register, and the Nth register temporarily stores the first data module;
s062: the main processor identifies a first data module temporarily stored in the nth register;
s063: and the main processor deletes the corresponding first data module in the Nth RAM according to the identified first data module in the Nth register.
As a preferred mode of the present invention, the step S090 further includes:
s091: when the Nth data module reaches the first node, the main processor deletes the N-1 th data module temporarily stored in the first register and writes the Nth data module into the first register, and the first register temporarily stores the Nth data module;
s092: the main processor identifies an Nth data module temporarily stored in the first register;
s093: and the main processor deletes the corresponding Nth data module in the first RAM according to the identified Nth data module in the first register.
As a preferred mode of the present invention, when a data transmission failure occurs, the main processor performs the following steps:
s120: the main processor judges the data transmission fault position;
s130: the main processor confirms that the fault position is between the Nth node and the (N + 1) th node;
s140: and the main processor controls the (N + 1) th RAM to start transmitting data.
As a preferable aspect of the present invention, the step S010 further includes:
s011: the main processor remotely mirrors the data module to a remote processor;
s012: the remote processor stores the data module to a remote database;
s013: and the remote processor deletes the corresponding data module stored in the remote database according to the data module in the first register identified by the main processor.
As a preferred mode of the present invention, when a data disaster occurs to the main processor, the method includes the following steps:
s014: the remote processor judges that the main processor has a data disaster;
s015: and the allopatric processor transmits the data in the allopatric database.
As a preferred aspect of the present invention, the data disaster recovery method further includes a server configuration preparation step, where the step includes:
s000: the server establishes relationship information among a main processor, each node, each RAM and each register;
s001: the server establishes the relationship information between the main processor and the remote processor;
s002: the server configures disaster tolerance information;
s003: and the server respectively establishes a data processing thread according to each disaster tolerance information.
The invention realizes the following beneficial effects:
1. the aim of efficiently dealing with data disasters is achieved by establishing a main processor, each node, each RAM and relationship information among registers, configuring disaster tolerance information and establishing a data processing thread;
2. the virtual transmission process of the RAM is carried out simultaneously in the data transmission process of the main processor, namely the main processor deletes the register and the corresponding data module which is finished by real-time transmission in the RAM so as to achieve the consistency of the virtual transmission and the real-time transmission on the part which is not transmitted and the consistency of time, when a data disaster occurs, the main processor can rapidly carry out data filling transmission, and the aim of improving the response efficiency of the main processor to the data disaster is achieved;
3. the synchronization of the real-time transmission and the virtual transmission can effectively reduce the delay problem of the main processor in dealing with disasters.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a diagram of the steps of a data transmission process of the present invention;
FIG. 2 is a system framework diagram of the present invention;
FIG. 3 is a diagram illustrating a step of the embodiment;
FIG. 4 is a diagram illustrating a step of the embodiment;
FIG. 5 is a diagram of host processor control steps for resolving data transfer failures;
FIG. 6 is a diagram of the steps for a data disaster resolution by a displaced processor;
fig. 7 is a step diagram of establishing a disaster tolerance framework by a server.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The first embodiment is as follows:
the reference figures are figures 1-5. A data disaster tolerance method comprises the following steps:
s010: the main processor divides data into a plurality of data modules, mirrors the data modules and stores the data modules in a plurality of RAMs;
s020: the main processor sends data according to the sequence of the data modules;
s030: when a first data module reaches a first node, the main processor writes the first data module into a first register, and the first register temporarily stores the first data module;
s040: the main processor identifying a first data module temporarily stored in the first register;
s050: the main processor deletes a corresponding first data module in the first RAM according to the identified first data module in the first register;
s060: when a first data module reaches a second node, the main processor writes the first data module into a second register, and the second register temporarily stores the first data module;
s070: the main processor identifies a first data module temporarily stored in the second register;
s080: the main processor deletes the corresponding first data module in the second RAM according to the identified first data module in the second register;
s090: when a second data module reaches a first node, the main processor deletes the first data module temporarily stored in the first register and writes the second data module into the first register, wherein the first register temporarily stores the second data module;
s100: the main processor identifying a second data module temporarily stored in the first register;
s110: and the main processor deletes the corresponding second data module in the first RAM according to the identified second data module in the first register.
Further, the step S060 further includes:
s061: when a first data module reaches an Nth node, the main processor writes the first data module into an Nth register, and the Nth register temporarily stores the first data module;
s062: the main processor identifies a first data module temporarily stored in the nth register;
s063: and the main processor deletes the corresponding first data module in the Nth RAM according to the identified first data module in the Nth register.
Further, the step S090 further includes:
s091: when the Nth data module reaches the first node, the main processor deletes the N-1 th data module temporarily stored in the first register and writes the Nth data module into the first register, and the first register temporarily stores the Nth data module;
s092: the main processor identifies an Nth data module temporarily stored in the first register;
s093: and the main processor deletes the corresponding Nth data module in the first RAM according to the identified Nth data module in the first register.
Further, when a data transmission failure occurs, the main processor performs the following steps:
s120: the main processor judges the data transmission fault position;
s130: the main processor confirms that the fault position is between the Nth node and the (N + 1) th node;
s140: and the main processor controls the (N + 1) th RAM to start transmitting data.
In a specific implementation process, when the host processor has a data transmission obstacle and the server determines that the transmission obstacle exists in the data transmission process, the host processor determines a node where the data transmission obstacle exists according to the register group, for example, when the host processor determines that a data module in a third register and a data module in a second register cannot be changed, it determines that a data disaster exists between the second node and a third node, and the host processor stops transmitting the data module and controls the third RAM to start replacing a data transmission module. For example, when the main processor transmits a data module, the third data module is stored in the third register, the second data module is stored in the second register, when the third data module is written in the fourth register, the second data module still stored in the second register is determined, it is determined that a transmission obstacle, i.e., a disaster, occurs between the second node and the third node in the data transmission system, the main processor stops transmitting the data module, controls the main third RAM to delete the third data module, and then controls the third RAM to perform data transmission instead.
It is worth mentioning that, when the main processor performs real-time data transmission, the main processor controls the RAM group to perform virtual data transmission, and the virtual data transmission deletes a transmitted data module, thereby ensuring that the data module at the corresponding node, the corresponding register and the data in the corresponding RAM are consistent, so as to ensure that a response can be made in time when a fault occurs, and improve the efficiency of data disaster tolerance.
Example two:
the reference figure is figure 6. For the first embodiment, the present embodiment is different in that:
further, the step S010 further includes:
s011: the main processor remotely mirrors the data module to a remote processor;
s012: the remote processor stores the data module to a remote database;
s013: and the remote processor deletes the corresponding data module stored in the remote database according to the data module in the first register identified by the main processor.
Further, when the main processor has a data disaster, the method comprises the following steps:
s014: the remote processor judges that the main processor has a data disaster;
s015: and the allopatric processor transmits the data in the allopatric database.
In a specific implementation process, after obtaining the mirror image data of the main processor, the remote processor stores the mirror image data into a remote database connected with the remote processor, when a data module is recorded in a first register connected with the main processor and the main processor identifies the data module in the first register, the main processor mirrors the identification information to the remote processor, and the remote processor deletes the corresponding data module according to the identification information.
It should be noted that the data modules in the identification information are continuous values, and if the data module is identified as the second data module for the first time and the data module is identified as the fourth data module for the second time, it is determined that a data disaster occurs, and the main processor stops transmitting data; and if the processor in the different place identifies the data module in the identification information as a second data module for a single time and identifies the data module as a fourth data module for a second time, the processor in the different place stops the information transmission of the main processor and replaces the main processor to perform data transmission. And the remote processor identifies a third data module according to the second data module identified at a single time, identifies the data module according to the data module temporarily written in the register group connected with the main processor, deletes the third data module in the remote database if the third data module is identified, and replaces the main processor to perform data transmission.
Example three:
the reference figure is figure 7. For the first embodiment, the present embodiment is different in that:
further, the data disaster recovery method further includes a server configuration preparation step, where the server configuration preparation step includes:
s000: the server establishes relationship information among a main processor, each node, each RAM and each register;
s001: the server establishes the relationship information between the main processor and the remote processor;
s002: the server configures disaster tolerance information;
s003: and the server respectively establishes a data processing thread according to each disaster tolerance information.
In a specific implementation process, the server establishes a data disaster recovery system for the data disaster recovery method, and the data disaster recovery system comprises a main processor, n RAMs, n nodes and n registers, and configures node information, main processor information, RAM information and register information, and establishes one or more connection threads for the information, wherein the threads are data processing threads, and the server records the connection information, the configuration information and the like after completing registration.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (7)
1. A method for data disaster recovery is characterized in that: the method comprises the following steps:
s010: the main processor divides data into a plurality of data modules, mirrors the data modules and stores the data modules in a plurality of RAMs;
s020: the main processor sends data according to the sequence of the data modules;
s030: when a first data module reaches a first node, the main processor writes the first data module into a first register, and the first register temporarily stores the first data module;
s040: the main processor identifying a first data module temporarily stored in the first register;
s050: the main processor deletes a corresponding first data module in the first RAM according to the identified first data module in the first register;
s060: when a first data module reaches a second node, the main processor writes the first data module into a second register, and the second register temporarily stores the first data module;
s070: the main processor identifies a first data module temporarily stored in the second register;
s080: the main processor deletes the corresponding first data module in the second RAM according to the identified first data module in the second register;
s090: when a second data module reaches a first node, the main processor deletes the first data module temporarily stored in the first register and writes the second data module into the first register, wherein the first register temporarily stores the second data module;
s100: the main processor identifying a second data module temporarily stored in the first register;
s110: and the main processor deletes the corresponding second data module in the first RAM according to the identified second data module in the first register.
2. The method according to claim 1, wherein: the step S060 further includes:
s061: when a first data module reaches an Nth node, the main processor writes the first data module into an Nth register, and the Nth register temporarily stores the first data module;
s062: the main processor identifies a first data module temporarily stored in the nth register;
s063: and the main processor deletes the corresponding first data module in the Nth RAM according to the identified first data module in the Nth register.
3. A method of data disaster recovery as claimed in claim 2, wherein: the step S090 further includes:
s091: when the Nth data module reaches the first node, the main processor deletes the N-1 th data module temporarily stored in the first register and writes the Nth data module into the first register, and the first register temporarily stores the Nth data module;
s092: the main processor identifies an Nth data module temporarily stored in the first register;
s093: and the main processor deletes the corresponding Nth data module in the first RAM according to the identified Nth data module in the first register.
4. A method as claimed in claim 3, wherein: when a data transmission failure occurs, the main processor performs the following steps:
s120: the main processor judges the data transmission fault position;
s130: the main processor confirms that the fault position is between the Nth node and the (N + 1) th node;
s140: and the main processor controls the (N + 1) th RAM to start transmitting data.
5. The method according to claim 1, wherein: the step S010 further includes:
s011: the main processor remotely mirrors the data module to a remote processor;
s012: the remote processor stores the data module to a remote database;
s013: and the remote processor deletes the corresponding data module stored in the remote database according to the data module in the first register identified by the main processor.
6. The method according to claim 5, wherein: when the main processor has data disaster, the method comprises the following steps:
s014: the remote processor judges that the main processor has a data disaster;
s015: and the allopatric processor transmits the data in the allopatric database.
7. The method according to claim 1, wherein: further comprising a server configuration preparation step, said steps being as follows:
s000: the server establishes relationship information among a main processor, each node, each RAM and each register;
s001: the server establishes the relationship information between the main processor and the remote processor;
s002: the server configures disaster tolerance information;
s003: and the server respectively establishes a data processing thread according to each disaster tolerance information.
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