CN108494234B - Floating power rail suitable for GaN high-speed gate drive circuit - Google Patents

适用于GaN高速栅驱动电路的浮动电源轨，属于电源管理技术领域。本发明采用双浮动电源轨的设计，能够实现同时满足GaN功率开关器件在安全电压内工作和低压转高压电平位移电路拥有足够的动态范围的浮动电源轨；高压转低压电平位移电路、电压钳位电路、逻辑控制电路和第一浮动电源轨产生电路构成闭环，用于产生第一电源轨BST作为GaN高速栅驱动电路中的缓冲电路的电源轨，能够保护GaN功率开关器件栅源电压工作在安全范围内；第二浮动电源轨产生电路构成开环，用于产生第二电源轨BSTA作为GaN高速栅驱动电路中的低压转高压电平位移电路的电源轨，能够保证其具有足够的动态范围。

A floating power rail suitable for a GaN high-speed gate drive circuit belongs to the technical field of power management. The invention adopts the design of double floating power supply rails, and can realize the floating power supply rails that simultaneously satisfy the GaN power switch device working within the safe voltage and the low voltage to high voltage level shift circuit with sufficient dynamic range; the high voltage to low voltage level shift circuit, The voltage clamping circuit, the logic control circuit and the first floating power rail generating circuit form a closed loop, and are used to generate the first power rail BST as the power rail of the buffer circuit in the GaN high-speed gate driving circuit, which can protect the gate-source voltage of the GaN power switching device Work within a safe range; the second floating power rail generation circuit forms an open loop, which is used to generate the second power rail BSTA as the power rail of the low-voltage to high-voltage level shift circuit in the GaN high-speed gate drive circuit, which can ensure that it has sufficient dynamic range.

Floating power rail suitable for GaN high-speed gate drive circuit

Technical Field

The invention belongs to the technical field of power management, and particularly relates to a floating power rail suitable for a GaN high-speed gate drive circuit.

Background

With the development of power electronics in recent years, the half-bridge driving circuit is moving towards high power and high frequency, which also brings new requirements to the selection of power tubes and the design of circuits. In contrast, because a GaN power switching device (such as a GaN HEMT) has good physical properties of high voltage resistance, no reverse recovery time and the like, a half-bridge gate driving circuit adopting the GaN power switching device has excellent properties of high speed, high power density and the like. However, when the enhancement-mode GaN power switching device (hereinafter, GaN HEMT is taken as an example) is used as the power transistor of the half-bridge gate driving circuit, the following phenomena occur, so that the conventional high-speed high-power gate driving circuit suitable for the Si power transistor cannot be used for the enhancement-mode GaN power switching device.

FIG. 1 is a schematic diagram of an enhancement-mode GaN power switch device applied to a half-bridge gate driver, wherein ① represents the existence of a power stage bias voltage V due to the pumping of an external load_SWIn the negative case, ② shows that the bootstrap capacitor C should be added to the circuit due to the low gate-source voltage of the enhancement-type GaN power switch device_bootUpper and lower polar plate differential pressure V_BST-V_SWThe clamp is in the safe operating range, ③ in the figure indicates the capacitor C due to bootstrap_bootUpper and lower polar plate differential pressure V_BST-V_SWClamped, BST voltage due to C in dead time_bootThe capacitive coupling effect is reduced along with the negative pressure of SW, which results in insufficient dynamic range of the low-voltage to high-voltage Level shift circuit (Level Up), wherein ④ shows that the power rails of the low-voltage to high-voltage Level shift circuit (Level Up) are BST and VSS, and the amplitude V of the driving signal after the Level shift is passed in the dead time_BST-V_SS＝V_Cboot-|V_SWWill be due to the difference of pressure V between the upper and lower polar plates of Cboot_CbootClamped, SW goes into negative pressure and decreases; the above 4 cases will lead to two consequences: first, the dynamic range of the low-to-high voltage Level shift circuit (Level Up) is not enough, so that the speed of Level shift becomes slow, and the requirement of high-speed gate drive on transmission delay is no longer met, taking the low-to-high voltage Level shift circuit (Level Up) in fig. 2 as an example, the floating power supply rail voltage V is_BSTThe reduction of the voltage causes the grid-source voltage V of the power tubes M1 and M2 in the low-voltage to high-voltage level shift circuit_GSWhen the voltage level shift circuit is small, the pull-up and pull-down capacity of the low-voltage to high-voltage level shift circuit to the output node is weakened, so that the speed of level shift is reduced; secondly, the power supply rails of the subsequent logic circuit of the low-voltage to high-voltage Level shift circuit (Level Up) are BST and SW, and the power supply of the low-voltage to high-voltage Level shift circuit (Level Up) isBST and VSS are different reference ground, and the amplitude V of the driving signal after level shift_BST-V_SS＝V_Cboot-|V_SWAfter the negative pressure is reduced along with the SW entering, the threshold level V of the post-stage logic can not be touched gradually_TEventually, a problem of loss of the driving signal occurs.

In the off state, the GaN HEMT (GaN high electron mobility transistor) in fig. 1 has a drain-source voltage V when a current flows from a source terminal to a drain terminal_DSNegative voltage of-2V to-3V exists, so that when the GaN HEMT is used as a lower power tube in a half-bridge gate driving circuit, due to the load pumping of an external load, a power level bias voltage V exists in dead time_SWThe negative condition is achieved, and the higher the load current is, the more serious the negative condition is; in conventional designs of bootstrap capacitor power modules, the floating supply rail BST is formed from the low voltage supply rail V_DDSupply power, which results in a bootstrap capacitance C during the dead time_bootWhile charging, bootstrap capacitor C_bootThe upper plate is clamped at V by a bootstrap diode_DDThe potential, the voltage difference across the capacitor can be up to (V)_DD+3) V; however, the GaN HEMT has a small gate-source breakdown voltage (V is required)_GS<6V, the optimal driving voltage does not exceed 5.5V), the upper power tube is easy to break down due to overlarge voltage difference between two ends of the bootstrap capacitor when being opened.

Therefore, in some bridge driver circuit designs, a clamping bootstrap capacitor C needs to be added to the bootstrap capacitor charging path_bootVoltage difference V between upper and lower plates_BST-V_SWThe clamping circuit can avoid the breakdown of the GaN tube dielectric layer caused by the overlarge grid-source voltage of the upper power tube. But because of bootstrap capacitance C_bootVoltage difference V between upper and lower plates_BST-V_SWIs clamped within 5.5V to ensure safe operation, and the power level bias voltage V in dead time_SWLarge negative value, the bootstrap capacitance C_bootThe coupling effect of the floating supply rail BST level follows the power stage bias voltage V_SWEntering the negative pressure and well below 5V brings new problems: 1. the dynamic range of a low-voltage to high-voltage Level shift circuit (Level Up) which is bridged between a power tube control circuit and a low-voltage logic circuit is insufficient (low-voltage to high-voltage power)The power supply rails of the Level shift circuit are generally a floating power supply rail BST and a chip ground), so that the response speed of the low-voltage to high-voltage Level shift circuit (Level Up) does not meet the high-speed requirement, and the transmission delay of a driving signal is increased; 2. the threshold Level of the post-stage logic circuit is reduced along with the synchronous reduction of the potentials of the floating power rail BST and the low-voltage power rail SW in the dead time, and meanwhile, the amplitude of a driving signal after Level shift is reduced due to the reduction of the dynamic range of a low-voltage to high-voltage Level shift circuit (Level Up), so that the two phenomena can cause that an input signal is not identified by the post-stage logic circuit during transmission and the signal is lost. The above problems bring a difficult problem to the design of a high-speed high-power half-bridge gate driving circuit suitable for a GaN power switch device, so that it is difficult to realize a floating power rail which can simultaneously meet the requirements that the GaN power switch device works in a safe voltage and a low-voltage to high-voltage Level shift circuit (Level Up) has a sufficient dynamic range.

Disclosure of Invention

Aiming at the defects, the invention provides a floating power rail suitable for a GaN high-speed high-power half-bridge gate driving circuit, and a bootstrap capacitor C is ensured_bootOn the premise that the voltage difference of the upper and lower polar plates is clamped in a safe voltage, the GaN half-bridge gate driving circuit is powered by the double-floating power supply rail generating circuit, so that the negative problems that the dielectric layer of the upper power tube can be broken down and the transmission delay of the driving signal is increased or even lost due to the fact that the traditional grid driving floating power supply rail generating circuit suitable for the Si power tube is applied to a GaN power switch device are solved.

The technical scheme of the invention is as follows:

the floating power supply rail suitable for the GaN high-speed gate drive circuit comprises a high-voltage to low-voltage level shift circuit, a voltage clamping circuit, a logic control circuit, a first floating power supply rail generating circuit and a second floating power supply rail generating circuit,

the second floating power rail generating circuit includes a first diode D₁A second diode D₂And a bootstrap capacitor C_bootFirst diode D₁Anode of (2) is connected to a power supply voltage V_DDThe cathode of the first diode is connected with a second diode D₂Of a cathodeAnd generating a second floating supply rail BSTA; bootstrap capacitor C_bootThe upper polar plate of the first diode is connected with a second diode D₂The anode of the GaN high-speed gate driving circuit and the output end of the first floating power supply rail generating circuit, and the lower polar plate of the GaN high-speed gate driving circuit is connected with a half-bridge switch node SW of the GaN high-speed gate driving circuit;

two input ends of the voltage clamping circuit are respectively connected with the bootstrap capacitor C_bootUpper and lower plates for detecting the bootstrap capacitor C_bootAnd outputs a first control signal Ctrl1 to the input terminal of the high-to-low voltage level shift circuit;

the high-voltage to low-voltage level shift circuit converts the first control signal Ctrl1 to a low-voltage power supply rail, outputs a first logic control signal LV1 and a second logic control signal LV2 and is connected with two input ends of the logic control circuit;

the logic control circuit generates a second control signal Ctrl2 according to the first logic control signal LV1 and a second logic control signal LV2 and is connected to an input terminal of the first floating power rail generation circuit;

the first floating power rail generation circuit is used to generate a first floating power rail BST.

Specifically, the GaN high-speed gate driving circuit includes a buffer circuit and a low-to-high voltage level shift circuit, the power rails of the buffer circuit are a first floating power rail BST and a half-bridge switch node power rail SW, and the power rails of the low-to-high voltage level shift circuit are a second floating power rail BSTA and a half-bridge switch node power rail SW.

Specifically, the first floating power rail generation circuit comprises a low-voltage switch tube PM0 and a bootstrap diode D_BOOTA first resistor R1, an NPN type triode, a Zener tube and a second resistor R2,

the grid of the low-voltage switch tube PM0 is used as the input end of the first floating power supply rail generation circuit to be connected with the second control signal Ctrl2, the source of the low-voltage switch tube PM0 is connected with one end of a first resistor R1, the collector of an NPN type triode and the cathode of a Zener tube and is connected with a power supply voltage VDD, the drain of the low-voltage switch tube PM0 is connected with the other end of the first resistor R1 and NPEmitter of N-type triode and bootstrap diode D_BOOTThe anode of (1);

the base electrode of the NPN type triode is connected with the anode of the Zener diode and is connected with a bootstrap diode D after passing through a second resistor R2_BOOTAnode of (2), bootstrap diode D_BOOTAs an output of the first floating supply rail generation circuit, outputs a first floating supply rail BST.

Specifically, the logic control circuit comprises a latch protection module, an RS latch module and a buffer,

Specifically, the voltage clamp circuit includes a seventh inverter INV7, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first triode Q1, a second triode Q2, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a seventh NMOS tube NM7, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, and a fourth PMOS tube PM 4;

the input end of the seventh inverter INV7 is connected to the gates of the fourth PMOS transistor PM4, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 and the drains of the third PMOS transistor PM3 and the fourth NMOS transistor NM4, and the output end thereof is connected to the gate of the first PMOS transistor PM 1;

the grid electrode of the first NMOS tube NM1 is connected with the grid electrode and the drain electrode of the second NMOS tube NM2 and the collector electrode of the first triode Q1, the drain electrode of the first NMOS tube NM1 is connected with the grid electrode and the drain electrode of the second PMOS tube PM2 and the grid electrode of the third PMOS tube PM3, the source electrode of the first NMOS tube NM1 is connected with the source electrodes of the second NMOS tube NM2, the third NMOS tube NM3, the fourth NMOS tube NM4 and the sixth NMOS tube NM6, and the first input end of the voltage clamping circuit is connected with the voltage V at the half-bridge switch node of the GaN_SW；

The third resistor R3 is connected between the source and the drain of the first PMOS pipe PM1, the fourth resistor R4 and the fifth resistor R5 are connected in series and in parallel between the drain of the first PMOS pipe PM1 and the source of the first NMOS pipe NM1, and the series point of the fourth resistor R4 and the fifth resistor R5 is connected with the base electrodes of the first triode Q1 and the second triode Q2;

the sixth resistor R6 and the seventh resistor R7 are connected in series between the source of the first PMOS transistor PM1 and the emitter of the first triode Q1, and the series point of the sixth resistor R6 and the seventh resistor R7 is connected with the emitter of the second triode Q2;

the gate-drain short circuit of the third NMOS transistor NM3 is connected to the collector of the second triode Q2 and the gate of the fourth NMOS transistor NM 4;

the grid electrode of the seventh NMOS transistor NM7 is connected with the drain electrodes of the fourth PMOS transistor PM4 and the fifth NMOS transistor NM5 and serves as the output end of the voltage clamping circuit, the source electrode of the seventh NMOS transistor NM7 is connected with the source electrode of the fifth NMOS transistor NM5 and the drain electrode of the sixth NMOS transistor NM6, the drain electrode of the seventh NMOS transistor NM7 is connected with the source electrodes of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 and serves as the second input end of the voltage clamping circuit and is connected with the voltage V of the first floating power supply rail_BST。

Specifically, the high-voltage to low-voltage level shift circuit comprises an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10, an eleventh NMOS tube NM11, a twelfth NMOS tube NH1, a thirteenth NMOS tube NH2, a fifth PMOS tube PM5, a sixth PMOS tube PM6, a seventh PMOS tube PM7, an eighth PMOS tube PM8, a ninth PMOS tube PH1, a tenth PMOS tube PH2, a third triode Q3 and a fourth triode Q4, and power supply rails of the high-voltage to low-voltage level shift circuit are a second floating half-bridge power supply rail BSTA and a switch node power supply rail SW;

the grid electrode of an eighth NMOS tube NM8 is connected with the input end of an eighth inverter INV8 and serves as the input end of the high-voltage to low-voltage level shift circuit, the drain electrode of the eighth NMOS tube NM8 is connected with the drain electrode of a fifth PMOS tube PM5 and the grid electrode of a sixth PMOS tube PM6, and the source electrode of the eighth NMOS tube NM8 is connected with the source electrode of a ninth NMOS tube NM9 and the voltage V at the half-bridge switching node of the GaN high-speed gate_SW；

The gate of the ninth NMOS transistor NM9 is connected to the output terminal of the eighth inverter INV8, and the drain thereof is connected to the gate of the fifth PMOS transistor PM5, the drain of the sixth PMOS transistor PM6 and the input terminal of the ninth inverter INV 9;

the gate of the seventh PMOS transistor PM7 is connected to the output terminal of the ninth inverter INV9 and the input terminal of the tenth inverter INV10, the drain thereof is connected to the source of the ninth PMOS transistor PH1, the source thereof is connected to the sources of the fifth, sixth and eighth PMOS transistors PM5, PM6 and PM8, and is connected to the voltage V of the second floating power rail_BSTA；

the gate of the ninth PMOS transistor PH1 is connected to the gate of the tenth PMOS transistor PH2, and the drain thereof is connected to the drain of the twelfth NMOS transistor NH 1;

The emitter of the third triode Q3 is connected with the power supply voltage V_DDA base and a collector of the NMOS transistor NH1 are connected to a source of the tenth NMOS transistor NM10, a drain of the tenth NMOS transistor NM10, and a gate of the eleventh NMOS transistor NM11, and output the first logic control signal LV 1; sources of the tenth and eleventh NMOS transistors NM10 and NM11 are grounded.

The invention has the beneficial effects that: the power rail provided by the invention adopts the design of double floating power rails, so that the floating power rail which can simultaneously meet the requirements that a GaN power switch device works in a safe voltage and a low-voltage-to-high-voltage level shift circuit has a sufficient dynamic range can be realized; the generated first floating power supply rail BST clamped and protected by the voltage difference of the bootstrap capacitor Cboot is used as a power supply rail of a buffer circuit in the GaN high-speed gate driving circuit, and the grid source voltage of the GaN power switch device can be protected to work in a safe range; resulting in a capacitor C which is not bootstrapped_bootThe second floating power supply rail BSTA of the voltage difference clamping protection is used as a power supply rail of a low-voltage-to-high-voltage level shift circuit in the GaN high-speed gate driving circuit, and can ensure that the power supply rail has a sufficient dynamic range.

Drawings

Fig. 1 is a schematic structural diagram of an enhancement-mode GaN power switch device applied to a half-bridge gate driver in the prior art.

Fig. 2 is a schematic diagram of a floating power rail for a GaN high-speed gate driver circuit according to an embodiment.

Fig. 3 is a specific implementation manner of the voltage clamp circuit and the Level shift circuit Level Down for converting high voltage to low voltage in the embodiment.

Fig. 4 is a typical application topology building method of the invention applied to a high-speed gate drive IC in the embodiment.

Detailed Description

The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and specific embodiments:

the floating power supply rail suitable for the GaN high-speed gate driving circuit adopts the design of double floating power supply rails, and a high-voltage to low-voltage level shift circuit, a voltage clamping circuit, a logic control circuit and a first floating power supply rail generating circuit form a closed loop and are used for generating a first power supply rail BST; two floating power rail generation circuits form an open loop for generating a second power rail BSTA.

The power supply rails of a buffer circuit in the GaN high-speed gate driving circuit are a first floating power supply rail BST and a half-bridge switch node power supply rail SW which are clamped and protected by the voltage difference of a bootstrap capacitor Cboot, and the gate-source voltage of a GaN power switch device can be protected to work in a safe range; the power rail of the low-voltage to high-voltage level shift circuit is a bootstrap capacitor C_bootThe voltage difference clamp protected second floating supply rail BSTA and the half-bridge switch node supply rail SW can guarantee that they have sufficient dynamic range.

As shown in fig. 2, an implementation manner of the first floating power rail generation circuit and the logic control circuit is shown, the first floating power rail generation circuit has an active clamping protection function and an initial power-on function, and includes a low voltage switch tube PM0, a bootstrap diode D_BOOTThe device comprises a first resistor R1, an NPN type triode, a Zener of a Zener tube and a second resistor R2, wherein the first resistor R1 is an initialization unit, and the NPN type triode, the Zener of the Zener tube and the second resistor R2 form an active clamping unit; the grid of the low-voltage switching tube PM0 is used as the input end of the first floating power supply rail generation circuit to be connected with the second control signal Ctrl2, the source of the low-voltage switching tube PM0 is connected with one end of a first resistor R1, the collector of an NPN type triode and the cathode of a Zener tube and is connected with a power supply voltage V_DDThe drain of the resistor is connected with the other end of the first resistor R1, the emitter of the NPN type triode and the bootstrap diode D_BOOTThe anode of (1); the base electrode of the NPN type triode is connected with the anode of the Zener diode and is connected with a bootstrap diode D after passing through a second resistor R2_BOOTAnode of (2), bootstrap diode D_BOOTAs an output of the first floating supply rail generation circuit, outputs a first floating supply rail BST.

As shown in fig. 3, the voltage clamp circuit includes a seventh inverter INV7, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first triode Q1, a second triode Q2, a first NMOS NM1, a second NMOS NM2, a third NMOS NM3, a fourth NMOS NM4, a fifth NMOS NM5, a sixth NMOS NM6, a seventh NMOS NM7, a first PMOS PM1, a second PM2, a third PMOS PM3, and a fourth PMOS PM 4; the input end of the seventh inverter INV7 is connected to the gates of the fourth PMOS transistor PM4, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 and the drains of the third PMOS transistor PM3 and the fourth NMOS transistor NM4, and the output end thereof is connected to the gate of the first PMOS transistor PM 1; the grid electrode of the first NMOS tube NM1 is connected with the grid electrode and the drain electrode of the second NMOS tube NM2 and the collector electrode of the first triode Q1, the drain electrode is connected with the grid electrode and the drain electrode of the second PMOS tube PM2 and the grid electrode of the third PMOS tube PM3, and the source electrode is connected with the fourth NMOS tubeThe source electrodes of the two NMOS tubes NM2, the third NMOS tube NM3, the fourth NMOS tube NM4 and the sixth NMOS tube NM6 are used as the first input end of the voltage clamping circuit to be connected with the voltage V at the half-bridge switching node of the GaN high-speed gate driving circuit_SW(ii) a The third resistor R3 is connected between the source and the drain of the first PMOS pipe PM1, the fourth resistor R4 and the fifth resistor R5 are connected in series and in parallel between the drain of the first PMOS pipe PM1 and the source of the first NMOS pipe NM1, and the series point of the fourth resistor R4 and the fifth resistor R5 is connected with the base electrodes of the first triode Q1 and the second triode Q2; the sixth resistor R6 and the seventh resistor R7 are connected in series between the source of the first PMOS transistor PM1 and the emitter of the first triode Q1, and the series point of the sixth resistor R6 and the seventh resistor R7 is connected with the emitter of the second triode Q2; the gate-drain short circuit of the third NMOS transistor NM3 is connected to the collector of the second triode Q2 and the gate of the fourth NMOS transistor NM 4; the grid electrode of the seventh NMOS transistor NM7 is connected with the drain electrodes of the fourth PMOS transistor PM4 and the fifth NMOS transistor NM5 and serves as the output end of the voltage clamping circuit, the source electrode of the seventh NMOS transistor NM7 is connected with the source electrode of the fifth NMOS transistor NM5 and the drain electrode of the sixth NMOS transistor NM6, the drain electrode of the seventh NMOS transistor NM7 is connected with the source electrodes of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 and serves as the second input end of the voltage clamping circuit and is connected with the voltage V of the first floating power supply rail_BST。

The voltage clamping circuit mainly comprises a band gap reference circuit and a current comparator. The first triode Q1 and the second triode Q2 form a reference core, and a bootstrap capacitor C is acquired through a divider resistor formed by a third resistor R3, a fourth resistor R4 and a fifth resistor R5_bootThe level of the voltage information of the upper and lower electrode plates BST-SW is inputted into the base regions of the first triode Q1 and the second triode Q2, and because the transconductance of the circuit where the first triode Q1 and the second triode Q2 are located is different, the current of the reference core mirrored to the current comparator through the first triode Q1 and the second triode Q2 is different, the voltage difference of the BST-SW is different, and the first control signal Ctrl1 outputted by the voltage clamping circuit is high or low.

The working principle of the generation of the first power rail BST is: the voltage clamp circuit is used for the bootstrap capacitor C_bootVoltage difference V between upper and lower plates_BST-V_SWPerforming real-time voltage detection and generating a first control signal Ctrl1, a high-voltage to low-voltage Level shift circuit (Level Down) converting the first control signal Ctrl1 to a low-voltage power rail for logic control, generating a first logic control signal LV1 and a second logic control signal LV2 to be input into a logic control circuit, and the logic control circuit generating a second control signal Ctrl2 to control a bootstrap diode D in a first floating power rail generation circuit_BOOTPositive end to low voltage power rail V_DDWith the low voltage switching tube PM0 in between.

When the bootstrap capacitor C is detected_bootAt undervoltage, the supply voltage V_DDBy means of a bootstrap diode D_BOOTTo bootstrap capacitor C_bootCharging; when the bootstrap capacitor C is detected_bootWhen the voltage on the power supply is over-voltage, the power supply voltage V is cut off_DDTo a bootstrap capacitor C_bootThe charging path of (a). The first control signal Ctrl1 output by the voltage clamping circuit is converted to a low-voltage power rail through a high-voltage to low-voltage level shift circuit (LevelDown), and a second control signal Ctrl2 is output to control the logic control circuit. The truth table of the logic control circuit is as follows, where a denotes the input signal of the first inverter INV1, B denotes the input signal of the second inverter INV2, Set denotes the output signal of the first NAND gate NAND1, Reset denotes the output signal of the second NAND gate NAND2, and Q denotes the output signal of the third NAND gate NAND 3:

the logic design can ensure that the RS latch module in the logic control circuit can still normally work under the influence of common-mode noise of the SW node.

At the bootstrap diode D_BOOTPositive terminal and V_DDA low-voltage switch tube PM0 is inserted between power supply biases, and when the voltage clamping circuit detects the bootstrap capacitor C_bootWhen the voltage difference BST-SW between the upper polar plate and the lower polar plate is over-voltage, a first control signal Ctrl1 is output and is converted to a low-voltage rail through a high-voltage to low-voltage Level shift circuit (Level Down) to be used as the input of a logic control circuit; the output signal of the logic control circuit is controlled by a first control signal Ctrl1The second control signal Ctrl2 is generated to quickly turn off the low-voltage switch tube PM0 to realize the supply voltage V_DDTo a bootstrap capacitor C_bootThe disconnection of the charging path of (1); the front stage circuit detects the bootstrap capacitor C_bootWhen the voltage difference BST-SW between the upper and lower polar plates is under-voltage, the logic control circuit outputs a second control signal Ctrl2 to turn on the low-voltage switch tube PM0, and the charging path is equivalent to a bootstrap diode D_BOOTAnd a bootstrap capacitor C_bootWhen the upper tube of the GaN high-speed gate drive circuit is turned off, the voltage of the half-bridge switch node SW is reduced to the ground potential VSS or below, the charging branch is turned on to start to supply the bootstrap capacitor C_bootAnd (6) charging.

The above working process realizes the bootstrap capacitor C_bootDetection of two-terminal level and bootstrap capacitor C_bootA controlled charging process. However, due to the connection of the low-voltage switch tube PM0, when the low-voltage switch tube PM0 is turned off, the body diode and the bootstrap diode D thereof_BOOTForming a pair of back-to-back diodes, such that V_ANode (i.e. bootstrap diode D)_BOOTAnode) becomes a high resistance node, which causes: 1. when the whole driving chip is powered on, the bootstrap capacitor C_bootTo the supply voltage V_DDThe power supply circuit is a high-resistance path and cannot be normally powered on; 2. after the whole driving chip works normally, the upper power tube is quickly turned on and off, dv/dt common-mode noise crosstalk of the first floating power rail BST is severe, and a high-resistance node V_AThe circuit is easy to be interfered and the normal work of the circuit is influenced. Therefore, in the first floating power rail generation circuit, the bootstrap capacitor C is connected by the large resistor R1_bootInitialization can be carried out to enable the BST-SW to reach the working voltage; the Zener of the Zener tube, the second resistor R2 and the NPN triode form an active clamping circuit for supplying V_ANode charging, the body diode of the low-voltage switch tube PM0 forms an active leakage path for V_ADischarging the node to cancel the dv/dt common mode noise pair V of the first floating supply rail BST_ACrosstalk of node voltages.

In the first floating power rail generation circuit, the active clamp circuit operates according to the following principle: when the level at the first floating supply rail BST drops rapidly, V_ANodes are crosstalked to be very low by negative dv/dtVoltage, Zenar reverse breakdown of Zenar, the voltage drop produced makes base and collector of NPN triode reverse bias; meanwhile, the current flowing through the second resistor R2 enables a voltage drop to BE generated between the base region and the emitter region of the NPN triode, the BE junction is forward biased, and the base region of the NPN triode is conducted; at this time, the active clamp path is turned on, and

in the above formula, k is boltzmann constant, T is ambient temperature, kT is 26mV at room temperature, β is amplification factor of NPN triode, I_ZenarAnd I_R2Is the current flowing through the Zenar and the second resistor R2 (I)_Zenar-I_R2) Representing the current flowing into the base of an NPN transistor, I_EFor NPN triode collector current, V is aligned when active clamp circuit is turned on_ACharging the node to cancel the dv/dt common mode noise pair V of the first floating supply rail BST_ACrosstalk of node voltages.

FIG. 1 is a schematic diagram of a second floating power rail generation circuit for high-speed reliable transmission of driving signals according to the present invention, including a first diode D1, a second diode D2, and a bootstrap capacitor C_bootThe anode of the first diode D1 is connected to a supply voltage V_DDA cathode of which is connected to a cathode of a second diode D2 and generates a second floating supply rail BSTA; the upper plate of the bootstrap capacitor is connected to the anode of the second diode D2 and the output terminal of the first floating power rail generation circuit, and the lower plate thereof is connected to the half-bridge switching node SW of the GaN high-speed gate driving circuit.

In the upper tube starting stage, the second diode D2 is conducted in the forward direction, the first diode D1 is turned off, and at this time

V_BST-V_D2＝V_BSTA

Wherein V_D2Is the forward voltage drop of the second diode D2 when conducting.

In the dead time when the upper tube is turned off and the lower tube is turned on, since the level of the first power rail BST is reduced to 2V at the lowest, the second diode D2 is turned off, the first diode D1 is turned on, and the second floating power rail BSTA is generatedThe potential being derived from the supply voltage V_DDProvide for

V_BSTA＝VDD-V_D1

Wherein V_D1Is the forward voltage drop of the first diode D1 when it is conducting.

The preferred implementation of the first diode D1 and the second diode D2 is: d1 is a high-voltage diode, and voltage resistance of Vin + VDD needs to be ensured from the negative end to the positive end of the diode during bootstrap; d2 is a low-voltage diode whose voltage resistance from negative terminal to positive terminal does not exceed the negative voltage value | V of SW_SWHowever, the negative end and the positive end of the voltage-withstanding circuit are opposite to the substrate, and the voltage withstanding of the Vin + VDD is required to be guaranteed, so that the chip area is saved most, the parasitic parameter is minimum, and the circuit is fastest correspondingly.

Fig. 4 is a typical topology set-up of the present invention applied to a GaN high-speed gate driver IC. The voltage clamping circuit, the high-voltage to low-voltage Level shift circuit (Level Down), the logic control circuit and the first floating power supply rail generating circuit jointly realize the functions of bootstrap charging and power supply for the gate driving circuit. Aiming at the problem that the potential at the BST of the first floating power supply rail is reduced to a low Level due to the occurrence of a source-drain negative voltage phenomenon of a GaN power switch device in dead time, the invention designs a power supply rail with a Level range from BSTA to SW to supply power to a low-voltage to high-voltage Level shift circuit (Level Up) in a half-bridge grid driving circuit.

The invention designs a power supply scheme of double floating power rails aiming at the physical characteristics of an enhanced GaN power switch device, and eliminates the negative influence of the enhanced GaN power switch device on the operation of a half-bridge gate drive circuit under high-speed and high-power application. It should be noted that the system control method and specific circuit design used in the present invention can also be applied to the driving circuit of Si power switch device and other wide bandgap semiconductor switch device (such as SiC power switch device), specifically, for the gate driving circuit of Si power switch device, the diode of lower power tube body will follow current in the dead time, and the voltage of SW node will drop to negative voltage of-0.7V in the dead time, and the present invention is also applicable to this application.

Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.