CN108562829B - Two-side clock synchronous monitoring method of line protection and double-end traveling wave distance measurement integrated device - Google Patents

The invention discloses a two-side clock synchronization monitoring method of a line protection and double-end traveling wave ranging integrated device, which comprises the following steps: step 1: the host calculates the channel delay; step 2: the slave computer adjusts the sampling time according to the sampling time of the host computer; and step 3: the host calculates clock deviations on two sides of the circuit; and 4, step 4: and the host judges whether the clocks on the two sides are synchronous according to the clock deviation on the two sides. The invention can realize the synchronization of the sampling time at two sides of the double-end traveling wave distance measurement, monitor the clock deviation at two sides in real time, ensure the consistency of the clocks at two sides and improve the reliability of the double-end traveling wave distance measurement.

Two-side clock synchronous monitoring method of line protection and double-end traveling wave distance measurement integrated device

Technical Field

The invention relates to a two-side clock synchronous monitoring method of a line protection and double-end traveling wave ranging integrated device.

Background

The travelling wave distance measurement method is a novel method for fault distance measurement by using current or voltage travelling waves, can effectively overcome the defects of an impedance method, and has the unique advantages of no influence of transition resistance, no influence of CT saturation, no influence of system oscillation, no influence of long-line distributed capacitance and the like, so that the travelling wave distance measurement method is widely applied to an electric power system.

The double-end traveling wave ranging algorithm calculates the distance between a fault point and two measuring points by using the difference of absolute time when an initial traveling wave generated by a fault inside the line reaches the measuring points at the two ends of the line, and when the external time ticks of devices at the two sides of the line deviate, an error ranging result can appear, and a negative effect is brought to the positioning analysis of the fault point.

A method for measuring the distance between two end travelling waves based on fuzzy matching is disclosed in the patent with application number CN201610333220.5, which is applied for 2016, 19 and 5.A time difference sequence Delta T is obtained by detecting and calibrating the arrival time of travelling wave of fault travelling wave by wavelet transform according to the travelling wave data of current at both sides of line when single-phase earth fault occurs in AC line_mAnd Δ T_n(ii) a Secondly, for Δ T_mAnd Δ T_nNormalizing and solving the distance between the two; then, solving the membership degree and determining a pair of most matched moments; and finally, calculating the fault distance and the asynchronous time delta t according to the most matched pair of moments. The mathematical treatment process is complex and is not suitable for practical engineering application.

The patent with application date of 2017, 10 and 20 and application number of 201710981512.4 discloses a real-time monitoring method for two-side external clocks, wherein the circuit protection function calculates channel delay in real time and completes synchronization of the internal clocks at two sides; the double-end traveling wave ranging function shares the internal clock and channel delay information of the line protection function, and real-time monitoring of external clocks at two sides is achieved. However, when the invention realizes the monitoring of the external clocks at two sides, whether the internal clocks at two sides are synchronized is not judged. If the internal clocks at the two sides are not synchronous, the error of the calculated deviation of the external clocks at the two sides is large.

Disclosure of Invention

Aiming at the problems, the invention provides a two-side clock synchronization monitoring method of a line protection and two-end traveling wave ranging integrated device, which is used for adjusting the synchronization of two-side sampling moments of two-end traveling wave ranging, monitoring the clock deviation of two sides in real time, improving the reliability of the two-end traveling wave ranging and being easy to realize engineering.

In order to achieve the technical purpose and achieve the technical effect, the invention is realized by the following technical scheme:

the two-side clock synchronous monitoring method of the line protection and double-end traveling wave distance measurement integrated device comprises the following steps:

step 1: the host calculates the channel delay;

step 2: the slave computer adjusts the sampling time according to the sampling time of the host computer;

and step 3: the host calculates clock deviations on two sides of the circuit;

and 4, step 4: and the host judges whether the clocks on the two sides are synchronous according to the clock deviation on the two sides.

Preferably, in step 1, the specific steps of the host computer calculating the channel delay are as follows:

101. before formally starting synchronous sampling, the master sends the master current time scale t to the slave_mAnd calculating the channel delay t_dA command of (2);

102. delay t after slave receives command_n-delayAfter that time, delay time t_n-delayReturning to the host;

103. let t be the time when the host receives the return information'_mThen calculate the channel delay t_d＝(t'_m-t_m-t_n-delay)/2。

Preferably, in step 2, the specific step of adjusting the sampling time of the slave according to the sampling time of the master is as follows:

201. the master sends the current time mark t to the slave_miChannel delay t_dAnd a sampling time adjustment command;

202. the slave machine receives the time t 'of the information in the step 201'_niAnd t_dDetermining t_miCorresponding sampling time t of the side_niWherein, t_niIs nearest (t'_ni-t_d) The slave sampling time of (1);

203. the slave computer calculates the error delta t between the sampling moments at two sides as t_ni-t_mi；

204. The slave computer will sample the time t next time_n(i+1)Is adjusted to t_n(i+1)＝t_ni+T_s- Δ T, wherein T_sIs the sampling interval.

Preferably, in step 3, the specific steps of the host computer calculating the clock deviations on the two sides of the line are as follows:

301. slave capturing PPS clock triggering time t_n-PPS；

302. The slave at the next first sampling time t_njSending t to the host_n-PPSAnd t_nj；

303. The host computer receives the message from the step 302 at the moment t'_mjSum channel delay t_dDetermining t_njCorresponding sampling time t of the side_mjWherein, t_mjIs nearest (t'_mj-t_d) The host sampling time of (1);

304. the host computer calculates the error delta t' between the sampling moments at two sides as | t_mj-t_nj|；

305. If Δ t' is greater than or equal to Δ t_maxIf so, the sampling moments of the host and the slave are not synchronized, the host does not calculate clock deviations at two sides, and the step 2 is returned; if Δ t' < Δ t_maxIf the sampling time of the master and the slave are synchronized, the master memorizes t_mjThe clock triggering time of the front host PPS is t_m-PPSCalculating the clock deviation Deltat on both sides_-PPS＝t_m-PPS-t_n-PPS(ii) a Where Δ t_maxIs a preset value.

Preferably, in step 4, the specific method for the host to judge whether the clocks on the two sides are synchronous according to the clock deviation on the two sides is as follows:

when the clock deviation at both sides is Δ t_-PPSWhen the clock synchronization is smaller than the abnormal threshold value, the clock synchronization at the two sides is judged;

when the clock deviation at both sides is Δ t_-PPSAnd when the clock is larger than the abnormal threshold value, judging that the clocks at the two sides are not synchronous.

Preferably, when the clocks on the two sides are judged to be asynchronous, the host sends out an alarm signal that the clocks on the two sides are asynchronous.

The invention has the beneficial effects that:

the invention can realize the synchronization of the sampling time at two sides of the double-end traveling wave distance measurement, monitor the clock deviation at two sides in real time, ensure the consistency of the clocks at two sides and improve the reliability of the double-end traveling wave distance measurement.

Drawings

FIG. 1 is a flow chart of a two-side clock synchronization monitoring method of the line protection and double-end traveling wave ranging integrated device of the present invention;

FIG. 2 is a schematic diagram of the host computing channel delay of the present invention;

FIG. 3 is a schematic diagram of the slave adjusting the sampling time according to the sampling time of the master according to the present invention;

FIG. 4 is a schematic diagram of the host computing a two-sided clock skew according to the present invention.

Detailed Description

The present invention will be better understood and implemented by those skilled in the art by the following detailed description of the technical solution of the present invention with reference to the accompanying drawings and specific examples, which are not intended to limit the present invention.

As shown in fig. 1, the method for monitoring the clock synchronization on both sides of the line protection and double-ended traveling wave ranging integrated device includes the following steps:

step 1: the host calculates the channel delay;

step 2: the slave computer adjusts the sampling time according to the sampling time of the host computer;

and step 3: the host calculates clock deviations on two sides of the circuit;

and 4, step 4: and the host judges whether the clocks on the two sides are synchronous according to the clock deviation on the two sides.

The following detailed description is presented in conjunction with preferred embodiments.

Preferably, as shown in fig. 2, in step 1, the specific step of the host calculating the channel delay is:

101. before formally starting synchronous sampling, the master sends the master current time scale t to the slave_mAnd calculating the channel delay t_dA command of (2);

102. delay t after slave receives command_n-delayAfter that time, delay time t_n-delayReturning to the host;

103. let t be the time when the host receives the return information'_mThen calculate the channel delay t_d＝(t'_m-t_m-t_n-delay)/2。

Preferably, as shown in fig. 3, in step 2, the specific step of the slave adjusting the sampling time according to the sampling time of the master is:

201. the master sends the current time mark t to the slave_miChannel delay t_dAnd a sampling time adjustment command;

202. the slave machine receives the information in the step 201 according to the timet'_niAnd t_dDetermining t_miCorresponding sampling time t of the side_niWherein, t_niIs nearest (t'_ni-t_d) The slave sampling time of (1);

203. the slave computer calculates the error delta t between the sampling moments at two sides as t_ni-t_mi；

204. In order to synchronize the sampling time of the two sides, the slave adjusts the sampling time to make delta t tend to 0, and the slave samples the next time t_n(i+1)Is adjusted to t_n(i+1)＝t_ni+T_s- Δ T, wherein T_sIs the sampling interval.

Preferably, as shown in fig. 4, in step 3, the specific steps of the host computer calculating the clock skew on both sides of the line are:

301. slave capturing PPS clock triggering time t_n-PPS；

302. The slave at the next first sampling time t_njSending t to the host_n-PPSAnd t_nj；

303. The host computer receives the message from the step 302 at the moment t'_mjSum channel delay t_dDetermining t_njCorresponding sampling time t of the side_mjWherein, t_mjIs nearest (t'_mj-t_d) The host sampling time of (1);

304. the host computer calculates the error delta t' between the sampling moments at two sides as | t_mj-t_nj|；

305. If Δ t' is greater than or equal to Δ t_maxIf so, the sampling moments of the host and the slave are not synchronized, the host does not calculate clock deviations at two sides, and the step 2 is returned; if Δ t' < Δ t_maxIf the sampling time of the master and the slave are synchronized, the master memorizes t_mjThe clock triggering time of the front host PPS is t_m-PPSCalculating the clock deviation Deltat on both sides_-PPS＝t_m-PPS-t_n-PPS(ii) a Where Δ t_maxIs a preset value.

Preferably, in step 4, the specific method for the host to judge whether the clocks on the two sides are synchronous according to the clock deviation on the two sides is as follows:

when the clock deviation at both sides is Δ t_-PPSWhen the clock synchronization is smaller than the abnormal threshold value, the clock synchronization at the two sides is judged;

when the clock deviation at both sides is Δ t_-PPSAnd when the clock is larger than the abnormal threshold value, judging that the clocks at the two sides are not synchronous.

Preferably, when the clocks on the two sides are judged to be asynchronous, the host sends out an alarm signal that the clocks on the two sides are asynchronous.

The invention can realize the synchronization of the sampling time at two sides of the double-end traveling wave distance measurement, monitor the clock deviation at two sides in real time, ensure the consistency of the clocks at two sides and improve the reliability of the double-end traveling wave distance measurement.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

1. The two-side clock synchronous monitoring method of the line protection and double-end traveling wave distance measurement integrated device is characterized by comprising the following steps of:

step 1: the host calculates the channel delay;

step 2: the slave computer adjusts the sampling time according to the sampling time of the host computer;

and step 3: the host calculates clock deviations on two sides of the circuit;

and 4, step 4: the host judges whether the clocks on the two sides are synchronous according to the clock deviation on the two sides;

in step 1, the specific steps of the host computer for calculating the channel delay are as follows:

101. before formally starting synchronous sampling, the master sends the master current time scale t to the slave_mAnd calculating the channel delay t_dA command of (2);

102. delay t after slave receives command_n-delayAfter that time, delay time t_n-delayReturning to the host;

103. let t be the time when the host receives the return information'_mThen calculate the channel delay t_d＝(t'_m-t_m-t_n-delay)/2；

In step 2, the specific steps of the slave adjusting the sampling time according to the sampling time of the master are as follows:

201. the master sends the current time mark t to the slave_miChannel delay t_dAnd a sampling time adjustment command;

202. the slave machine receives the time t 'of the information in the step 201'_niAnd t_dDetermining t_miCorresponding sampling time t of the side_niWherein, t_niIs nearest (t'_ni-t_d) The slave sampling time of (1);

203. the slave computer calculates the error delta t between the sampling moments at two sides as t_ni-t_mi；

204. The slave computer will sample the time t next time_n(i+1)Is adjusted to t_n(i+1)＝t_ni+T_s- Δ T, wherein T_sIs the sampling interval;

in step 3, the specific steps of calculating the clock deviations on the two sides of the line by the host computer are as follows:

301. slave capturing PPS clock triggering time t_n-PPS；

302. The slave at the next first sampling time t_njSending t to the host_n-PPSAnd t_nj；

303. The host computer receives the message from the step 302 at the moment t'_mjSum channel delay t_dDetermining t_njCorresponding sampling time t of the side_mjWherein, t_mjIs nearest (t'_mj-t_d) The host sampling time of (1);

304. the host computer calculates the error delta t' between the sampling moments at two sides as | t_mj-t_nj|；

305. If Δ t' is greater than or equal to Δ t_maxIf so, the sampling moments of the host and the slave are not synchronized, the host does not calculate clock deviations at two sides, and the step 2 is returned; if Δ t' < Δ t_maxIf the sampling time of the master and the slave are synchronized, the master memorizes t_mjThe clock triggering time of the front host PPS is t_m-PPSCalculating the clock deviation Deltat on both sides_-PPS＝t_m-PPS-t_n-PPS(ii) a Where Δ t_maxIs a preset value;

in step 4, the specific method for judging whether the clocks on the two sides are synchronous by the host according to the clock deviation on the two sides is as follows:

when the clock deviation at both sides is Δ t_-PPSWhen the clock synchronization is smaller than the abnormal threshold value, the clock synchronization at the two sides is judged;

when the clock deviation at both sides is Δ t_-PPSWhen the clock frequency is larger than the abnormal threshold value, the clocks at the two sides are judged to be asynchronous;

when the clocks at the two sides are judged to be asynchronous, the host sends out an alarm signal that the clocks at the two sides are asynchronous.