CN108574486A - clock signal processing system and method thereof - Google Patents

一种时脉信号处理系统及其方法，应用于通用串行总线USB音频同步模式(synchronous mode)声音时脉重建的环境中，利用本发明的时脉信号处理系统以进行时脉信号处理方法时，首先，利用第一级锁相回路PLL(Phase‑Locked Loops)将所输入的通用串行总线USB信息帧起始位SOF(SOF,Start Of Frame)频率予以提升，提供时脉同步，并输出至第二级锁相回路；接着，利用第二级锁相回路PLL降低第一级锁相回路的输出的时脉抖动(Timing Jitter)并将其时脉抖动予以降低到20ps以下。

A clock signal processing system and method thereof are applied to the environment of audio clock reconstruction in synchronous mode of universal serial bus (USB). When the clock signal processing system of the present invention is used to perform the clock signal processing method, firstly, the frequency of the inputted universal serial bus (USB) information frame start bit SOF (SOF, Start Of Frame) is increased by using a first-stage phase-locked loop (PLL) (Phase-Locked Loops) to provide clock synchronization and output to a second-stage phase-locked loop; then, the second-stage phase-locked loop (PLL) is used to reduce the clock jitter (Timing Jitter) of the output of the first-stage phase-locked loop and reduce its clock jitter to less than 20ps.

时脉信号处理系统及其方法Clock signal processing system and method thereof

技术领域technical field

本发明涉及信号处理系统及方法，更详而言之，涉及一种应用于通用串行总线USB音频(Audio)同步模式(synchronous mode)声音时脉重建的环境中的时脉信号处理系统及其方法，将所输入的通用串行总线USB信息帧起始位SOF(SOF,Start Of Frame)频率予以提升，提供时脉同步，并将其时脉抖动予以降低到20ps以下。The present invention relates to a signal processing system and method, more specifically, to a clock signal processing system and its application in the environment of universal serial bus USB audio (Audio) synchronous mode (synchronous mode) sound clock reconstruction In the method, the frequency of the input SOF (SOF, Start Of Frame) of the USB information frame is increased to provide clock synchronization, and the clock jitter thereof is reduced to below 20 ps.

背景技术Background technique

目前的USB定义了四种传输型态：(1)控制传输(Control Transfers)，The current USB defines four transfer types: (1) Control Transfers,

为用于控制传输命令及状态操作，例如设定装置、取得装置信息、发送指令到装置等，每个USB装置都有一个Endpoint 0，USB Core为装置插入后进行设定；(2)中断传输(Interrupt Transfers)，与一般常见的中断不同，需要host端先询问(Polling)才会执行，以一个固定速率传输少量数据，例如，To control transmission commands and state operations, such as setting the device, obtaining device information, sending commands to the device, etc., each USB device has an Endpoint 0, and the USB Core is set after the device is inserted; (2) interrupt transmission (Interrupt Transfers), different from common interrupts, requires the host to ask (Polling) before executing, and transfer a small amount of data at a fixed rate, for example,

USB键盘，鼠标；(3)批次传输(Bulk Transfers)，用于大量数据传输、且需确保数据无误，例如，传至随身碟，而并无速度限制，若传输失败则再重传以便确保数据正确；以及，(4)同时传输(Isochronous Transfers)，用于大量数据传输，但不确保数据是否正确到达，例如，USB视频装置，希望传送的声音或影像的速率是稳定的，然，若有几个信息帧遗失，没有通过循环冗余检测码CRC数据也不会重传。USB keyboard, mouse; (3) Bulk Transfers (Bulk Transfers), used for large amounts of data transfer, and it is necessary to ensure that the data is correct, for example, transfer to a flash drive, and there is no speed limit. The data is correct; and, (4) simultaneous transmission (Isochronous Transfers), used for large amounts of data transmission, but does not ensure that the data arrives correctly, for example, a USB video device, the rate of sound or video that is expected to be transmitted is stable, however, if A few frames of information are lost, and the data that does not pass the cyclic redundancy check code CRC will not be retransmitted.

Transaction传输是指USB数据的传输，大部分的传输包含了三种封包(Token packet、Data packet、Handshake或称Status packet)；Transaction传输可以从主机端(Host)传向外围设备(Device)，或从外围设备(Device)传向主机端(Host)，而传送方向由Tokenpacket指定；一般来说，目标端利用Handshake(Status packet)来判断此次传输是否成功。Transaction transmission refers to the transmission of USB data. Most of the transmission includes three types of packets (Token packet, Data packet, Handshake or Status packet); Transaction transmission can be transmitted from the host (Host) to the peripheral device (Device), or From the peripheral device (Device) to the host end (Host), and the transmission direction is specified by Tokenpacket; generally speaking, the target end uses Handshake (Status packet) to judge whether the transmission is successful.

而为了确保同步，USB把时间切割成固定长度的小区间。例如，低速和全速的时候是以1ms为单位，称为一个信息帧Frame，而高速时再把一个信息帧Frame切成八等分，一个0.125ms为单位，称为微帧microframes；In order to ensure synchronization, USB cuts the time into small intervals of fixed length. For example, at low speed and full speed, the unit is 1ms, which is called an information frame Frame, and at high speed, an information frame is cut into eight equal parts, and a unit of 0.125ms is called microframes;

信息帧起始位SOF封包(Start-Of-Frame Packet)为一种特殊的封包，是在每一个信息帧Frame开始时发送。The start-of-frame SOF packet (Start-Of-Frame Packet) is a special packet, which is sent at the beginning of each information frame Frame.

通用串行总线USB音频同步模式(synchronous mode)在放音与录音时需要一个时脉CLK来驱动数字模拟转换器DAC与模拟数字转换器ADC，而此时脉CLK须与USB接收与传送的数据同步，例如，此时脉CLK须与USB HOST送过来的数据流速率同步，这样才不会造成不连续音，否则会有不连续现象。Universal Serial Bus USB audio synchronous mode (synchronous mode) requires a clock CLK to drive the digital-to-analog converter DAC and the analog-to-digital converter ADC during playback and recording, and this clock CLK must be compatible with the data received and transmitted by the USB Synchronization, for example, at this time, the clock CLK must be synchronized with the data flow rate sent by the USB HOST, so as not to cause discontinuous sound, otherwise there will be discontinuity.

最早的作法是用单一锁相回路PLL将通用串行总线USB信息帧起始位SOF频率(例如，全速时为1Khz(1Khz@full speed)，或是，全速时为8Khz(8Khz@high speed))升频到1024*48Khz，但是单一锁相回路PLL将USB SOF频率，例如，1Khz予以提升49152倍之后，信号的时脉抖动非常严重，以致于数字模拟转换器DAC与模拟数字转换器ADC有极大的杂音。The earliest practice is to use a single phase-locked loop PLL to set the SOF frequency of the universal serial bus USB information frame (for example, 1Khz (1Khz@full speed) at full speed, or 8Khz (8Khz@high speed) at full speed) ) to 1024*48Khz, but after a single phase-locked loop PLL increases the USB SOF frequency, for example, 1Khz by 49152 times, the clock pulse jitter of the signal is very serious, so that the digital-to-analog converter DAC and the analog-to-digital converter ADC have different Great noise.

现行USB AUDIO方案公司又提出了一个适应性模式(adaptive mode)，其观念是USBDEVICE使用两个很深的先进先出FIFO缓冲区(深度一般大于1000)来分别储存HOST传过来以及要传给HOST的数据。然后控制器动态调适本地的时脉合成器(clock synthesizor)频率，使DAC/ADC速度让缓冲区内的数据深度处于一个范围(设定缓冲区储存的数量上下限)，并控制锁相回路时脉CLK PLL来调整此缓冲区的除取速度让其处于一个设定范围。然，利用此适应式模式会有两个缺点产生，第一个缺点是动态调适方式调整时脉合成器将造成时脉抖动变大(通常大于200ps)并将导致声音品质变差，而第二个缺点为使用很深的缓冲区将造成播放音的延迟。The current USB AUDIO solution company has proposed an adaptive mode (adaptive mode). The concept is that USBDEVICE uses two deep first-in-first-out FIFO buffers (the depth is generally greater than 1000) to store the data transmitted from the HOST and those to be transmitted to the HOST. The data. Then the controller dynamically adjusts the frequency of the local clock synthesizer (clock synthesizer), so that the DAC/ADC speed keeps the data depth in the buffer within a range (setting the upper and lower limits of the number stored in the buffer), and controls the phase-locked loop time Pulse CLK PLL to adjust the division speed of this buffer to keep it in a set range. However, using this adaptive mode will have two disadvantages. The first disadvantage is that the dynamic adjustment method to adjust the clock synthesizer will cause the clock jitter to increase (usually greater than 200ps) and cause the sound quality to deteriorate. The second A disadvantage is that using a deep buffer will cause a delay in playing the sound.

就目前的使用先进先出FIFO缓冲区而言，美国专利公开/公告号US7715513“Datasynchronization apparatus”公开包含先进先出暂存器、控制电路、以及锁相回路的数据同步装置；先进先出暂存器接收并储存多个数据且根据储存于先进先出暂存器中的数据的数目提供暂存器调整信号；储存于先进先出暂存器中的数据以根据一主时脉信号所得来的时脉速率发出至外部装置；控制电路根据暂存器调整信号来提供锁相回路调整信号；以及，锁相回路提供主时脉信号且依据锁相回路调整信号来调整主时脉信号的频率。换言之，以先进先出FIFO缓冲区作为缓冲区，然后调整锁相回路PLL的速度来让USB播音不会有不连续现象产生。As far as the current FIFO buffer is used, U.S. Patent Publication/Notice No. US7715513 "Data synchronization apparatus" discloses a data synchronization device comprising a first-in first-out register, a control circuit, and a phase-locked loop; the first-in first-out register The register receives and stores a plurality of data and provides a register adjustment signal according to the number of data stored in the first-in first-out register; the data stored in the first-in first-out register is obtained according to a main clock signal The clock rate is sent to the external device; the control circuit provides a PLL adjustment signal according to the register adjustment signal; and the PLL provides the main clock signal and adjusts the frequency of the main clock signal according to the PLL adjustment signal. In other words, use the first-in-first-out FIFO buffer as the buffer, and then adjust the speed of the phase-locked loop PLL so that there will be no discontinuity in USB playback.

另，赛普拉斯半导体(Cypress Semiconductor)公司的通用串行总线USB音频(Audio)的作法也是以先进先出FIFO缓冲区作为缓冲区，然后调整锁相回路PLL的速度而让USB播音无不连续现象。In addition, Cypress Semiconductor's Universal Serial Bus USB Audio (Audio) method also uses the first-in-first-out FIFO buffer as a buffer, and then adjusts the speed of the phase-locked loop PLL to make USB broadcasting without discontinuity Phenomenon.

台湾公开/公告号I557573「可携式储存装置、及相关方法与非暂时性机器可读媒体」所公开的是，一便携式储存装置用以从一第一运算装置获得第一文件的一版本，并更新该便携式储存装置中的该第一文件，以形成一经更新第一文件；然后，该便携式储存装置判定该第一文件在一第二运算装置上的一版本不同于该便携式储存装置中的该经更新第一文件，并将该经更新第一文件提供给该第二运算装置；此外，该便携式储存装置用以判定该第一文件在一远端储存服务上的一版本不同于该经更新第一文件，并将该经更新第一文件提供给该远端储存服务。Taiwan publication/announcement number I557573 "Portable storage device, related method and non-transitory machine-readable medium" discloses that a portable storage device is used to obtain a version of a first file from a first computing device, and updating the first file in the portable storage device to form an updated first file; then, the portable storage device determines that a version of the first file on a second computing device is different from that in the portable storage device the updated first file, and provide the updated first file to the second computing device; in addition, the portable storage device is used to determine that a version of the first file on a remote storage service is different from the The first file is updated, and the updated first file is provided to the remote storage service.

台湾公开/公告号I544337「共用通用串行的总线(USB)装置之双作业系统架构以及双作业系统架构共用通用串行的总线(USB)装置之方法」公开，一种可共用USB装置的双作业系统架构包括：一第一作业系统；一第二作业系统；USB集线器，连接多个USB装置；以及一切换开关，用以在该第一作业系统切换至该第二作业系统时，使该第二作业系统连接至USB集线器，并切断该第一作业系统与USB集线器的连接。Taiwan publication/announcement number I544337 "Dual operating system framework for sharing a universal serial bus (USB) device and a method for sharing a universal serial bus (USB) device in a dual operating system architecture" discloses a dual operating system that can share a USB device The operating system architecture includes: a first operating system; a second operating system; a USB hub for connecting a plurality of USB devices; and a switch for switching the first operating system to the second operating system to enable the The second operating system is connected to the USB hub, and cuts off the connection between the first operating system and the USB hub.

台湾公开/公告号I540426「移动装置基于热条件之动态调整」是公开，一移动装置可经组态以监测与该移动装置及/或一同级装置相关联之环境、系统及使用者事件。一或多个事件的发生可触发对系统设定的调整。该移动装置可经组态以基于对使用者的经预测叫用之一预报来将频繁叫用的应用程序保持为最新。该移动装置可接收与应用程序相关联的推播通知，所述推播通知指示新内容可供所述应用程序下载。该移动装置可在背景中启动与所述推播通知相关联的应用程序且下载该新内容。在执行一应用程序或与一同级装置通信之前，该移动装置可经组态以检查该移动装置及/或一同级装置的能量及数据预算以及环境条件以确保一高品质使用者体验。Taiwan Publication/Bulletin No. I540426 "Dynamic Adjustment of Mobile Devices Based on Thermal Conditions" discloses that a mobile device can be configured to monitor environmental, system and user events associated with the mobile device and/or peer devices. The occurrence of one or more events may trigger adjustments to system settings. The mobile device can be configured to keep frequently used applications up to date based on a forecast of the user's predicted calls. The mobile device can receive a push notification associated with an application indicating that new content is available for download by the application. The mobile device can launch an application associated with the push notification in the background and download the new content. Before executing an application or communicating with a peer device, the mobile device can be configured to check the energy and data budget and environmental conditions of the mobile device and/or peer devices to ensure a high quality user experience.

所以，如何能避免以单一锁相回路PLL将USB SOF频率，例如，1Khz予以提升49152倍之后，信号的时脉抖动非常严重，以致于数字模拟转换器DAC与模拟数字转换器ADC有极大的杂音；以及，如何能避免使用适应性模式，而不会产生动态调适方式调整时脉合成器所造成的时脉抖动变大(大于200ps)并导致声音品质变差的情况，亦不会产生使用很深的缓冲区而造成播放音的延迟的情况，均是待解决的问题。Therefore, how to avoid using a single phase-locked loop PLL to increase the USB SOF frequency, for example, 1Khz by 49152 times, the clock pulse jitter of the signal is very serious, so that there is a huge difference between the digital-to-analog converter DAC and the analog-to-digital converter ADC Noise; and, how to avoid the use of adaptive mode, without the dynamic adjustment method to adjust the clock pulse jitter caused by the clock synthesizer to become larger (greater than 200ps) and cause the sound quality to deteriorate, and it will not occur when using The delay of playing sound caused by a deep buffer zone is a problem to be solved.

发明内容Contents of the invention

本发明的主要目的在于提供一种时脉信号处理系统及其方法，应用于通用串行总线USB音频同步模式(synchronous mode)声音时脉重建的环境中，利用第一级锁相回路PLL(Phase-Locked Loops)将所输入的通用串行总线USB信息帧起始位SOF(SOF,Start OfFrame)频率予以提升，提供时脉同步，并输出至第二级锁相回路；接着，利用第二级锁相回路PLL降低第一级锁相回路的输出的时脉抖动(Timing Jitter)并将其时脉抖动予以降低到20ps以下。The main purpose of the present invention is to provide a kind of clock signal processing system and method thereof, be applied in the environment of universal serial bus USB audio synchronous mode (synchronous mode) sound clock reconstruction, utilize the first stage phase-locked loop PLL (Phase -Locked Loops) to increase the frequency of the input SOF (SOF, Start Of Frame) of the input universal serial bus USB information frame, provide clock synchronization, and output to the second-stage phase-locked loop; then, use the second-stage The phase-locked loop PLL reduces the timing jitter (Timing Jitter) of the output of the first-stage phase-locked loop and reduces the timing jitter to below 20 ps.

本发明的另一目的在于提供一种时脉信号处理系统及其方法，应用于通用串行总线USB音频同步模式(synchronous mode)声音时脉重建的环境中，利用双锁相回路PLL的方式来锁定与系统单芯片SOC同步时脉。Another object of the present invention is to provide a kind of clock signal processing system and method thereof, be applied in the environment of universal serial bus USB audio synchronous mode (synchronous mode) voice clock reconstruction, utilize the mode of double phase-locked loop PLL to realize Locked to the system-on-a-chip SOC synchronous clock.

本发明的又一目的在于提供一种时脉信号处理系统及其方法，应用于通用串行总线USB音频同步模式(synchronous mode)声音时脉重建的环境中，第一级锁相回路PLL将USBSOF提升到49152倍，主要提供时脉同步，而第二级锁相回路PLL将降低第一级锁相回路PLL的输出时脉抖动，将其抖动降低到20ps以下。Yet another object of the present invention is to provide a kind of clock signal processing system and method thereof, be applied in the environment of universal serial bus USB audio synchronous mode (synchronous mode) sound clock pulse reconstruction, the first stage PLL will USBSOF Increased to 49152 times, mainly to provide clock synchronization, and the second-stage phase-locked loop PLL will reduce the output clock jitter of the first-stage phase-locked loop PLL, reducing its jitter to below 20ps.

本发明的又一目的在于提供一种时脉信号处理系统及其方法，应用于通用串行总线USB音频同步模式(synchronous mode)声音时脉重建的环境中，当数字模拟转换器DAC/模拟数字转换器ADC时脉与通用串行总线USB信息帧起始位SOF同步时，能使用一个小容量的缓冲区(<100)储存一个信息帧起始位SOF的数据量，而无须很深的缓冲区(>1000)即能正常且没有不连续的播放音，且，由于使用小缓冲区，因而，声音延迟性也大幅改善到1ms以内。Yet another object of the present invention is to provide a kind of clock signal processing system and method thereof, be applied in the environment of universal serial bus USB audio synchronous mode (synchronous mode) sound clock reconstruction, when the digital-to-analog converter DAC/analog-digital When the ADC clock pulse of the converter is synchronized with the SOF of the universal serial bus USB information frame, a small-capacity buffer (<100) can be used to store the data volume of a SOF of the information frame without a deep buffer Zone (>1000) can be played normally without discontinuous sound, and, because of the use of a small buffer, the sound delay is also greatly improved to within 1ms.

本发明的又一目的在于提供一种时脉信号处理系统及其方法，应用于通用串行总线USB音频同步模式(synchronous mode)声音时脉重建的环境中，可改善时脉抖动、大幅缩减先进先出FIFO缓冲区大小、提升音频的信号噪声比SNR、并降低音频的延迟。Another object of the present invention is to provide a clock signal processing system and method thereof, which can be used in the environment of universal serial bus USB audio synchronous mode (synchronous mode) sound clock reconstruction, which can improve clock jitter and greatly reduce advanced First output the FIFO buffer size, improve the signal-to-noise ratio SNR of the audio, and reduce the delay of the audio.

根据以上所述的目的，本发明提供一种时脉信号处理系统，该时脉信号处理系统包含USB接口、第一级锁相回路PLL、第二级锁相回路PLL、第一先进先出FIFO缓冲区、以及第二先进先出FIFO缓冲区。According to the purpose described above, the present invention provides a kind of clock signal processing system, and this clock signal processing system comprises USB interface, first-stage phase-locked loop PLL, second-stage phase-locked loop PLL, first first-in-first-out FIFO buffer, and a second FIFO buffer.

第一级锁相回路PLL，该第一级锁相回路PLL输入端与USB接口连接，USB接口接收/传送USB HOST输出/输入的声音数据，USB接口会送出信息帧起始位SOF至该第一级锁相回路PLL输入端，USB接口并将脉波数量调制PCM IN信号传送至第一先进先出FIFO缓冲区、USB接口并然后接受来自于第二先进先出FIFO缓冲区的脉波数量调制PCM OUT信号；以及，该第一级锁相回路PLL收到信息帧起始位SOF后，例如，会输出49152倍时脉给第二级锁相回路PLL，该第一级锁相回路PLL担任的是升频/时脉同步的角色。The first-level phase-locked loop PLL, the input end of the first-level phase-locked loop PLL is connected to the USB interface, the USB interface receives/transmits the sound data output/input by the USB HOST, and the USB interface will send the start bit SOF of the information frame to the second The first-level phase-locked loop PLL input terminal, the USB interface and the pulse quantity modulation PCM IN signal is sent to the first FIFO buffer, the USB interface and then receives the pulse quantity from the second FIFO buffer Modulate the PCM OUT signal; and, after the first-stage phase-locked loop PLL receives the information frame start bit SOF, for example, it will output 49152 times the clock pulse to the second-stage phase-locked loop PLL, and the first-stage phase-locked loop PLL It plays the role of frequency up/clock synchronization.

第二级锁相回路PLL，该第二级锁相回路PLL将改善所接收到的来自于该第一级锁相回路PLL的升频后的同步时脉的时脉信号；该第二级锁相回路PLL将降低该时脉信号的时脉抖动，然后将经时脉抖动处理后的时脉信号输出至数字模拟转换器DAC与模拟数字转换器ADC；其中，第二级锁相回路PLL降低第一级锁相回路PLL的输出的时脉抖动并将其时脉抖动予以降低到20ps以下。The second-stage phase-locked loop PLL, the second-stage phase-locked loop PLL will improve the received clock signal from the up-converted synchronous clock pulse of the first-stage phase-locked loop PLL; the second-stage lock The phase loop PLL will reduce the clock jitter of the clock signal, and then output the clock signal processed by the clock jitter to the digital-to-analog converter DAC and the analog-to-digital converter ADC; among them, the second-stage phase-locked loop PLL reduces The clock jitter of the output of the first-stage phase-locked loop PLL is reduced to less than 20 ps.

第一先进先出FIFO缓冲区，该第一先进先出FIFO缓冲区是数字模拟转换器DAC暂存数据小容量的先进先出缓冲区(深度<100)，可储存HOST经由USB接口所送过来的一个信息帧起始位SOF的数据，该数据可由数字模拟转换器DAC来予以读取。The first first-in first-out FIFO buffer, the first first-in first-out FIFO buffer is a small-capacity first-in first-out buffer (depth <100) for digital-to-analog converter DAC temporary storage data, which can store HOST sent over via USB interface The data of an information frame start bit SOF, which can be read by the digital-to-analog converter DAC.

第二先进先出FIFO缓冲区，该第二先进先出FIFO缓冲区，暂存模拟数字转换器ADC输出的小容量的先进先出缓冲区(深度<100)，经由USB接口，通过每个信息帧起始位SOF而读取该第二先进先出FIFO缓冲区的数据并将其传送至HOST。The second first-in-first-out FIFO buffer, the second first-in-first-out FIFO buffer, temporarily stores the small-capacity first-in-first-out buffer (depth<100) output by the analog-to-digital converter ADC, through the USB interface, through each information The start of frame bit SOF is used to read the data of the second FIFO buffer and transmit it to the HOST.

本发明的时脉信号处理系统使用第一级锁相回路PLL、以及第二级锁相回路PLL，经由该第一级锁相回路PLL而将信息帧起始位SOF(1khz or8khz)予以升频，该第二级锁相回路PLL将升频后的同步时脉的时脉信号进行降低时脉抖动处理，以便将经时脉抖动处理后的时脉信号(例如，1024*48K hz)输出至数字模拟转换器DAC与模拟数字转换器ADC以供其使用。当稳定时数字模拟转换器DAC的时脉CLK是跟信息帧起始位SOF同步的，经由USB接口而来的声音的音频数据亦与信息帧起始位SOF同步，所以数字模拟转换器DAC上使用的时脉CLK跟第一先进先出FIFO缓冲区的数据(DATA)同步，而无不连续的情形，因而，第一先进先出FIFO缓冲区只要能容纳一个信息帧起始位SOF的数据容量即可，而如此一来，经由USB接口的USB HOST到数字模拟转换器DAC的数据延迟就可以非常短。The clock signal processing system of the present invention uses a first-stage phase-locked loop PLL and a second-stage phase-locked loop PLL, and up-converts the start bit SOF (1khz or 8khz) of the information frame through the first-stage phase-locked loop PLL , the second-level phase-locked loop PLL performs clock jitter reduction processing on the clock signal of the up-converted synchronous clock, so as to output the clock signal (for example, 1024*48K hz) after clock jitter processing to Digital-to-analog converter DAC and analog-to-digital converter ADC for its use. When stable, the clock pulse CLK of the digital-to-analog converter DAC is synchronized with the SOF of the information frame, and the audio data of the sound coming from the USB interface is also synchronized with the SOF of the information frame, so the digital-to-analog converter DAC The used clock CLK is synchronous with the data (DATA) of the first FIFO buffer, without discontinuity. Therefore, the first FIFO buffer only needs to be able to accommodate the data capacity of an information frame start bit SOF In this way, the data delay from the USB HOST to the digital-to-analog converter DAC via the USB interface can be very short.

于本发明的实施例中，第一级锁相回路PLL可包含第一相位检测器PD(Phase Detect)、第一低通滤波器LPF、第一压控振荡器VCO、以及第一除频器；第一相位检测器PD将信息帧起始位SOF跟第一除频器(除以49152)的输出进行相位差异检测、并将进行相位差异检测后的信号传送至第一低通滤波器LPF；以及，第一低通滤波器LPF将相位差异的信号做低频滤波处理、并将其传送至第一压控振荡器VCO，第一低通滤波器LPF的设计方向为须能接受极低频(低至1Khz)的输入。In an embodiment of the present invention, the first-stage phase-locked loop PLL may include a first phase detector PD (Phase Detect), a first low-pass filter LPF, a first voltage-controlled oscillator VCO, and a first frequency divider ; The first phase detector PD carries out phase difference detection with the output of the information frame start bit SOF and the first frequency divider (divided by 49152), and sends the signal after the phase difference detection to the first low-pass filter LPF and, the first low-pass filter LPF performs low-frequency filtering processing on the signal of the phase difference, and transmits it to the first voltage-controlled oscillator VCO, and the design direction of the first low-pass filter LPF must be able to accept extremely low frequencies ( input as low as 1Khz).

另，于本发明的实施例中，第二级锁相回路PLL可包含第二相位检测器PD(PhaseDetect)、第二低通滤波器LPF、第二压控振荡器VCO、以及第二除频器；第二相位检测器PD将比较来自于第一级锁相回路PLL的经升频后的同步时脉的时脉信号、以及第二压控振荡器VCO的输出、并然后送至第二低通滤波器LPF；第二低通滤波器LPF的设计方向跟第一低通滤波器LPF不一样，是为了降低第一级锁相回路PLL输出的经升频后的同步时脉的时脉信号的时脉抖动，需要将第二低通滤波器LPF设计在过阻尼状态，而稳定时间设计为数ms；以及，第二压控振荡器VCO的输出将传送至第二除频器，而第二除频器将进行除2处理，第二除频器作责任周期调整以便将信号输出至数字模拟转换器DAC与模拟数字转换器ADC以供其使用。In addition, in the embodiment of the present invention, the second-stage phase-locked loop PLL may include a second phase detector PD (PhaseDetect), a second low-pass filter LPF, a second voltage-controlled oscillator VCO, and a second frequency divider The second phase detector PD will compare the clock signal of the up-converted synchronous clock from the first-stage phase-locked loop PLL and the output of the second voltage-controlled oscillator VCO, and then send it to the second Low-pass filter LPF; the design direction of the second low-pass filter LPF is different from that of the first low-pass filter LPF, in order to reduce the clock pulse of the up-converted synchronous clock output by the first-stage phase-locked loop PLL signal clock jitter, the second low-pass filter LPF needs to be designed in an over-damped state, and the settling time is designed to be several ms; and, the output of the second voltage-controlled oscillator VCO will be sent to the second frequency divider, and the first The second frequency divider will divide by 2, and the second frequency divider will adjust the duty cycle so as to output the signal to the digital-to-analog converter DAC and the analog-to-digital converter ADC for their use.

利用本发明的时脉信号处理系统以进行时脉信号处理方法的过程时，首先，进行升频动作；经由USB接口，利用第一级锁相回路PLL(Phase-Locked Loops)将所输入的通用串行总线USB信息帧起始位SOF频率予以提升，提供时脉同步，并输出至第二级锁相回路。When utilizing the clock signal processing system of the present invention to carry out the process of the clock signal processing method, at first, carry out the up-frequency action; Via the USB interface, utilize the first-stage phase-locked loop PLL (Phase-Locked Loops) to input the common The SOF frequency of the serial bus USB information frame start bit is increased to provide clock synchronization and output to the second-stage phase-locked loop.

其中，该第一级锁相回路PLL收到信息帧起始位SOF后，例如，会输出49152倍时脉给第二级锁相回路PLL，该第一级锁相回路PLL担任的是升频/时脉同步的角色。Wherein, after the first-stage phase-locked loop PLL receives the start bit SOF of the information frame, for example, it will output 49152 times the clock pulse to the second-stage phase-locked loop PLL, and the first-stage phase-locked loop PLL is responsible for up-frequency / clock synchronization role.

接着，进行时脉抖动处理动作；利用第二级锁相回路PLL降低第一级锁相回路PLL的输出的时脉信号的时脉抖动并将其时脉抖动予以降低到20ps以下。Then, the clock jitter processing action is performed; the clock jitter of the clock signal output by the first-stage phase-locked loop PLL is reduced by using the second-stage phase-locked loop PLL and the clock jitter is reduced to below 20 ps.

其中，该第二级锁相回路PLL将改善所接收到的来自于该第一级锁相回路PLL的升频后的同步时脉的时脉信号；该第二级锁相回路PLL将降低该时脉信号的时脉抖动，然后将经时脉抖动处理后的时脉信号输出至数字模拟转换器DAC与模拟数字转换器ADC；以及，第二级锁相回路PLL降低第一级锁相回路的输出的时脉抖动并将其时脉抖动予以降低到20ps以下。Wherein, the second-stage phase-locked loop PLL will improve the clock signal received from the up-converted synchronous clock pulse of the first-stage phase-locked loop PLL; the second-stage phase-locked loop PLL will reduce the The clock signal of the clock signal is jittered, and then the clock signal processed by the clock jitter is output to the digital-to-analog converter DAC and the analog-to-digital converter ADC; and, the second-stage phase-locked loop PLL reduces the first-stage phase-locked loop The clock jitter of the output and reduce the clock jitter to below 20ps.

为使熟悉该项技艺人士了解本发明的目的、特征及技术效果，兹通过下述具体实施例，并配合所附的附图，对本发明详加说明如后：In order to make those skilled in the art understand the purpose, characteristics and technical effects of the present invention, hereby through the following specific embodiments, and cooperate with the accompanying drawings, the present invention is described in detail as follows:

附图说明Description of drawings

图1为一系统示意图，用以显示说明本发明的时信号处理系统的系统架构、以及配合USB接口、数字模拟转换器DAC与模拟数字转换器ADC的运行情形；1 is a schematic diagram of a system, which is used to illustrate the system architecture of the time signal processing system of the present invention, as well as the operation of a USB interface, a digital-to-analog converter DAC and an analog-to-digital converter ADC;

图2为一流程图，用以显示说明利用如图1中的本发明的时脉信号处理系统以进行时脉信号处理方法的流程步骤；FIG. 2 is a flowchart for illustrating the process steps of using the clock signal processing system of the present invention as in FIG. 1 to perform a clock signal processing method;

图3为一示意图，用以显示说明本发明的时脉信号处理系统的一实施例的架构、以及配合USB接口、数字模拟转换器DAC与模拟数字转换器ADC的运行情形；FIG. 3 is a schematic diagram for illustrating the architecture of an embodiment of the clock signal processing system of the present invention, and the operation of a USB interface, a digital-to-analog converter DAC and an analog-to-digital converter ADC;

图4为一示意图，用以显示说明于图3的实施例中的第一级锁相回路PLL的结构；FIG. 4 is a schematic diagram for illustrating the structure of the first-stage phase-locked loop PLL in the embodiment of FIG. 3;

图5为一流程图，用以显示说明利用如图3中的本发明的时脉信号处理系统的实施例以进行时脉信号处理方法的一流程步骤；FIG. 5 is a flow chart for illustrating a process step of a clock signal processing method using the embodiment of the clock signal processing system of the present invention as shown in FIG. 3;

图6为一流程图，用以显示说明利用如图5中的时脉信号处理方法的进行升频动作步骤的更详细程序；Fig. 6 is a flow chart, in order to show the more detailed program that utilizes the clock signal processing method in Fig. 5 to carry out the step of up-conversion action;

图7为一示意图，用以显示说明本发明的时脉信号处理系统的另一实施例的架构、以及配合USB接口、数字模拟转换器DAC与模拟数字转换器ADC的运行情形；FIG. 7 is a schematic diagram for illustrating the structure of another embodiment of the clock signal processing system of the present invention, and the operation of the USB interface, the digital-to-analog converter DAC and the analog-to-digital converter ADC;

图8为一示意图，用以显示说明于图7的实施例中的第一级锁相回路PLL的结构；FIG. 8 is a schematic diagram for illustrating the structure of the first-stage phase-locked loop PLL in the embodiment of FIG. 7;

图9为一流程图，用以显示说明利用如图7中的本发明的时脉信号处理系统的另一实施例以进行时脉信号处理方法的另一流程步骤；以及FIG. 9 is a flow chart for illustrating another process step of a clock signal processing method using another embodiment of the clock signal processing system of the present invention as shown in FIG. 7; and

图10为一流程图，用以显示说明利用如图9中的时脉信号处理方法的进行时脉抖动处理动作步骤的更详细程序。FIG. 10 is a flow chart for illustrating a more detailed procedure for performing clock jitter processing using the clock signal processing method as shown in FIG. 9 .

附图标记说明：Explanation of reference signs:

1 时脉信号处理系统1 Clock signal processing system

31、32 步骤31, 32 steps

41、42 步骤41, 42 steps

51、52 步骤51, 52 steps

100 USB接口100 USB interface

101 第一级锁相回路PLL101 Phase-locked loop PLL of the first stage

102 第二级锁相回路PLL102 The second phase-locked loop PLL

103 第一先进先出FIFO缓冲区103 First in first out FIFO buffer

104 第二先进先出FIFO缓冲区104 Second FIFO buffer

105 数字模拟转换器DAC105 Digital to Analog Converter DAC

106 模拟数字转换器ADC106 Analog to Digital Converter ADC

200 第一相位检测器PD200 First phase detector PD

201 第一低通滤波器LPF201 First low-pass filter LPF

202 第一压控振荡器VCO202 The first voltage-controlled oscillator VCO

203 第一除频器203 First frequency divider

300 第二相位检测器PD300 second phase detector PD

301 第二低通滤波器LPF301 second low-pass filter LPF

302 第二压控振荡器VCO302 Second voltage controlled oscillator VCO

303 第二除频器303 Second frequency divider

411、412 步骤411, 412 steps

521、522、523 步骤521, 522, 523 steps

1011 时脉信号1011 clock signal

1021 时脉信号1021 clock signal

PCM IN 脉波数量调制PCM IN信号PCM IN Pulse quantity modulation PCM IN signal

PCM OUT 脉波数量调制PCM OUT信号PCM OUT pulse quantity modulation PCM OUT signal

具体实施方式Detailed ways

图1为一系统示意图，用以显示说明本发明的时脉信号处理系统的系统架构、以及配合USB接口、数字模拟转换器DAC与模拟数字转换器ADC的运行情形。如图1中所示，时脉信号处理系统1包含USB接口100、第一级锁相回路PLL 101、第二级锁相回路PLL 102、第一先进先出FIFO缓冲区103、以及第二先进先出FIFO缓冲区104。FIG. 1 is a schematic diagram of the system, which is used to illustrate the system architecture of the clock signal processing system of the present invention, and the operation of the USB interface, the digital-to-analog converter DAC and the analog-to-digital converter ADC. As shown in FIG. 1 , the clock signal processing system 1 includes a USB interface 100, a first-stage phase-locked loop PLL 101, a second-stage phase-locked loop PLL 102, a first FIFO buffer 103, and a second advanced First out FIFO buffer 104.

第一级锁相回路PLL 101，该第一级锁相回路PLL 101输入端与USB接口100连接。USB接口100接收/传送经由USB线缆(Cable)的USB主机端(USB HOST)(未图示)输出/输入的声音数据，USB接口100会送出信息帧起始位SOF至该第一级锁相回路PLL 101输入端。USB接口100并将脉波数量调制PCM IN信号传送至第一先进先出FIFO缓冲区103、USB接口100，并接受来自于第二先进先出FIFO缓冲区104的脉波数量调制PCM OUT信号。以及，该第一级锁相回路PLL 101担任的是升频/时脉同步的角色。例如，第一级锁相回路PLL 101收到信息帧起始位SOF后，会输出49152倍时脉给第二级锁相回路PLL 102。The first stage PLL 101 , the input end of the first stage PLL 101 is connected to the USB interface 100 . The USB interface 100 receives/transmits the audio data output/input via the USB HOST (not shown) of the USB cable (Cable), and the USB interface 100 will send the information frame start bit SOF to the first-level lock Phase loop PLL 101 input. The USB interface 100 transmits the PCM IN signal to the first FIFO buffer 103 and the USB interface 100 , and receives the PCM OUT signal from the second FIFO buffer 104 . And, the first-stage phase-locked loop PLL 101 plays the role of up-conversion/clock synchronization. For example, the PLL 101 of the first stage of the phase-locked loop will output 49152 times the clock pulse to the PLL 102 of the second stage of the phase-locked loop after receiving the SOF of the information frame.

第二级锁相回路PLL 102，该第二级锁相回路PLL 102将改善所接收到的来自于该第一级锁相回路PLL的升频后的同步时脉的时脉信号1011；该第二级锁相回路PLL 102将降低该时脉信号1011的时脉抖动，然后将经时脉抖动处理后的时脉信号1021输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106；其中，第二级锁相回路PLL 102降低第一级锁相回路PLL 101的输出的时脉抖动并将其时脉抖动予以降低到20ps以下。The second-stage phase-locked loop PLL 102, the second-stage phase-locked loop PLL 102 will improve the received clock signal 1011 of the up-converted synchronous clock from the first-stage phase-locked loop PLL; The secondary phase-locked loop PLL 102 will reduce the clock jitter of the clock signal 1011, and then output the clock signal 1021 processed by the clock jitter to the digital-to-analog converter DAC 105 and the analog-to-digital converter ADC 106; wherein, The second-stage phase-locked loop PLL 102 reduces the clock jitter of the output of the first-stage phase-locked loop PLL 101 and reduces the clock jitter to below 20 ps.

第一先进先出FIFO缓冲区103，该第一先进先出FIFO缓冲区103可以为小容量的先进先出缓冲区(深度<100)，用于数字模拟转换器DAC 105暂存数据，可储存主机端(HOST)经由USB接口100所送过来的一个信息帧起始位SOF的数据(未图示)，该数据可由数字模拟转换器DAC 105来予以读取。The first FIFO buffer 103, the first FIFO buffer 103 can be a small-capacity first-in-first-out buffer (depth<100), used for digital-to-analog converter DAC 105 temporarily storing data, can store A SOF data (not shown) sent from the host (HOST) via the USB interface 100 can be read by the digital-to-analog converter DAC 105 .

第二先进先出FIFO缓冲区104，该第二先进先出FIFO缓冲区104可以为小容量的先进先出缓冲区(深度<100)，用于暂存模拟数字转换器ADC106输出的数据。经由USB接口100，通过每个信息帧起始位SOF而读取该第二先进先出FIFO缓冲区104的数据并将其传送至主机端(HOST)。The second FIFO buffer 104, which can be a small-capacity FIFO buffer (depth<100), is used to temporarily store the data output by the analog-to-digital converter ADC106. Through the USB interface 100, the data of the second FIFO buffer 104 is read and transmitted to the host (HOST) through the SOF of each information frame.

于实际施行时，本发明的时脉信号处理系统1使用第一级锁相回路PLL101、以及第二级锁相回路PLL 102，经由该第一级锁相回路PLL 101而将信息帧起始位SOF(1khz or 8khz)予以升频，获得同步时脉的另一时脉信号1011。该第二级锁相回路102将该另一时脉信号1011进行降低时脉抖动处理，以便将经时脉抖动处理后的时脉信号1021(例如，1024*48Khz)输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106，以供其使用。当稳定时，数字模拟转换器DAC 105的时脉CLK与信息帧起始位SOF同步，经由USB接口100而来的声音的音频数据也与信息帧起始位SOF同步，所以数字模拟转换器DAC 105上使用的时脉CLK与第一先进先出FIFO缓冲区103的数据(DATA)同步，而无不连续的情形。因而，第一先进先出FIFO缓冲区103只要能容纳一个信息帧起始位SOF的数据容量即可，而如此一来，经由USB接口100的USB主机端(HOST)到数字模拟转换器DAC 105的数据延迟就可以非常短。In actual implementation, the clock signal processing system 1 of the present invention uses the first-stage phase-locked loop PLL101 and the second-stage phase-locked loop PLL 102, through which the first-stage phase-locked loop PLL 101 sets the information frame start bit SOF (1khz or 8khz) is up-converted to obtain another clock signal 1011 of the synchronous clock. The second-stage phase-locked loop 102 performs clock jitter reduction processing on the other clock signal 1011, so as to output the clock signal 1021 (for example, 1024*48Khz) processed by the clock jitter to the digital-to-analog converter DAC 105 and analog-to-digital converter ADC 106 for its use. When stable, the clock pulse CLK of the digital-to-analog converter DAC 105 is synchronized with the SOF of the information frame, and the audio data of the sound coming via the USB interface 100 is also synchronized with the SOF of the information frame, so the digital-to-analog converter DAC The clock CLK used on 105 is synchronized with the data (DATA) of the first FIFO buffer 103 without discontinuity. Thereby, the first FIFO buffer 103 only needs to be able to accommodate the data capacity of an information frame start bit SOF, and in this way, the USB host terminal (HOST) of the USB interface 100 to the digital-to-analog converter DAC 105 The data latency can be very short.

于本发明的实施例中，第一级锁相回路PLL 101可包含第一相位检测器PD(PhaseDetect)、第一低通滤波器LPF、第一压控振荡器VCO、以及第一除频器(1/N)。第一相位检测器PD将信息帧起始位SOF与第一除频器(除以49152)的输出进行相位差异检测、并将进行相位差异检测后的信号传送至第一低通滤波器LPF；以及，第一低通滤波器LPF将相位差异的信号做低频滤波处理、并将其传送至第一压控振荡器VCO，第一低通滤波器LPF的设计方向为须能接受极低频(低至1Khz)的输入。In an embodiment of the present invention, the first-stage phase-locked loop PLL 101 may include a first phase detector PD (PhaseDetect), a first low-pass filter LPF, a first voltage-controlled oscillator VCO, and a first frequency divider (1/N). The first phase detector PD performs phase difference detection with the output of the information frame start bit SOF and the first frequency divider (divided by 49152), and sends the signal after the phase difference detection to the first low-pass filter LPF; And, the first low-pass filter LPF performs low-frequency filtering processing on the signal of the phase difference, and transmits it to the first voltage-controlled oscillator VCO. The design direction of the first low-pass filter LPF must be able to accept extremely low frequencies (low to 1Khz) input.

另，于本发明的实施例中，第二级锁相回路PLL可包含第二相位检测器PD(PhaseDetect)、第二低通滤波器LPF、第二压控振荡器VCO、以及第二除频器(1/2)；第二相位检测器PD将比较来自于第一级锁相回路PLL101的经升频后的同步时脉的该另一时脉信号1011、以及第二压控振荡器VCO的输出、并送至第二低通滤波器LPF，第二低通滤波器LPF的设计方向跟第一低通滤波器LPF不一样，为了降低第一级锁相回路PLL输出的经升频后的同步时脉的该另一时脉信号1011的时脉抖动，需要将第二低通滤波器LPF设计在过阻尼状态，而稳定时间设计为数ms；以及，第二压控振荡器VCO的输出将传送至第二除频器(1/2)，而第二除频器将进行除2处理，第二除频器作责任周期调整以便将信号输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106，以供其使用。In addition, in the embodiment of the present invention, the second-stage phase-locked loop PLL may include a second phase detector PD (PhaseDetect), a second low-pass filter LPF, a second voltage-controlled oscillator VCO, and a second frequency divider device (1/2); the second phase detector PD will compare the other clock signal 1011 of the up-converted synchronous clock from the first-stage phase-locked loop PLL101, and the second voltage-controlled oscillator VCO Output and sent to the second low-pass filter LPF, the design direction of the second low-pass filter LPF is different from that of the first low-pass filter LPF, in order to reduce the up-converted output of the first-stage phase-locked loop PLL The clock jitter of the other clock signal 1011 of the synchronous clock needs to design the second low-pass filter LPF in an over-damped state, and the settling time is designed to be several ms; and the output of the second voltage-controlled oscillator VCO will transmit to the second frequency divider (1/2), and the second frequency divider will divide by 2, and the second frequency divider will adjust the duty cycle so as to output the signal to the digital-to-analog converter DAC 105 and the analog-to-digital converter ADC 106 for its use.

图2为一流程图，用以显示说明利用如图1中的本发明的时脉信号处理系统以进行时脉信号处理方法的流程步骤。FIG. 2 is a flow chart for illustrating the process steps of the clock signal processing method using the clock signal processing system of the present invention as shown in FIG. 1 .

如图2中所示，首先，于步骤31，进行升频动作；经由USB接口100，利用第一级锁相回路PLL 101将所输入的通用串行总线USB信息帧起始位SOF频率予以提升，获得升频后的时脉同步的另一时脉信号1011，并输出至第二级锁相回路PLL 102，并进到步骤32。As shown in Fig. 2, at first, in step 31, carry out the up-conversion action; Via USB interface 100, utilize the first-stage phase-locked circuit PLL 101 to improve the frequency of the input universal serial bus USB information frame start bit SOF , obtain another clock signal 1011 synchronized with the up-converted clock, and output it to the second-stage phase-locked loop PLL 102 , and proceed to step 32 .

在此，其中，该第一级锁相回路PLL 101收到信息帧起始位SOF后，例如，会输出49152倍时脉给第二级锁相回路PLL 102，该第一级锁相回路PLL 101担任的是升频/时脉同步的角色。Here, after the first-stage phase-locked loop PLL 101 receives the information frame start bit SOF, for example, it will output 49152 times the clock pulse to the second-stage phase-locked loop PLL 102, and the first-stage phase-locked loop PLL 101 plays the role of frequency up/clock synchronization.

于步骤32，进行时脉抖动处理动作；利用第二级锁相回路PLL 102降低第一级锁相回路PLL输出的该另一时脉信号1011的时脉抖动并将其时脉抖动予以降低到20ps以下。In step 32, the clock jitter processing action is performed; the second-stage PLL 102 is used to reduce the clock jitter of the other clock signal 1011 output by the first-stage PLL and reduce the clock jitter to 20 ps the following.

在此，其中，该第二级锁相回路PLL 102将改善所接收到的来自于该第一级锁相回路PLL 101的升频后的同步时脉的时脉信号1011；该第二级锁相回路PLL 102将降低该另一时脉信号1011的时脉抖动，然后将经时脉抖动处理后的时脉信号1021输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106；以及，第二级锁相回路PLL 102降低第一级锁相回路PLL 101输出的时脉抖动并将其时脉抖动予以降低到20ps以下。Here, the second-stage PLL 102 will improve the received clock signal 1011 of the up-converted synchronous clock from the first-stage PLL 101; the second-stage lock The phase loop PLL 102 will reduce the clock jitter of the other clock signal 1011, and then output the clock signal 1021 processed by the clock jitter to the digital-to-analog converter DAC 105 and the analog-to-digital converter ADC 106; and, the second The first-stage phase-locked loop PLL 102 reduces the clock jitter output by the first-stage phase-locked loop PLL 101 and reduces the clock jitter to less than 20 ps.

图3为一示意图，用以显示说明本发明的时脉信号处理系统的一实施例的架构、以及配合USB接口、数字模拟转换器DAC与模拟数字转换器ADC的运行情形。如图3中所示，时脉信号处理系统1包含第一级锁相回路PLL 101、第二级锁相回路PLL 102、第一先进先出FIFO缓冲区103、以及第二先进先出FIFO缓冲区104。FIG. 3 is a schematic diagram for illustrating the structure of an embodiment of the clock signal processing system of the present invention, and the operation of the USB interface, the digital-to-analog converter DAC and the analog-to-digital converter ADC. As shown in FIG. 3 , the clock signal processing system 1 includes a first-stage phase-locked loop PLL 101, a second-stage phase-locked loop PLL 102, a first FIFO buffer 103, and a second FIFO buffer District 104.

第一级锁相回路PLL 101，该第一级锁相回路PLL 101输入端与USB接口100连接，USB接口100接收/传送经由USB线缆(Cable)的USB主机端(USB HOST)(未图示)输出/输入的声音数据，USB接口100会送出信息帧起始位SOF(例如，1khz或8khz)至该第一级锁相回路PLL101输入端，USB接口100并将脉波数量调制PCM IN信号传送至第一先进先出FIFO缓冲区103，USB接口100并接受来自于第二先进先出FIFO缓冲区104的脉波数量调制PCM OUT信号；以及，该第一级锁相回路PLL 101收到信息帧起始位SOF(例如，1khz或8khz)后，会输出，例如，1024*48khz时脉，给第二级锁相回路PLL 102，该第一级锁相回路PLL 101担任的是升频/时脉同步的角色。The first-stage phase-locked loop PLL 101, the input end of the first-stage phase-locked loop PLL 101 is connected to the USB interface 100, and the USB interface 100 receives/transmits the USB host terminal (USB HOST) (not shown in the figure) via the USB cable (Cable). Shown) output/input sound data, USB interface 100 will send information frame start bit SOF (for example, 1khz or 8khz) to the input terminal of the first-stage phase-locked loop PLL101, USB interface 100 and pulse number modulation PCM IN The signal is sent to the first FIFO buffer 103, and the USB interface 100 receives the pulse quantity modulation PCM OUT signal from the second FIFO buffer 104; and, the first-stage phase-locked loop PLL 101 receives After the information frame start bit SOF (for example, 1khz or 8khz), it will output, for example, a 1024*48khz clock pulse to the second-stage phase-locked loop PLL 102, and the first-stage phase-locked loop PLL 101 is responsible for raising The role of frequency/clock synchronization.

第二级锁相回路PLL 102，该第二级锁相回路PLL 102将改善所接收到的来自于该第一级锁相回路PLL的升频后的同步时脉的该另一时脉信号1011；该第二级锁相回路PLL 102将降低该时脉信号1011的时脉抖动，然后将经时脉抖动处理后的时脉信号1021(例如，经除2处理后的512*48khz)输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106；其中，第二级锁相回路PLL 102降低第一级锁相回路PLL 101的输出的时脉抖动并将其时脉抖动予以降低到20ps以下。The second-stage phase-locked loop PLL 102, the second-stage phase-locked loop PLL 102 will improve the received another clock signal 1011 of the up-converted synchronous clock from the first-stage phase-locked loop PLL; The second-stage phase-locked loop PLL 102 will reduce the clock jitter of the clock signal 1011, and then output the clock signal 1021 processed by the clock jitter (for example, 512*48khz after dividing by 2) to the digital The analog converter DAC 105 and the analog-to-digital converter ADC 106; wherein, the second-stage phase-locked loop PLL 102 reduces the clock jitter of the output of the first-stage phase-locked loop PLL 101 and reduces the clock jitter to below 20 ps.

第一先进先出FIFO缓冲区103，该第一先进先出FIFO缓冲区103可以是小容量的先进先出缓冲区(深度<100)，用于数字模拟转换器DAC 105暂存数据，可储存主机端(HOST)经由USB接口100所送过来的一个信息帧起始位SOF的数据(未图示)，该数据可由数字模拟转换器DAC 105来予以读取。The first FIFO buffer 103, the first FIFO buffer 103 can be a small-capacity FIFO buffer (depth<100), used for digital-to-analog converter DAC 105 temporarily storing data, can store A SOF data (not shown) sent from the host (HOST) via the USB interface 100 can be read by the digital-to-analog converter DAC 105 .

第二先进先出FIFO缓冲区104，该第二先进先出FIFO缓冲区104可以是小容量的先进先出缓冲区(深度<100)，用于暂存模拟数字转换器ADC 106输出的数据。经由USB接口100，通过每个信息帧起始位SOF而读取该第二先进先出FIFO缓冲区104的数据并将其传送至主机端(HOST)。The second FIFO buffer 104, which may be a small-capacity FIFO buffer (depth<100), is used to temporarily store the data output by the analog-to-digital converter ADC 106 . Through the USB interface 100, the data of the second FIFO buffer 104 is read and transmitted to the host (HOST) through the SOF of each information frame.

于实际施行时，本发明的时脉信号处理系统1使用第一级锁相回路PLL 101、以及第二级锁相回路PLL 102，经由该第一级锁相回路PLL 101而将信息帧起始位SOF(1khz or8khz)予以升频，获得升频后的时脉同步的另一时脉信号，该第二级锁相回路102将该另一时脉信号1011进行降低时脉抖动处理，以便将经时脉抖动处理后的时脉信号1021(例如，512*48K hz)输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106，以供其使用。当稳定时，数字模拟转换器DAC 105的时脉CLK与信息帧起始位SOF同步，经由USB接口100而来的声音的音频数据亦与信息帧起始位SOF同步，所以数字模拟转换器DAC 105上使用的时脉CLK与第一先进先出FIFO缓冲区103的数据(DATA)同步，而无不连续的情形。因而，第一先进先出FIFO缓冲区103只要能容纳一个信息帧起始位SOF的数据容量即可，而如此一来，经由USB接口100的USB主机端(HOST)到数字模拟转换器DAC 105的数据延迟就可以非常短。In actual implementation, the clock signal processing system 1 of the present invention uses the first-stage phase-locked loop PLL 101 and the second-stage phase-locked loop PLL 102, through which the first-stage phase-locked loop PLL 101 starts the information frame Bit SOF (1khz or 8khz) is up-converted to obtain another clock signal synchronized with the up-converted clock, and the second-stage phase-locked loop 102 processes the other clock signal 1011 to reduce the clock jitter, so that the time-lapse The dithered clock signal 1021 (for example, 512*48K Hz) is output to the digital-to-analog converter DAC 105 and the analog-to-digital converter ADC 106 for their use. When stable, the clock pulse CLK of the digital-to-analog converter DAC 105 is synchronized with the SOF of the information frame, and the audio data of the sound coming from the USB interface 100 is also synchronized with the SOF of the information frame, so the digital-to-analog converter DAC The clock CLK used on 105 is synchronized with the data (DATA) of the first FIFO buffer 103 without discontinuity. Thereby, the first FIFO buffer 103 only needs to be able to accommodate the data capacity of an information frame start bit SOF, and in this way, the USB host terminal (HOST) of the USB interface 100 to the digital-to-analog converter DAC 105 The data latency can be very short.

图4为一示意图，用以显示说明于图3的实施例中的第一级锁相回路PLL的结构。FIG. 4 is a schematic diagram for showing the structure of the first-stage phase-locked loop PLL in the embodiment illustrated in FIG. 3 .

于本实施例中，第一级锁相回路PLL 101可包含第一相位检测器PD(Phase Detect)200、第一低通滤波器LPF 201、第一压控振荡器VCO 202、以及第一除频器(1/N)203；第一相位检测器PD 200将信息帧起始位SOF跟第一除频器(除以N)的输出进行相位差异检测，并将进行相位差异检测后的信号传送至第一低通滤波器LPF 201，以及，第一低通滤波器LPF201将相位差异的信号做低频滤波处理，并传送至第一压控振荡器VCO 202，而第一压控振荡器VCO 202会将其传送至第一除频器203与第二级锁相回路PLL 102(例如，1024*48khz时脉)，其中，第一低通滤波器LPF 201的设计方向为须能接受极低频(低至1Khz)的输入。In this embodiment, the first-stage phase-locked loop PLL 101 may include a first phase detector PD (Phase Detect) 200, a first low-pass filter LPF 201, a first voltage-controlled oscillator VCO 202, and a first divider frequency converter (1/N) 203; the first phase detector PD 200 performs phase difference detection with the output of the information frame start bit SOF and the first frequency divider (divided by N), and performs the signal after the phase difference detection sent to the first low-pass filter LPF 201, and the first low-pass filter LPF201 performs low-frequency filtering processing on the phase difference signal, and sends it to the first voltage-controlled oscillator VCO 202, and the first voltage-controlled oscillator VCO 202 will send it to the first frequency divider 203 and the second-stage phase-locked loop PLL 102 (for example, 1024*48khz clock pulse), wherein, the design direction of the first low-pass filter LPF 201 must be able to accept extremely low frequency (down to 1Khz) input.

图5为一流程图，用以显示说明利用如图3中的本发明的时脉信号处理系统的实施例以进行时脉信号处理方法的一流程步骤。FIG. 5 is a flow chart for illustrating a process step of a clock signal processing method using the clock signal processing system of the present invention as shown in FIG. 3 .

如图5中所示，首先，于步骤41，进行升频动作；经由USB接口100，As shown in Fig. 5, at first, in step 41, carry out frequency up-conversion action; Via USB interface 100,

利用第一级锁相回路PLL 101将所输入的通用串行总线USB信息帧起始位SOF频率予以提升，提供时脉同步的时脉信号1011，并输出至第二级锁相回路PLL 102，并进到步骤42。Utilize the first-stage phase-locked loop PLL 101 to increase the frequency of the input universal serial bus USB information frame start bit SOF, provide a clock-synchronized clock signal 1011, and output it to the second-stage phase-locked loop PLL 102, And go to step 42.

在此，其中，该第一级锁相回路PLL 101担任的是升频/时脉同步的角色。该第一级锁相回路PLL 101收到信息帧起始位SOF后，例如，1khz或8khz，会输出1024*48khz时脉给第二级锁相回路PLL 102。Herein, the first-stage phase-locked loop PLL 101 plays the role of frequency up/clock synchronization. After the first-stage PLL 101 receives the SOF of the information frame, for example, 1khz or 8khz, it will output a 1024*48khz clock to the second-stage PLL 102 .

于步骤42，进行时脉抖动处理动作，利用第二级锁相回路PLL 102降低第一级锁相回路PLL的输出的时脉信号1011的时脉抖动并将其时脉抖动予以降低到20ps以下。In step 42, the clock jitter processing action is performed, and the clock jitter of the clock signal 1011 output by the first-stage phase-locked loop PLL is reduced by the second-stage phase-locked loop PLL 102 and the clock jitter is reduced to below 20 ps .

在此，其中，该第二级锁相回路PLL 102将改善所接收到的来自于该第一级锁相回路PLL 101的升频后的同步时脉的另一时脉信号1011，例如，1024*48k hz时脉信号。该第二级锁相回路PLL 102将降低该另一时脉信号1011的时脉抖动，然后将经时脉抖动处理后的时脉信号1021，例如，512*48khz时脉信号，输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106。以及，第二级锁相回路PLL 102降低第一级锁相回路PLL 101输出的时脉抖动并将其时脉抖动予以降低到20ps以下。Here, the second stage PLL 102 will improve another clock signal 1011 received from the up-converted synchronous clock from the first stage PLL 101, for example, 1024* 48k hz clock signal. The second phase-locked loop PLL 102 will reduce the clock jitter of the other clock signal 1011, and then output the clock signal 1021 processed by the clock jitter, for example, a 512*48khz clock signal, to the digital-to-analog converter converter DAC 105 and analog-to-digital converter ADC 106. And, the second-stage phase-locked loop PLL 102 reduces the clock jitter output by the first-stage phase-locked loop PLL 101 and reduces the clock jitter to below 20 ps.

图6为一流程图，用以显示说明利用如图5中的时脉信号处理方法的进行升频动作步骤的更详细程序。FIG. 6 is a flow chart showing a more detailed procedure for performing up-conversion steps using the clock signal processing method as in FIG. 5 .

首先，于步骤411，进行相位差异检测；第一相位检测器PD 200将信息帧起始位SOF(例如，1khz或8khz)与第一除频器(除以N)203的输出进行相位差异检测，并将进行相位差异检测后的信号传送至第一低通滤波器LPF 201，并进到步骤412。First, in step 411, phase difference detection is performed; the first phase detector PD 200 performs phase difference detection on the information frame start bit SOF (for example, 1khz or 8khz) and the output of the first frequency divider (divided by N) 203 , and transmit the signal after phase difference detection to the first low-pass filter LPF 201 , and proceed to step 412 .

于步骤412，进行低频滤波处理；第一低通滤波器LPF 201将相位差异的信号作低频滤波处理，并传送至第一压控振荡器VCO 202，而第一压控振荡器VCO 202会将其传送至第一除频器203与第二级锁相回路PLL 102(例如，1024*48khz时脉)，其中，第一低通滤波器LPF201的设计方向为须能接受极低频(低至1Khz)的输入。In step 412, low-frequency filtering processing is performed; the first low-pass filter LPF 201 performs low-frequency filtering processing on the phase difference signal, and transmits it to the first voltage-controlled oscillator VCO 202, and the first voltage-controlled oscillator VCO 202 will It is transmitted to the first frequency divider 203 and the second-stage phase-locked loop PLL 102 (for example, 1024*48khz clock), wherein, the design direction of the first low-pass filter LPF201 must be able to accept extremely low frequencies (down to 1Khz )input of.

图7为一示意图，用以显示说明本发明的时脉信号处理系统的另一实施例的架构、以及配合USB接口、数字模拟转换器DAC与模拟数字转换器ADC的运行情形。如图7中所示，时脉信号处理系统1包含USB接口100、第一级锁相回路PLL 101、第二级锁相回路PLL 102、第一先进先出FIFO缓冲区103、以及第二先进先出FIFO缓冲区104。FIG. 7 is a schematic diagram for illustrating the architecture of another embodiment of the clock signal processing system of the present invention, and the operation of the USB interface, the digital-to-analog converter DAC and the analog-to-digital converter ADC. As shown in FIG. 7 , the clock signal processing system 1 includes a USB interface 100, a first-stage phase-locked loop PLL 101, a second-stage phase-locked loop PLL 102, a first FIFO buffer 103, and a second advanced First out FIFO buffer 104.

第一级锁相回路PLL 101，该第一级锁相回路PLL 101输入端与USB接口100连接，USB接口100接收/传送经由USB线缆(Cable)的USB主机端(USB HOST)(未图示)输出/输入的声音数据，USB接口100会送出信息帧起始位SOF(例如，1khz或8khz)至该第一级锁相回路PLL101输入端，USB接口100并将脉波数量调制PCM IN信号传送至第一先进先出FIFO缓冲区103，USB接口100并接受来自于第二先进先出FIFO缓冲区104的脉波数量调制PCM OUT信号，以及，该第一级锁相回路PLL 101收到信息帧起始位SOF(例如，1khz或8khz)后，会输出，例如，1024*48khz时脉，给第二级锁相回路PLL 102，该第一级锁相回路PLL 101担任的是升频/时脉同步的角色。The first-stage phase-locked loop PLL 101, the input end of the first-stage phase-locked loop PLL 101 is connected to the USB interface 100, and the USB interface 100 receives/transmits the USB host terminal (USB HOST) (not shown in the figure) via the USB cable (Cable). Shown) output/input sound data, USB interface 100 will send information frame start bit SOF (for example, 1khz or 8khz) to the input terminal of the first-stage phase-locked loop PLL101, USB interface 100 and pulse number modulation PCM IN The signal is sent to the first FIFO buffer 103, and the USB interface 100 receives the pulse quantity modulation PCM OUT signal from the second FIFO buffer 104, and the first-stage phase-locked loop PLL 101 receives After the information frame start bit SOF (for example, 1khz or 8khz), it will output, for example, a 1024*48khz clock pulse to the second-stage phase-locked loop PLL 102, and the first-stage phase-locked loop PLL 101 is responsible for raising The role of frequency/clock synchronization.

第二级锁相回路PLL 102，该第二级锁相回路PLL 102将改善所接收到的来自于该第一级锁相回路PLL的升频后的同步时脉的该另一时脉信号1011；该第二级锁相回路PLL 102将降低该另一时脉信号1011的时脉抖动，然后将经时脉抖动处理后的时脉信号1021(例如，经除2处理后的512*48khz)输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106；其中，第二级锁相回路PLL 102降低第一级锁相回路PLL 101的输出的时脉抖动并将其时脉抖动予以降低到20ps以下。The second-stage phase-locked loop PLL 102, the second-stage phase-locked loop PLL 102 will improve the received another clock signal 1011 of the up-converted synchronous clock from the first-stage phase-locked loop PLL; The second-stage phase-locked loop PLL 102 will reduce the clock jitter of the other clock signal 1011, and then output the clock signal 1021 processed by the clock jitter (for example, 512*48khz after dividing by 2) to Digital-to-analog converter DAC 105 and analog-to-digital converter ADC 106; wherein, the second-stage phase-locked loop PLL 102 reduces the clock jitter of the output of the first-stage phase-locked loop PLL 101 and reduces the clock jitter to below 20ps .

第一先进先出FIFO缓冲区103，该第一先进先出FIFO缓冲区103可以是小容量的先进先出缓冲区(深度<100)，用于数字模拟转换器DAC 105暂存数据。可储存主机端(HOST)经由USB接口100所送过来的一个信息帧起始位SOF的数据(未图示)，该数据可由数字模拟转换器DAC 105来予以读取。The first FIFO buffer 103 , the first FIFO buffer 103 may be a small-capacity FIFO buffer (depth<100), used for the digital-to-analog converter DAC 105 to temporarily store data. Data (not shown) of a SOF sent by the host (HOST) via the USB interface 100 can be stored, and the data can be read by the digital-to-analog converter DAC 105 .

第二先进先出FIFO缓冲区104，该第二先进先出FIFO缓冲区104可以是小容量的先进先出缓冲区(深度<100)，用于暂存模拟数字转换器ADC 106输出的数据。经由USB接口100，通过每个信息帧起始位SOF而读取该第二先进先出FIFO缓冲区104的数据并将其传送至主机端(HOST)。The second FIFO buffer 104, which may be a small-capacity FIFO buffer (depth<100), is used to temporarily store the data output by the analog-to-digital converter ADC 106 . Through the USB interface 100, the data of the second FIFO buffer 104 is read and transmitted to the host (HOST) through the SOF of each information frame.

于实际施行时，本发明的时脉信号处理系统1使用第一级锁相回路PLL 101、以及第二级锁相回路PLL 102，经由该第一级锁相回路PLL 101而将信息帧起始位SOF(1khz or8khz)予以升频，获得另一时脉信号1011，该第二级锁相回路102将该另一时脉信号1011进行降低时脉抖动处理，以便将经时脉抖动处理后的时脉信号1021(例如，512*48K hz)输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106，以供其使用。当稳定时，数字模拟转换器DAC 105的时脉CLK与信息帧起始位SOF同步，经由USB接口100而来的声音的音频数据亦与信息帧起始位SOF同步，所以数字模拟转换器DAC 105上使用的时脉CLK与第一先进先出FIFO缓冲区103的数据(DATA)同步，而无不连续的情形。因而，第一先进先出FIFO缓冲区103只要能容纳一个信息帧起始位SOF的数据容量即可，而如此一来，经由USB接口100的USB主机端(HOST)到数字模拟转换器DAC 105的数据延迟就可以非常短。In actual implementation, the clock signal processing system 1 of the present invention uses the first-stage phase-locked loop PLL 101 and the second-stage phase-locked loop PLL 102, through which the first-stage phase-locked loop PLL 101 starts the information frame Bit SOF (1khz or 8khz) is up-converted to obtain another clock signal 1011, and the second-stage phase-locked loop 102 processes the other clock signal 1011 to reduce clock jitter, so that the clock after clock jitter processing The signal 1021 (for example, 512*48K hz) is output to the digital-to-analog converter DAC 105 and the analog-to-digital converter ADC 106 for their use. When stable, the clock pulse CLK of the digital-to-analog converter DAC 105 is synchronized with the SOF of the information frame, and the audio data of the sound coming from the USB interface 100 is also synchronized with the SOF of the information frame, so the digital-to-analog converter DAC The clock CLK used on 105 is synchronized with the data (DATA) of the first FIFO buffer 103 without discontinuity. Thereby, the first FIFO buffer 103 only needs to be able to accommodate the data capacity of an information frame start bit SOF, and in this way, the USB host terminal (HOST) of the USB interface 100 to the digital-to-analog converter DAC 105 The data latency can be very short.

图8为一示意图，用以显示说明于图7的实施例中的第一级锁相回路PLL的结构。FIG. 8 is a schematic diagram for showing the structure of the first-stage phase-locked loop PLL in the embodiment illustrated in FIG. 7 .

于本实施例中，第二级锁相回路PLL 102可包含第二相位检测器PD(Phase Detect)300、第二低通滤波器LPF 301、第二压控振荡器VCO 302、以及第二除频器(1/2)303；第二相位检测器PD 300将比较来自于第一级锁相回路PLL 101的经升频后的同步时脉的该另一时脉信号1011、以及第二压控振荡器VCO 302的输出进行相位差异检测，并将进行相位差异检测后的信号传送至第二低通滤波器LPF 301。第二低通滤波器LPF 301的设计方向跟第一低通滤波器LPF 201不一样，是为了降低第一级锁相回路PLL 101输出的经升频后的同步时脉的时脉信号1011的时脉抖动，需要将第二低通滤波器LPF 301设计在过阻尼状态，而稳定时间设计为数ms；以及，第二压控振荡器VCO 302的输出将传送至第二除频器(1/2)303，而第二除频器303将进行除2处理，第二除频器303作责任周期调整以便将信号输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106，以供其使用。In this embodiment, the second-stage phase-locked loop PLL 102 may include a second phase detector PD (Phase Detect) 300, a second low-pass filter LPF 301, a second voltage-controlled oscillator VCO 302, and a second divider frequency converter (1/2) 303; the second phase detector PD 300 will compare the other clock signal 1011 of the up-converted synchronous clock from the first-stage phase-locked loop PLL 101, and the second voltage-controlled The output of the oscillator VCO 302 is subjected to phase difference detection, and the signal after the phase difference detection is sent to the second low-pass filter LPF 301 . The design direction of the second low-pass filter LPF 301 is different from that of the first low-pass filter LPF 201. clock jitter, the second low-pass filter LPF 301 needs to be designed in an over-damped state, and the settling time is designed to be several ms; and the output of the second voltage-controlled oscillator VCO 302 will be sent to the second frequency divider (1/ 2) 303, and the second frequency divider 303 will divide by 2, and the second frequency divider 303 will adjust the duty cycle so as to output the signal to the digital-to-analog converter DAC 105 and the analog-to-digital converter ADC 106 for their use .

换言之，第二级锁相回路PLL 102的处理流程为，首先，进行相位差异检测；第二相位检测器PD 300将比较来自于第一级锁相回路PLL 101的经升频后的同步时脉的该另一时脉信号1011(例如，1024*48k hz)、以及第二压控振荡器VCO 302的输出进行相位差异检测，并将进行相位差异检测后的信号传送至第二低通滤波器LPF 301。In other words, the processing flow of the second-stage phase-locked loop PLL 102 is as follows: first, phase difference detection is performed; the second phase detector PD 300 will compare the up-converted synchronous clock from the first-stage phase-locked loop PLL 101 The other clock signal 1011 (for example, 1024*48k Hz) and the output of the second voltage-controlled oscillator VCO 302 perform phase difference detection, and the signal after the phase difference detection is sent to the second low-pass filter LPF 301.

继而，进行低通滤波处理；第二低通滤波器LPF 301将相位差异的信号做低频滤波处理、并传送至第二压控振荡器VCO 302，而第二压控振荡器VCO 302会将其，例如，1024*48khz时脉信号，传送至第二除频器(1/2)303与第二相位检测器PD 300；其中，第二低通滤波器LPF 301的设计方向跟第一低通滤波器LPF 201不一样，是为了降低第一级锁相回路PLL101输出的经升频后的同步时脉的该另一时脉信号1011的时脉抖动，需要将第二低通滤波器LPF 301设计在过阻尼状态，而稳定时间设计为数ms。Then, perform low-pass filter processing; the second low-pass filter LPF 301 performs low-frequency filter processing on the phase difference signal, and transmits it to the second voltage-controlled oscillator VCO 302, and the second voltage-controlled oscillator VCO 302 will convert it to , for example, a 1024*48khz clock signal is sent to the second frequency divider (1/2) 303 and the second phase detector PD 300; wherein, the design direction of the second low-pass filter LPF 301 is the same as that of the first low-pass The filter LPF 201 is different, in order to reduce the clock pulse jitter of the other clock signal 1011 of the up-converted synchronous clock output by the first-stage phase-locked loop PLL101, the second low-pass filter LPF 301 needs to be designed In the over-damped state, the settling time is designed to be several milliseconds.

接着，进行除频处理；第二压控振荡器VCO 302的输出，例如，1024*48khz时脉信号，将传送至第二除频器(1/2)303，而第二除频器303将进行除2处理，第二除频器303做责任周期调整以便将时脉信号1021，例如，512*48k hz时脉信号，输出至数字模拟转换器DAC 105与模拟数字转换器ADC 106以供其使用。Next, perform frequency division processing; the output of the second voltage-controlled oscillator VCO 302, for example, a 1024*48khz clock signal, will be sent to the second frequency divider (1/2) 303, and the second frequency divider 303 will To perform division by 2, the second frequency divider 303 adjusts the duty cycle so that the clock signal 1021, for example, a 512*48k Hz clock signal, is output to the digital-to-analog converter DAC 105 and the analog-to-digital converter ADC 106 for other use.

图9为一流程图，用以显示说明利用如图7中的本发明的时脉信号处理系统的另一实施例以进行时脉信号处理方法的另一流程步骤。FIG. 9 is a flow chart for illustrating another process step of a clock signal processing method using another embodiment of the clock signal processing system of the present invention as shown in FIG. 7 .

如图9中所示，首先，于步骤51，进行升频动作；经由USB接口100，利用第一级锁相回路PLL 101将所输入的通用串行总线USB信息帧起始位SOF频率予以提升，获得升频后的时脉同步的另一时脉信号1011，并输出至第二级锁相回路PLL 102，并进到步骤52。As shown in Figure 9, at first, in step 51, the up-frequency action is performed; through the USB interface 100, the frequency of the input universal serial bus USB information frame start bit SOF is increased by using the first-stage phase-locked loop PLL 101 , obtain another clock signal 1011 synchronized with the up-converted clock, and output it to the second-stage phase-locked loop PLL 102 , and proceed to step 52 .

在此，其中，该第一级锁相回路PLL 101收到信息帧起始位SOF后，例如，1khz或8khz，会输出，例如，1024*48khz时脉给第二级锁相回路PLL102，该第一级锁相回路PLL 101担任的是升频/时脉同步的角色。Here, after the first-stage phase-locked loop PLL 101 receives the SOF of the information frame, for example, 1khz or 8khz, it will output, for example, a 1024*48khz clock to the second-stage phase-locked loop PLL102, the The first-stage phase-locked loop PLL 101 plays the role of frequency up/clock synchronization.

于步骤52，进行时脉抖动处理动作；利用第二级锁相回路PLL 102降低第一级锁相回路PLL的输出的升频后的时脉同步的另一时脉信号1011的时脉抖动，并将其时脉抖动予以降低到20ps以下。In step 52, the clock jitter processing action is performed; the second-stage PLL 102 is used to reduce the clock jitter of another clock signal 1011 synchronized with the up-converted clock output of the first-stage PLL, and Reduce its clock jitter to below 20ps.

在此，其中，该第二级锁相回路PLL 102将改善所接收到的来自于该第一级锁相回路PLL 101的升频后的同步时脉的时脉信号1011，例如，1024*48khz时脉信号；该第二级锁相回路PLL 102将降低该时脉信号1011的时脉抖动，然后将经时脉抖动处理后的时脉信号1021，例如，512*48khz时脉信号，输出至数字模拟转换器DAC 105与模拟数字转换器ADC106；以及，第二级锁相回路PLL 102降低第一级锁相回路PLL 101输出的时脉抖动并将其时脉抖动予以降低到20ps以下。Here, the second-stage PLL 102 will improve the received clock signal 1011 of the up-converted synchronous clock from the first-stage PLL 101 , for example, 1024*48khz Clock signal; the second-stage phase-locked loop PLL 102 will reduce the clock jitter of the clock signal 1011, and then output the clock signal 1021 processed by the clock jitter, for example, a 512*48khz clock signal, to The digital-to-analog converter DAC 105 and the analog-to-digital converter ADC106 ; and the second-stage phase-locked loop PLL 102 reduces the clock jitter output by the first-stage phase-locked loop PLL 101 to less than 20 ps.

图10为一流程图，用以显示说明利用如图9中方时脉信号处理方法的进行时脉抖动处理动作步骤的更详细程序。FIG. 10 is a flow chart for illustrating a more detailed procedure for performing clock jitter processing using the clock signal processing method as shown in FIG. 9 .

首先，于步骤521，进行相位差异检测；第二相位检测器PD 300将比较来自于第一级锁相回路PLL 101的经升频后的同步时脉的该另一时脉信号1011(例如，1024*48k hz)、以及第二压控振荡器VCO 302的输出进行相位差异检测、并将进行相位差异检测后的信号传送至第二低通滤波器LPF301，并进到步骤522。First, in step 521, phase difference detection is performed; the second phase detector PD 300 will compare the other clock signal 1011 (for example, 1024 *48k hz), and the output of the second voltage-controlled oscillator VCO 302 for phase difference detection, and the signal after the phase difference detection is sent to the second low-pass filter LPF301, and proceeds to step 522.

于步骤522，进行低通滤波处理；第二低通滤波器LPF 301将相位差异的信号做低频滤波处理、并传送至第二压控振荡器VCO 302，而第二压控振荡器VCO 302会将其，例如，1024*48k hz时脉信号，传送至第二除频器(1/2)303与第二相位检测器PD 300，并进到步骤523；其中，第二低通滤波器LPF 301的设计方向跟第一低通滤波器LPF 201不一样，是为了降低第一级锁相回路PLL 101输出的经升频后的同步时脉的该另一时脉信号1011的时脉抖动，需要将第二低通滤波器LPF 301设计在过阻尼状态，而稳定时间设计为数ms。In step 522, low-pass filter processing is performed; the second low-pass filter LPF 301 performs low-frequency filter processing on the phase difference signal and transmits it to the second voltage-controlled oscillator VCO 302, and the second voltage-controlled oscillator VCO 302 will Send it, for example, a 1024*48k hz clock signal to the second frequency divider (1/2) 303 and the second phase detector PD 300, and proceed to step 523; wherein, the second low-pass filter LPF 301 The design direction of the first low-pass filter LPF 201 is different from that of the first low-pass filter LPF 201, in order to reduce the clock jitter of the other clock signal 1011 of the up-converted synchronous clock output by the first-stage phase-locked loop PLL 101. The second low-pass filter LPF 301 is designed to be in an over-damped state, and the settling time is designed to be several milliseconds.

于步骤523，进行除频处理；第二压控振荡器VCO 302的输出，例如，1024*48k hz时脉信号，将传送至第二除频器(1/2)303，而第二除频器303将进行除2处理，第二除频器303作责任周期调整以便将时脉信号1021，例如，512*48k hz时脉信号，输出至数字模拟转换器DAC105与模拟数字转换器ADC 106，以供其使用。In step 523, frequency division processing is performed; the output of the second voltage-controlled oscillator VCO 302, for example, a 1024*48k hz clock signal, will be sent to the second frequency divider (1/2) 303, and the second frequency divider The frequency divider 303 will divide by 2, and the second frequency divider 303 will adjust the duty cycle so as to output the clock signal 1021, for example, a 512*48k hz clock signal, to the digital-to-analog converter DAC105 and the analog-to-digital converter ADC 106, for its use.

综合以上的所述实施例，我们可以得到本发明的一种时脉信号处理系统及其方法，应用于通用串行总线USB音频同步模式(synchronous mode)声音时脉重建的环境中，利用本发明的时脉信号处理系统以进行时脉信号处理方法时，首先，利用第一级锁相回路PLL(Phase-Locked Loops)将所输入的通用串行总线USB信息帧起始位SOF(SOF,Start OfFrame)频率予以提升，获得升频后的时脉同步的另一时脉信号，并输出至第二级锁相回路；接着，利用第二级锁相回路PLL降低第一级锁相回路的输出的时脉抖动(Timing Jitter)并将其时脉抖动予以降低到20ps以下。本发明的时脉信号处理系统及方法包含以下优点：Combining the above described embodiments, we can obtain a clock signal processing system and method thereof of the present invention, which is applied to the environment of universal serial bus USB audio synchronous mode (synchronous mode) sound clock reconstruction, using the present invention When carrying out the clock signal processing method in the clock signal processing system, at first, utilize the first-stage phase-locked loop PLL (Phase-Locked Loops) to input the universal serial bus USB information frame start bit SOF (SOF, Start OfFrame) frequency is promoted to obtain another clock signal synchronized with the clock pulse after the up-conversion, and output to the second-stage phase-locked loop; then, utilize the second-stage phase-locked loop PLL to reduce the output of the first-stage phase-locked loop Clock jitter (Timing Jitter) and reduce its clock jitter to below 20ps. The clock signal processing system and method of the present invention include the following advantages:

于通用串行总线USB音频同步模式(synchronous mode)声音时脉重建的环境中，利用第一级锁相回路PLL(Phase-Locked Loops)将所输入的通用串行总线USB信息帧起始位SOF(SOF,Start Of Frame)频率予以提升，获得升频后的时脉同步的另一时脉信号，并输出至第二级锁相回路；接着，利用第二级锁相回路PLL降低第一级锁相回路的输出的时脉抖动(Timing Jitter)并将其时脉抖动予以降低到20ps以下。In the environment of universal serial bus USB audio synchronous mode (synchronous mode) sound clock reconstruction environment, use the first stage phase-locked loop PLL (Phase-Locked Loops) to input the universal serial bus USB information frame start bit SOF (SOF, Start Of Frame) frequency is increased to obtain another clock signal synchronized with the up-converted clock, and output to the second-stage phase-locked loop; then, use the second-stage phase-locked loop PLL to reduce the first-stage lock The timing jitter of the output of the phase loop (Timing Jitter) and reduce the timing jitter to below 20ps.

利用双锁相回路PLL的方式来锁定与系统单芯片SOC同步时脉。The dual phase-locked loop PLL is used to lock the clock synchronous with the system single chip SOC.

第一级锁相回路PLL将USB SOF提升，主要是提供时脉同步，而第二级锁相回路PLL将降低第一级锁相回路PLL的输出时脉抖动，将其抖动降低到20ps以下。The first-stage phase-locked loop PLL improves the USB SOF, mainly to provide clock synchronization, and the second-stage phase-locked loop PLL will reduce the output clock jitter of the first-stage phase-locked loop PLL, reducing its jitter to less than 20ps.

当数字模拟转换器DAC/模拟数字转换器ADC时脉与通用串行总线USB信息帧起始位SOF同步时，能使用一个小容量的缓冲区(<100)储存一个信息帧起始位SOF的数据量，而无须很深的缓冲区(>1000)即能正常且没有不连续的播放音，且，由于使用小缓冲区，因而，声音延迟性也大幅改善到1ms以内。When the digital-to-analog converter DAC/analog-to-digital converter ADC clock is synchronized with the universal serial bus USB information frame start bit SOF, a small-capacity buffer (<100) can be used to store a message frame start bit SOF The amount of data can be played normally without a deep buffer (>1000) and there is no discontinuous sound. Moreover, due to the use of a small buffer, the sound delay is also greatly improved to within 1ms.

可改善时脉抖动、大幅缩减先进先出FIFO缓冲区大小、提升音频的信号噪声比SNR、并降低音频的延迟。It can improve the clock jitter, greatly reduce the size of the FIFO buffer, improve the signal-to-noise ratio SNR of the audio, and reduce the delay of the audio.

以上所述仅为本发明的优选实施例而已，并非用以限定本发明的范围；凡其它未脱离本发明所公开的构思下所完成的等效改变或修饰，均应包含在下述的权利要求内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; all other equivalent changes or modifications that do not deviate from the concept disclosed in the present invention should be included in the following claims Inside.