CN108695337B - Programmable erasable non-volatile memory - Google Patents

本发明公开一种可编程可抹除的非挥发性存储器，包括：一第一晶体管，一第二晶体管，一抹除栅区域与一金属层。第一晶体管包括：一选择栅极，一第一掺杂区域以及一第二掺杂区域。选择栅极连接至一字符线。第一掺杂区域连接至一源极线。第二晶体管包括：该第二掺杂区域，一第三掺杂区域以及一浮动栅极。第三掺杂区域连接至一位线。抹除栅区域连接至一抹除线。该浮动栅极延伸至抹除栅区域上方，且相邻于该抹除栅区域。金属层位于该浮动栅极上方，且该金属层连接至该位线。

The present invention discloses a programmable and erasable non-volatile memory, comprising: a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor comprises: a selection gate, a first doped region and a second doped region. The selection gate is connected to a word line. The first doped region is connected to a source line. The second transistor comprises: the second doped region, a third doped region and a floating gate. The third doped region is connected to a bit line. The erase gate region is connected to an erase line. The floating gate extends above the erase gate region and is adjacent to the erase gate region. The metal layer is located above the floating gate, and the metal layer is connected to the bit line.

Programmable erasable non-volatile memory

Technical Field

The present invention relates to non-volatile memories, and more particularly to programmable and erasable non-volatile memories.

Background

Referring to fig. 1A to 1D, a conventional programmable and erasable nonvolatile memory is shown. Such programmable and erasable non-volatile memory is disclosed in US patent 8941167. FIG. 1A is a top view of a programmable erasable non-volatile memory; FIG. 1B is a first direction (a1a2 direction) cross-sectional view of a programmable erasable nonvolatile memory; FIG. 1C is a second direction (b1b2 direction) cross-sectional view of the programmable erasable nonvolatile memory; FIG. 1D is an equivalent circuit diagram of a programmable erasable nonvolatile memory.

The operation principle of the conventional programmable and erasable nonvolatile memory is described as follows.

Disclosure of Invention

The invention aims to provide a programmable erasable nonvolatile memory with a completely new architecture. The programmable erasable nonvolatile memory of the invention is composed of n-type transistors. In addition, a program assisted metal layer (program assisted metal layer) is designed in the programmable erasable non-volatile memory and is positioned above the floating grid. During the programming operation, a bias voltage is provided on the programming auxiliary metal layer to increase electrons injected into the floating gate and effectively improve the programming capability.

The invention is a programmable erasable nonvolatile memory, comprising: a first transistor having a select gate connected to a word line, a first doped region connected to a source line and a second doped region; a second transistor having the second doped region, a third doped region connected to a bit line, and a floating gate; an erasing gate region connected to an erasing line, wherein the floating gate extends to above the erasing gate region and is adjacent to the erasing gate region; and a metal layer located above the floating gate and connected to the bit line.

The invention is a programmable erasable nonvolatile memory, comprising: a select transistor having a gate terminal connected to a word line, a first drain/source terminal connected to a source line, and a second drain/source terminal; a floating gate transistor having a first drain/source terminal connected to the second drain/source terminal of the select transistor, a second drain/source terminal connected to a bit line, and a floating gate; a first capacitor connected between the floating gate and an erase line; and a second capacitor connected between the floating gate and the bit line.

In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:

drawings

FIGS. 1A-1D are schematic diagrams of a conventional programmable and erasable nonvolatile memory;

FIGS. 2A-2H are schematic diagrams illustrating a process, an equivalent circuit and an operating bias voltage of the programmable erasable nonvolatile memory according to the present invention;

FIG. 3 is a diagram of another embodiment of the present invention.

Description of the symbols

31. 32, 33: p-type doped region

34: selection grid

35: erase gate region

36: floating gate

38: n-type doped region

39. 42: isolation structure

44. 46: grid oxide layer

SL: source line

WL: character line

BL1, BL 2: bit line

EL1, EL 2: erase line

Ms, Mf: transistor with a metal gate electrode

SG: selection grid

FG: floating gate

PAM: programming assist metal layer

Ct, Cp: capacitor with a capacitor element

n +: n-type doped region

PW: p-type well region

P-sub: p-type substrate

DNW: deep n-type well region

Detailed Description

Fig. 2A to fig. 2H are schematic diagrams illustrating a manufacturing process, an equivalent circuit and an operating bias voltage of the programmable and erasable nonvolatile memory according to the present invention. The manufacturing process is a process for manufacturing two memory cells, but the invention is not limited thereto.

Fig. 2B shows a gate structure forming step and a doped region forming step. First, two gate oxide layers 44 and 46 are formed on the surface of a p-type substrate (p-sub). Then, a polysilicon gate (polysilicon gate) FG, SG is formed to cover the two gate oxide layers 44, 46, so as to form two gate structures.

In fig. 2B, two gate structures divide the a-region surface area into three portions. And one of the gate structures extends outward and is adjacent to the B region. In addition, the polysilicon gate FG of the gate structure adjacent to the B region is a Floating Gate (FG). The polysilicon gate SG in the other gate structure is a Select Gate (SG) which can be used as a word line (word line).

As shown in fig. 2B, the p-type substrate is doped with two gate structures as masks. Therefore, three parts of the A region which are not covered by the two gate structures form three n-type doped regions n +; and the part of the B region which is not covered by the gate structure forms an n-type doped region n +.

In the region a, the n-type doped region n + at both sides of the select gate SG forms a select transistor (select transistor) with the select gate SG; the n-type doped regions n + on both sides of the floating gate FG form a floating gate transistor (floating gate transistor) with the floating gate FG. The floating gate transistor and the selection transistor are n-type transistors and are manufactured in the p-type well region PW, and the floating gate transistor and the selection transistor are connected in series.

Furthermore, the n + doped region in the region B is an erase gate region, and the floating gate FG extends outward and is adjacent to the erase gate region. Thus, the erase gate region and the floating gate FG are combined into a tunneling capacitor.

In fig. 2B, a first portion (a1) of the floating gate FG covers over area B and a second portion (a2) of the floating gate FG covers over area a, according to an embodiment of the present invention. The area ratio A1/A2 of the first portion (A1) to the second portion (A2) is approximately between 1/4 and 2/3, and better performance is obtained when the area ratio A1/A2 is equal to 3/7. The region a2 is the channel area (channel area) of the floating gate transistor.

Fig. 2C shows a metal layer formation step in a first direction. In the metal layer forming step in the first direction (X direction), source lines SL in the first direction are formed, and the source lines SL are connected to one n-type doped region n + of the selection transistor via the through holes.

In addition, in the metal layer forming step in the first direction, a metal island (metal island) is also formed as a program assisted metal layer (PAM). The programming auxiliary metal layer PAM is located above the floating gate FG, and an Interlayer dielectric (ILD) is disposed between the programming auxiliary metal layer PAM and the floating gate FG for separating the programming auxiliary metal layer PAM and the floating gate FG, so that the programming auxiliary metal layer PAM is not in contact with the floating gate FG. In addition, the program assist metal layer PAM is connected to an n-doped region n + of the floating gate transistor via a through hole. Furthermore, the program assistant metal layer PAM and the floating gate FG are combined to form a program assisted capacitor (program assisted capacitor).

According to a preferred embodiment of the present invention, the area of the program assist metal layer PAM is larger than the area of the floating gate FG, and the floating gate FG is completely covered by the program assist metal layer PAM.

As shown in fig. 2D, in a cross-sectional view along the ab-dashed line in the second direction (Y direction), the program assist metal layer PAM is located above the floating gate FG, and the source line SL is in contact with the n-type doped region n + via a through hole.

Fig. 2E shows a metal layer forming step in a second direction. In the metal layer forming step in the second direction (Y direction), the bit lines BL1, BL2 in the second direction are formed, and the bit lines BL1, BL2 contact the corresponding program assist metal layer PAM through the through holes and contact one n-type doped region n + of the floating gate transistor.

As shown in fig. 2F, in a cross-sectional view along the dashed line cd in the second direction (Y direction), the bit line BL1 contacts the program assist metal layer PAM through a through hole and contacts an n-type doped region n + of the floating gate transistor.

Furthermore, in the manufacturing process of another embodiment, the P-well (PW) may be enlarged such that the n + doped region under the a-region and the B-region is surrounded by the P-well (PW). In other words, in another embodiment, the floating gate transistor, the select transistor and the erase gate region are all constructed in a single P-well (PW). Thus, the memory cell size of the programmable erasable non-volatile memory of the present invention will be effectively reduced and will not be limited by the well area fabrication process rule of the semiconductor manufacturer.

FIG. 2H is a schematic diagram of the bias voltages during the program operation, erase operation and read operation of the programmable and erasable nonvolatile memory according to the present invention.

In the program operation (PGM), a ground voltage (0V) is applied to the p-well PW and the source line SL, a program voltage VPP is applied to the bit line BL and the erase line EL, and a turn-on voltage Von is applied to the word line WL. Wherein the programming voltage VPP is about 6-8V, and the turn-on voltage Von is about 0.5-1.5V.

Therefore, the selection transistor Ms is turned on, and a programming current (program current) is generated in the memory cell from the bit line BL to the source line SL through the floating gate transistor Mf and the selection transistor Ms. Furthermore, since the programming voltage VPP is supplied to the bit line BL and the erase line EL, when electrons (or called hot carriers) pass through the channel region (channel area) of the floating gate transistor Mf, the electrons are attracted and injected into the floating gate FG and stored in the floating gate FG according to the channel electron injection effect (CHE effect) to complete the programming operation.

During an erase operation (ERS), a ground voltage (0V) is applied to the p-well PW, the source line SL and the bit line BL, an erase voltage VEE is applied to the erase line EL, and an off voltage Voff is applied to the word line WL. The erase voltage VEE is about 12V, and the off-voltage Voff is about 0V.

Therefore, the selection transistor Ms is turned off. Electrons stored in the floating gate FG in the memory cell are ejected (project) from the floating gate FG by FN Tunneling, and leave the programmable and erasable nonvolatile memory cell through the penetrating capacitor Ct to the erase line EL. Therefore, after the erase state, there will be no stored electrons in the floating gate FG.

In the Read operation (Read), a ground voltage (0V) is applied to the p-well PW, the source line SL and the erase line EL, a Read voltage Vread is applied to the bit line BL, and a turn-on voltage Von is applied to the word line WL. Where the read voltage Vread is about 1V.

Therefore, the selection transistor Ms is turned on, and a read current (read current) generated in the memory cell flows from the bit line BL to the source line SL through the floating gate transistor Mf and the selection transistor Ms. Furthermore, the storage state of the programmable erasable nonvolatile memory can be known according to the magnitude of the reading current.

Referring to FIG. 3, another embodiment of the present invention is shown in a programmable erasable nonvolatile memory. The difference between FIG. 2E and the deep N-well (DNW) is that the detailed structure is not repeated. That is, in the non-volatile memory of this embodiment, the select transistor and the floating gate transistor are formed in the p-type well PW, and the deep n-type well DNW is included between the p-type well PW and the p-type substrate (p-sub).

Similarly, in the manufacturing process of other embodiments, the P-well (PW) may also be enlarged such that the n + doped region under the a region and the B region is surrounded by the P-well (PW). In other words, in other embodiments, the floating gate transistor, the select transistor and the erase gate region are all constructed in a single P-well (PW). Thus, the memory cell size of the programmable erasable non-volatile memory of the present invention will be effectively reduced and will not be limited by the well area fabrication process rule of the semiconductor manufacturer.

From the above description, the present invention provides a new architecture of programmable and erasable non-volatile memory. The select transistor and the floating gate transistor in the memory cell are composed of n-type transistors. Since the mobility of the memory cell of the present invention is higher than that of the memory cell of the p-type transistor, the memory cell of the present invention has a better margin. In addition, a programming auxiliary metal layer is further designed in the memory unit, and a programming auxiliary capacitor is formed by the programming auxiliary metal layer and the floating grid. During the programming operation, the bias voltage provided on the programming auxiliary metal layer can increase the number of electrons injected into the floating gate and effectively improve the programming capability.

In summary, although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the definition of the appended claims.