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CN108809313A - Using the low-voltage charge transfer circuit of negative voltage and Bootstrap - Google Patents

  • ️Tue Nov 13 2018

CN108809313A - Using the low-voltage charge transfer circuit of negative voltage and Bootstrap - Google Patents

Using the low-voltage charge transfer circuit of negative voltage and Bootstrap Download PDF

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Publication number
CN108809313A
CN108809313A CN201810627194.6A CN201810627194A CN108809313A CN 108809313 A CN108809313 A CN 108809313A CN 201810627194 A CN201810627194 A CN 201810627194A CN 108809313 A CN108809313 A CN 108809313A Authority
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China
Prior art keywords
voltage
charge
mosfet
negative voltage
charge transfer
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2018-06-19
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Chinese (zh)
Inventor
陈珍海
许媛
侯丽
何宁业
刘琦
宁仁霞
吕海江
魏敬和
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Huangshan University
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Huangshan University
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2018-06-19
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2018-06-19
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2018-11-13
2018-06-19 Application filed by Huangshan University filed Critical Huangshan University
2018-06-19 Priority to CN201810627194.6A priority Critical patent/CN108809313A/en
2018-11-13 Publication of CN108809313A publication Critical patent/CN108809313A/en
2019-04-22 Priority to PCT/CN2019/083606 priority patent/WO2019242396A1/en
Status Pending legal-status Critical Current

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/34Analogue value compared with reference values

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

The invention belongs to IC design technical fields, specially a kind of low-voltage charge transfer circuit using negative voltage and Bootstrap, including a charge transmission MOSFET pipes S, a Bootstrap boost pressure circuit, a negative voltage transmission MOSFET pipes B, a voltage switch K, a circuit for generating negative voltage, a generating positive and negative voltage clock generation circuit, the first NMOS tube M1, the second NMOS tube M2, PMOS tube M3, the first capacitance C1 and the second capacitance C2.Its advantage is that overcoming the problem that signal swing is limited in existing signal circuit, can be widely applied in various types of signal processing circuit.

Description

采用负电压和栅压自举的低电压电荷传输电路Low Voltage Charge Transfer Circuit Using Negative Voltage and Gate Voltage Bootstrapping

技术领域technical field

本发明涉及一种用于电荷域流水线模数转换器的输入信号摆幅增强型电荷信号传输电路,属于集成电路技术领域。The invention relates to an input signal swing-enhanced charge signal transmission circuit for a charge-domain pipeline analog-to-digital converter, which belongs to the technical field of integrated circuits.

背景技术Background technique

随着数字信号处理技术的不断发展,电子系统的数字化和集成化是必然趋势。然而现实中的信号大都是连续变化的模拟量,需经过模数转换变成数字信号方可输入到数字系统中进行处理和控制,因而模数转换器在未来的数字系统设计中是不可或缺的组成部分。在宽带通信、数字高清电视和雷达等应用领域,系统要求模数转换器同时具有非常高的采样速率和分辨率。这些应用领域的便携式终端产品对于模数转换器的要求不仅要高采样速率和高分辨率,其功耗还应该最小化。With the continuous development of digital signal processing technology, the digitization and integration of electronic systems is an inevitable trend. However, most signals in reality are continuously changing analog quantities, which need to be transformed into digital signals through analog-to-digital conversion before they can be input into digital systems for processing and control. Therefore, analog-to-digital converters are indispensable in future digital system design. made of. In applications such as broadband communications, digital high-definition television, and radar, systems require analog-to-digital converters with both very high sampling rates and resolutions. Portable terminal products in these application fields require not only high sampling rate and high resolution for analog-to-digital converters, but also minimum power consumption.

目前,能够同时实现高采样速率和高分辨率的模数转换器结构为流水线结构模数转换器。流水线结构是一种多级的转换结构,每一级使用低精度的基本结构的模数转换器,输入信号经过逐级的处理,最后由每级的结果组合生成高精度的输出。其基本思想就是把总体上要求的转换精度平均分配到每一级,每一级的转换结果合并在一起可以得到最终的转换结果。由于流水线结构模数转换器可以在速度、功耗和芯片面积上实现最好的折中,因此在实现较高精度的模数转换时仍然能保持较高的速度和较低的功耗。At present, the analog-to-digital converter structure capable of simultaneously realizing high sampling rate and high resolution is a pipeline-structured analog-to-digital converter. The pipeline structure is a multi-stage conversion structure. Each stage uses an analog-to-digital converter with a low-precision basic structure. The input signal is processed step by step, and finally the results of each stage are combined to generate a high-precision output. The basic idea is to evenly distribute the conversion precision required by the whole to each level, and combine the conversion results of each level to get the final conversion result. Since the pipeline structure ADC can achieve the best compromise in speed, power consumption and chip area, it can still maintain high speed and low power consumption when realizing higher precision analog-to-digital conversion.

现有比较成熟的实现流水线结构模数转换器的方式是基于开关电容技术的流水线结构。基于该技术的流水线模数转换器中采样保持电路和各个子级电路的工作也都必须使用高增益和宽带宽的运算放大器。模数转换器的速度和处理精度取决于所使用高增益和超宽带宽的运算放大器负反馈的建立速度和精度。因此该类流水线结构模数转换器设计的核心是所使用高增益和超宽带宽的运算放大器的设计。这些高增益和宽带宽运算放大器的使用限制了开关电容流水线模数转换器的速度和精度,成为该类模数转换器性能提高的主要限制瓶颈,并且精度不变的情况下模数转换器功耗水平随速度的提高呈直线上升趋势。要降低基于开关电容电路的流水线模数转换器的功耗水平,最直接的方法就是减少或者消去高增益和超宽带宽的运算放大器的使用。The existing relatively mature way to realize the analog-to-digital converter of the pipeline structure is the pipeline structure based on the switched capacitor technology. Operational amplifiers with high gain and wide bandwidth must be used in the sampling and holding circuit and each sub-level circuit in the pipeline analog-to-digital converter based on this technology. The speed and processing accuracy of the analog-to-digital converter depends on the speed and accuracy of the negative feedback settling of the op amp with high gain and ultra-wide bandwidth used. Therefore, the core of the design of this kind of pipeline structure analog-to-digital converter is the design of the operational amplifier with high gain and ultra-wide bandwidth. The use of these high-gain and wide-bandwidth operational amplifiers limits the speed and accuracy of switched-capacitor pipelined ADCs, and becomes the main bottleneck limiting the performance improvement of this type of ADC. The consumption level increases linearly with the increase of speed. The most straightforward way to reduce the power consumption of a pipelined A/D converter based on switched capacitor circuits is to reduce or eliminate the use of high-gain and ultra-wide bandwidth operational amplifiers.

电荷域流水线模数转换器就是一种不使用高增益和超宽带宽的运算放大器的模数转换器,该结构模数转换器具有低功耗特性同时又能实现高速度和高精度。电荷域流水线模数转换器采用电荷域信号处理技术。电路中,信号以电荷包的形式表示,电荷包的大小代表不同大小的信号量,不同大小的电荷包在不同存储节点间的存储、传输、加/减、比较等处理实现信号处理功能。通过采用周期性的时钟来驱动控制不同大小的电荷包在不同存储节点间的信号处理便可以实现模数转换功能。The charge-domain pipelined ADC is an analog-to-digital converter that does not use an operational amplifier with high gain and ultra-wide bandwidth. This structure of the analog-to-digital converter has the characteristics of low power consumption and can achieve high speed and high precision at the same time. The charge-domain pipelined analog-to-digital converter uses charge-domain signal processing techniques. In the circuit, the signal is expressed in the form of a charge packet, and the size of the charge packet represents a semaphore of different sizes, and the storage, transmission, addition/subtraction, comparison, etc. of the charge packets of different sizes between different storage nodes realize the signal processing function. The analog-to-digital conversion function can be realized by using a periodic clock to drive and control the signal processing of charge packets of different sizes between different storage nodes.

在电荷域流水线模数转换器中,各级电荷域流水线子级电路由本级电荷传输控制开关、多个电荷物理存储节点、多个连接到电荷存储节点的电荷存储元件、多个比较器、多个受比较器输出结果控制的基准电荷选择电路在控制时钟的控制下构成。各级流水线子级电路的工作过程中,电荷的传输、加/减、比较量化等功能均围绕各子级的电荷物理存储节点进行。In the charge-domain pipeline analog-to-digital converter, the charge-domain pipeline sub-stage circuits of each stage are composed of the charge transfer control switch of the current stage, multiple charge physical storage nodes, multiple charge storage elements connected to the charge storage nodes, multiple comparators, A plurality of reference charge selection circuits controlled by the output results of the comparators are formed under the control of the control clock. During the working process of the pipeline sub-stage circuits at all levels, the functions of charge transmission, addition/subtraction, comparison and quantification are all carried out around the charge physical storage nodes of each sub-stage.

由于流水线模数转换器的实现包括了大量的数字电路,而普通CMOS工艺是实现这些大规模数字电路的最佳工艺。要借助数字信号处理技术来实现超高速和超高精度的电荷域流水线模数转换器,最核心的一个问题就是电荷信号的存储传输、比较量化以及加减运算等关键步骤在现有的普通CMOS工艺条件下能够高效并精确地实现。因此,为借助大规模数字信号处理技术来实现高速度和高精度电荷域流水线模数转换器,必须提供一种适用于普通CMOS工艺的高精度电荷信号传输电路。Because the realization of the pipeline analog-to-digital converter includes a large number of digital circuits, the common CMOS technology is the best technology to realize these large-scale digital circuits. To use digital signal processing technology to realize ultra-high-speed and ultra-high-precision charge-domain pipeline analog-to-digital converters, the core problem is that key steps such as storage and transmission of charge signals, comparison and quantification, and addition and subtraction operations are performed in the existing ordinary CMOS. It can be realized efficiently and accurately under the process conditions. Therefore, in order to realize high-speed and high-precision charge-domain pipeline analog-to-digital converters with the help of large-scale digital signal processing technology, it is necessary to provide a high-precision charge signal transmission circuit suitable for common CMOS processes.

对于高效信号传输技术的实现,现有的技术实现方式典型的有专利:US2007/0279507A1增强型信号传输电路,其典型电路结构如图1所示。电荷信号传输MOSFET管S的栅极VG被连接到由MOS管M1、M2和M3构成的运算放大器1的输出端。运算放大器1的输出端运算电荷传输之前,S处于关断状态,待传输电荷被存储在C1上。图2为该电路的工作电压波形示意图。t0时刻,Ck1发生负阶越变化,Ck1n发生正阶越变化,导致Ni电压VNi突变到一个低电位而No的电压VNo突变到一个高电位,运算放大器1将会响应该变化并驱动MOSFET管S栅极VG电压为高电平,使得S开始导通;由于电势差的缘故,Ni上所存储电荷将会以电子形式向No转移,引起VNi上升而VNo下降,运算放大器1将同样会响应该变化并驱动MOSFET管S栅极VG电压逐渐降低;t1时刻,当VNi上升到电压VR时,VG电压逐渐降低到截止电压Vth时,S重新关断,电荷传输过程结束,其中VR由共源共栅运算放大器的静态工作点确定。For the realization of high-efficiency signal transmission technology, there is a typical existing technical implementation method: US2007/0279507A1 enhanced signal transmission circuit, and its typical circuit structure is shown in Figure 1. The gate V G of the charge signal transmission MOSFET S is connected to the output terminal of the operational amplifier 1 composed of MOS transistors M1 , M2 and M3 . Before the operational charge is transmitted at the output terminal of the operational amplifier 1, S is in an off state, and the charge to be transmitted is stored on C1 . Figure 2 is a schematic diagram of the working voltage waveform of the circuit. At t0, Ck1 changes negatively and Ck1n changes positively, causing Ni voltage V Ni to suddenly change to a low potential and No voltage V No to change suddenly to a high potential. Operational amplifier 1 will respond to this change and drive MOSFET The V G voltage of the gate of the transistor S is at a high level, making S start to conduct; due to the potential difference, the charge stored on Ni will be transferred to No in the form of electrons, causing V Ni to rise and V No to fall, and the operational amplifier 1 will It will also respond to this change and drive the gate V G voltage of the MOSFET S to gradually decrease; at time t1, when V Ni rises to the voltage VR, and the V G voltage gradually decreases to the cut-off voltage V th , S is turned off again, and the charge transfer The process ends, where VR is determined by the quiescent operating point of the cascode op amp.

对于图1所示信号传输电路,在低电压条件下面临的一个突出问题是它们能处理的输入模拟信号摆幅受限,无法达到通用ADC对输入模拟信号差分摆幅的需求。如图2中所示,电荷传输和电压传输的一个最大区别是电荷传输结束时,MOSFET管S的源和漏两端保持了一个压差VDS,为保证电荷传输过程的安全可靠,MOSFET管S的这个VDS压差通常被设置在20%的VDD电源电压左右。在前期的1.8V电压条件下,MS的VDS压差通常被设置在0.35~0.4V,这就明显降低了电荷域ADC流水线子级电路能处理的输入模拟信号摆幅范围。For the signal transmission circuit shown in Figure 1, a prominent problem faced under low voltage conditions is that the input analog signal swings they can handle are limited, and cannot meet the requirements of general-purpose ADCs for the differential swings of input analog signals. As shown in Figure 2, one of the biggest differences between charge transmission and voltage transmission is that at the end of the charge transmission, a voltage difference V DS is maintained between the source and drain of the MOSFET S. To ensure the safety and reliability of the charge transmission process, the MOSFET S This V DS dropout voltage of S is usually set at around 20% of the VDD supply voltage. Under the previous 1.8V voltage condition, the V DS voltage difference of MS is usually set at 0.35~0.4V, which obviously reduces the input analog signal swing range that the charge domain ADC pipeline sub-stage circuit can handle.

与图1所示信号传输电路的输入信号摆幅主要相关的信号节点为电荷传输管MOSFET管S的栅、漏、源和衬底四端。由于在实际电路中源端和漏端分别属于前后相连的两个子级电路,因此源端的电容是漏端电容的2N倍(N为源端所在子级电路的位数),导致电荷传输时漏端电压下降幅度是源端的2N倍,因此电路的有效信号摆幅主要表现为漏端电压下降幅度,即:VA=VCK1n-VDS-VR,VCK1n为控制信号CK1n的高电平电压。在低电压条件下,VDS所占用的20%VDD电压的压差没有优化空间;VCK1n电压为芯片的全局性基准电压,其理论最大值可为VDD,但实际中其最大值还受G端电压限制,而G端电压最大值只能为电源电压VDD,有明显限制;VR的最低电压受S端限制,而S的最低电压会受到信号‘地电平’电压的限制。因此,要增大信号摆幅,必须克服VR电压的信号‘地电平’和VCK1n电压的VDD限制。本发明中,克服VCK1n电压的VDD限制,采用栅压自举技术,在电荷传输时将G端电压抬高一个VDD电压,这样VCK1n电压的上限可以提高到VDD电压;为克服VR电压的信号‘地电平’限制,采用负电压降压的方式,通过将MOSFET管S的衬底电压接负电压的方式降低S端电压的最低值,这样可以明显降低VR电压的下限,从而增加BCT的信号摆幅。The signal nodes mainly related to the input signal swing of the signal transmission circuit shown in FIG. 1 are the gate, drain, source and substrate of the charge transfer transistor MOSFET S. Since the source terminal and the drain terminal belong to two sub-level circuits connected back and forth in the actual circuit, the capacitance of the source terminal is 2 N times that of the drain terminal capacitance (N is the number of digits of the sub-level circuit where the source terminal is located), resulting in the time of charge transfer The voltage drop at the drain terminal is 2 N times that of the source terminal, so the effective signal swing of the circuit is mainly expressed as the drop range of the drain terminal voltage, that is: V A =V CK1n -V DS -V R , V CK1n is the high level of the control signal CK1n level voltage. Under low voltage conditions, there is no room for optimization of the 20% V DD voltage difference occupied by V DS ; the V CK1n voltage is the global reference voltage of the chip, and its theoretical maximum value can be V DD , but the actual maximum value is still It is limited by the voltage of the G terminal, and the maximum voltage of the G terminal can only be the power supply voltage V DD , which is obviously limited; the minimum voltage of VR is limited by the S terminal, and the minimum voltage of S is limited by the signal 'ground level' voltage . Therefore, to increase the signal swing, the signal 'ground level' of the VR voltage and the V DD limitation of the V CK1n voltage must be overcome. In the present invention, to overcome the V DD limitation of the V CK1n voltage, the gate voltage bootstrap technology is adopted to raise the G terminal voltage by a V DD voltage during charge transmission, so that the upper limit of the V CK1n voltage can be increased to the V DD voltage; in order to overcome The signal 'ground level' of the VR voltage is limited, and the negative voltage step-down method is used to reduce the minimum value of the S terminal voltage by connecting the substrate voltage of the MOSFET S to a negative voltage, which can significantly reduce the VR voltage. lower limit, thereby increasing the signal swing of the BCT.

发明内容Contents of the invention

本发明的目的是克服现有技术中存在的不足,提供一种采用负电压和栅压自举的低电压电荷传输电路,是一种适用于普通CMOS工艺的高精度电荷传输电路。The purpose of the present invention is to overcome the deficiencies in the prior art and provide a low-voltage charge transfer circuit using negative voltage and gate voltage bootstrap, which is a high-precision charge transfer circuit suitable for common CMOS technology.

按照本发明提供的采用负电压和栅压自举的低电压电荷传输电路技术方案,其特征是:包括一个电荷传输MOSFET管S、一个栅压自举增压电路、一个负电压传输MOSFET管B、一个电压开关K、一个负电压产生电路、一个正负电压时钟产生电路、第一NMOS管M1、第二NMOS管M2、PMOS管M3、第一电容C1和第二电容C2;According to the technical scheme of the low-voltage charge transfer circuit adopting negative voltage and grid voltage bootstrap provided by the present invention, it is characterized in that it includes a charge transfer MOSFET tube S, a grid voltage bootstrap booster circuit, and a negative voltage transfer MOSFET tube B , a voltage switch K, a negative voltage generating circuit, a positive and negative voltage clock generating circuit, a first NMOS transistor M1, a second NMOS transistor M2, a PMOS transistor M3, a first capacitor C1 and a second capacitor C2;

所述采用负电压和栅压自举的低电压电荷传输电路对应连接关系为:第一NMOS管M1的栅端连接到电荷待传输节点Ni,即电荷传输MOSFET管S的源极,还连接到栅压自举增压电路的电压输入端;第一NMOS管M1的源端和衬底连接到地电平,第一NMOS管M1的漏端连接到第二NMOS管M2的源端;第二NMOS管M2的漏端连接到PMOS管M3的漏端和电荷传输MOSFET管S的栅端,第二NMOS管M2的栅端连接到第一偏置电压,第二NMOS管M2的衬底接地电平;PMOS管M3的栅端连接到第二偏置电压,PMOS管M3的源端和衬底连接到栅压自举增压电路的电压输出端Vboost;电荷传输目标节点No,即电荷传输MOSFET管S的漏极,通过第二电容C2接电荷传输控制信号Ck1n;电荷待传输节点Ni通过第一电容C1接电荷传输控制信号Ck1;电荷传输MOSFET管S的衬底连接到电压开关K的上端,电荷传输MOSFET管S的衬底还连接到负电压传输MOSFET管B的漏端;电压开关K的下端接地电平,其导通和关断受电荷传输控制信号Ck1控制;负电压传输MOSFET管B的衬底和源端连接到负电压产生电路的输出端,负电压传输MOSFET管B的栅端连接到正负电压时钟产生电路的输出端;负电压产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n,正负电压时钟产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n;栅压自举增压电路的时钟输入端连接电荷传输控制信号Ck1;其中,述电荷传输控制信号Ck1和电荷传输控制信号Ck1n为高电平不交叠脉冲信号,所述高电平为大于零电位的正电压;所述地电平为零电位;所述负电位为小于地电平的负电压。The corresponding connection relationship of the low-voltage charge transfer circuit using negative voltage and gate voltage bootstrapping is as follows: the gate terminal of the first NMOS transistor M1 is connected to the node Ni for charge transfer, that is, the source of the charge transfer MOSFET S, and is also connected to The voltage input terminal of the gate voltage bootstrap booster circuit; the source terminal and the substrate of the first NMOS transistor M1 are connected to the ground level, and the drain terminal of the first NMOS transistor M1 is connected to the source terminal of the second NMOS transistor M2; The drain terminal of the NMOS transistor M2 is connected to the drain terminal of the PMOS transistor M3 and the gate terminal of the charge transfer MOSFET S, the gate terminal of the second NMOS transistor M2 is connected to the first bias voltage, and the substrate of the second NMOS transistor M2 is grounded. level; the gate terminal of the PMOS transistor M3 is connected to the second bias voltage, and the source terminal and the substrate of the PMOS transistor M3 are connected to the voltage output terminal V boost of the gate voltage bootstrap booster circuit; the charge transfer target node No, that is, the charge transfer The drain of the MOSFET S is connected to the charge transfer control signal Ck1n through the second capacitor C2; the charge transfer node Ni is connected to the charge transfer control signal Ck1 through the first capacitor C1; the substrate of the charge transfer MOSFET S is connected to the voltage switch K At the upper end, the substrate of the charge transfer MOSFET S is also connected to the drain of the negative voltage transfer MOSFET B; the lower end of the voltage switch K is grounded, and its on and off are controlled by the charge transfer control signal Ck1; the negative voltage transfer MOSFET The substrate and source terminals of tube B are connected to the output terminal of the negative voltage generating circuit, and the gate terminal of the negative voltage transmission MOSFET tube B is connected to the output terminal of the positive and negative voltage clock generating circuit; the first and second inputs of the negative voltage generating circuit Terminals are respectively connected to the charge transmission control signal Ck1 and the charge transmission control signal Ck1n, the first and second input terminals of the positive and negative voltage clock generation circuit are respectively connected to the charge transmission control signal Ck1 and the charge transmission control signal Ck1n; the gate voltage bootstrap booster circuit The clock input terminal of the clock is connected to the charge transmission control signal Ck1; wherein, the charge transmission control signal Ck1 and the charge transmission control signal Ck1n are high-level non-overlapping pulse signals, and the high level is a positive voltage greater than zero potential; The ground level is zero potential; the negative potential is a negative voltage lower than the ground level.

所述采用负电压和栅压自举的低电压电荷传输电路,其特征还在于:当进行电荷传输时,所述栅压自举增压电路处于增压状态,所述电荷传输MOSFET管的栅极为高电平VDD+VNi,电荷电压传输MOSFET管处于导通状态;当电荷传输结束后,所述栅压自举增压电路处于充电状态,所述电荷传输MOSFET管的栅极接地电平,所述电荷传输MOSFET管处于关断状态;其中,VDD为电源电压,VNi为MOSFET管的源极电压。The low-voltage charge transfer circuit using negative voltage and grid voltage bootstrap is also characterized in that: when performing charge transfer, the grid voltage bootstrap booster circuit is in a boosted state, and the gate of the charge transfer MOSFET tube Extremely high level V DD +V Ni , the charge voltage transfer MOSFET is in the on state; when the charge transfer is completed, the gate voltage bootstrap booster circuit is in the charging state, and the gate of the charge transfer MOSFET is grounded Ping, the charge transfer MOSFET is in an off state; wherein, V DD is the power supply voltage, and V Ni is the source voltage of the MOSFET.

所述采用负电压和栅压自举的低电压电荷传输电路,其特征还在于:当进行电荷传输时,所述负电压传输MOSFET管B的栅极接高电平,负电压传输MOSFET管B处于导通状态,所述电荷传输MOSFET管S的衬底接负电压;当电荷传输结束后,所述负电压传输MOSFET管B的栅极接负电压,所述负电压传输MOSFET管B处于关断状态,所述电荷传输MOSFET管S的衬底接地电平。The low-voltage charge transfer circuit using negative voltage and grid voltage bootstrapping is also characterized in that: when performing charge transfer, the gate of the negative voltage transfer MOSFET B is connected to a high level, and the negative voltage transfer MOSFET B In the conduction state, the substrate of the charge transfer MOSFET S is connected to a negative voltage; when the charge transfer is completed, the gate of the negative voltage transfer MOSFET B is connected to a negative voltage, and the negative voltage transfer MOSFET B is turned off In the off state, the substrate of the charge transfer MOSFET S is grounded.

本发明的优点是:本发明所提供的适用于普通CMOS工艺的采用负电压和栅压自举的低电压电荷传输电路,克服了现有信号传输电路中信号摆幅受限的问题,可以广泛应用于电荷域流水线模数转换器中各级电荷域子级流水电路中。The advantages of the present invention are: the low-voltage charge transmission circuit using negative voltage and gate voltage bootstrap provided by the present invention, which is suitable for common CMOS technology, overcomes the problem of limited signal swing in the existing signal transmission circuit, and can be widely used The invention is applied to charge domain sub-level pipeline circuits of all levels in charge domain pipeline analog-to-digital converters.

以下将结合附图和实施例,对本发明进行较为详细的说明。The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

附图说明Description of drawings

图1为现有信号传输电路原理图。FIG. 1 is a schematic diagram of an existing signal transmission circuit.

图2为现有信号传输电路工作电压波形示意图。FIG. 2 is a schematic diagram of a working voltage waveform of an existing signal transmission circuit.

图3为本发明采用负电压和栅压自举的低电压电荷传输电路结构原理图。FIG. 3 is a structural schematic diagram of a low-voltage charge transfer circuit using negative voltage and gate voltage bootstrapping in the present invention.

图4为本发明采用负电压和栅压自举的低电压电荷传输电路工作电压波形示意图。FIG. 4 is a schematic diagram of the working voltage waveform of the low-voltage charge transfer circuit using negative voltage and grid voltage bootstrapping in the present invention.

图5为本发明所述栅压自举增压电路的一种实现电路图。FIG. 5 is an implementation circuit diagram of the gate voltage bootstrap booster circuit of the present invention.

图6为本发明所述负电压产生电路的一种实现电路图。FIG. 6 is an implementation circuit diagram of the negative voltage generating circuit of the present invention.

图7(a)为本发明所述正负电压时钟产生电路的一种实现电路原理图。FIG. 7( a ) is a schematic diagram of an implementation circuit of the positive and negative voltage clock generation circuit of the present invention.

图7(b)为本发明所述正负电压时钟产生电路工作的电压波形图。Fig. 7(b) is a voltage waveform diagram of the operation of the positive and negative voltage clock generating circuit of the present invention.

图8为本发明采用负电压和栅压自举的低电压电荷传输电路在电荷域流水线模数转换器中的应用。FIG. 8 shows the application of the low-voltage charge transfer circuit using negative voltage and gate voltage bootstrap in the charge-domain pipeline analog-to-digital converter of the present invention.

具体实施方式Detailed ways

实施例,下面结合附图和实例对本发明进行进一步详细的说明。Embodiments, the present invention will be further described in detail below in conjunction with the accompanying drawings and examples.

图3所示为本发明设计的采用负电压和栅压自举的低电压电荷传输电路的结构原理图,其在图1所示信号传输电路中的MOSFET管S的衬底增加了一个负电压产生电路和负电压传输电路,在MOSFET管S的源极和电源VDD之间增加了一个栅压自举增压电路。所述采用负电压和栅压自举的低电压电荷传输电路包括一个电荷传输MOSFET管S、一个栅压自举增压电路、一个负电压传输MOSFET管B、一个电压开关K、一个负电压产生电路、一个正负电压时钟产生电路、第一NMOS管M1、第二NMOS管M2、PMOS管M3、第一电容C1和第二电容C2。Fig. 3 shows the schematic diagram of the structure of the low-voltage charge transmission circuit using negative voltage and grid voltage bootstrapping designed by the present invention, which adds a negative voltage to the substrate of the MOSFET tube S in the signal transmission circuit shown in Fig. 1 In the generation circuit and the negative voltage transmission circuit, a gate voltage bootstrap booster circuit is added between the source of the MOSFET S and the power supply VDD. The low-voltage charge transfer circuit using negative voltage and grid voltage bootstrap includes a charge transfer MOSFET S, a grid voltage bootstrap booster circuit, a negative voltage transfer MOSFET B, a voltage switch K, and a negative voltage generator circuit, a positive and negative voltage clock generating circuit, a first NMOS transistor M1, a second NMOS transistor M2, a PMOS transistor M3, a first capacitor C1 and a second capacitor C2.

所述采用负电压和栅压自举的低电压电荷传输电路对应连接关系为:第一NMOS管M1的栅端连接到电荷待传输节点Ni,即电荷传输MOSFET管S的源极,还连接到栅压自举增压电路的电压输入端;第一NMOS管M1的源端和衬底连接到地电平,第一NMOS管M1的漏端连接到第二NMOS管M2的源端;第二NMOS管M2的漏端连接到PMOS管M3的漏端和电荷传输MOSFET管S的栅端,第二NMOS管M2的栅端连接到第一偏置电压,第二NMOS管M2的衬底接地电平;PMOS管M3的栅端连接到第二偏置电压,PMOS管M3的源端和衬底连接到栅压自举增压电路的电压输出端Vboost;电荷传输目标节点No,即电荷传输MOSFET管S的漏极,通过第二电容C2接电荷传输控制信号Ck1n;电荷待传输节点Ni通过第一电容C1接电荷传输控制信号Ck1;电荷传输MOSFET管S的衬底连接到电压开关K的上端,电荷传输MOSFET管S的衬底还连接到负电压传输MOSFET管B的漏端;电压开关K的下端接地电平,其导通和关断受电荷传输控制信号Ck1控制;负电压传输MOSFET管B的衬底和源端连接到负电压产生电路的输出端,负电压传输MOSFET管B的栅端连接到正负电压时钟产生电路的输出端;负电压产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n,正负电压时钟产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n;栅压自举增压电路的时钟输入端连接电荷传输控制信号Ck1。The corresponding connection relationship of the low-voltage charge transfer circuit using negative voltage and gate voltage bootstrapping is as follows: the gate terminal of the first NMOS transistor M1 is connected to the node Ni for charge transfer, that is, the source of the charge transfer MOSFET S, and is also connected to The voltage input terminal of the gate voltage bootstrap booster circuit; the source terminal and the substrate of the first NMOS transistor M1 are connected to the ground level, and the drain terminal of the first NMOS transistor M1 is connected to the source terminal of the second NMOS transistor M2; The drain terminal of the NMOS transistor M2 is connected to the drain terminal of the PMOS transistor M3 and the gate terminal of the charge transfer MOSFET S, the gate terminal of the second NMOS transistor M2 is connected to the first bias voltage, and the substrate of the second NMOS transistor M2 is grounded. level; the gate terminal of the PMOS transistor M3 is connected to the second bias voltage, and the source terminal and the substrate of the PMOS transistor M3 are connected to the voltage output terminal V boost of the gate voltage bootstrap booster circuit; the charge transfer target node No, that is, the charge transfer The drain of the MOSFET S is connected to the charge transfer control signal Ck1n through the second capacitor C2; the charge transfer node Ni is connected to the charge transfer control signal Ck1 through the first capacitor C1; the substrate of the charge transfer MOSFET S is connected to the voltage switch K At the upper end, the substrate of the charge transfer MOSFET S is also connected to the drain of the negative voltage transfer MOSFET B; the lower end of the voltage switch K is grounded, and its on and off are controlled by the charge transfer control signal Ck1; the negative voltage transfer MOSFET The substrate and source terminals of tube B are connected to the output terminal of the negative voltage generating circuit, and the gate terminal of the negative voltage transmission MOSFET tube B is connected to the output terminal of the positive and negative voltage clock generating circuit; the first and second inputs of the negative voltage generating circuit Terminals are respectively connected to the charge transmission control signal Ck1 and the charge transmission control signal Ck1n, the first and second input terminals of the positive and negative voltage clock generation circuit are respectively connected to the charge transmission control signal Ck1 and the charge transmission control signal Ck1n; the gate voltage bootstrap booster circuit The clock input terminal of is connected to the charge transfer control signal Ck1.

图4给出了本发明采用负电压和栅压自举的低电压电荷传输电路的工作电压波形示意图。通过采用栅自举升压技术,在电荷传输时将G端电压抬高一个VDD电压,这样VCK1n电压的上限可以提高到VDD电压,从而达到增加BCT信号摆幅的目的。VCK1n电压被提高到V’CK1n,理论上的上限可以提高到VDD,可以看出BCT电路的信号摆幅V’A增加了(V’CK1n-VCK1n);通过采用负电压降压后,VR电压被降低为V’R,S端电压的最低值为负电压,可以看出BCT电路的信号摆幅VA增加了VR-V’R的差值电压;同时采用负电压和栅压自举升压技术后,本发明所述采用负电压和栅压自举的低电压电荷传输电路的输出端信号摆幅共增加了(V’CK1n-VCK1n)+(VR-V’R)的摆幅。FIG. 4 shows a schematic diagram of the working voltage waveform of the low-voltage charge transfer circuit using negative voltage and gate voltage bootstrap according to the present invention. By using the gate bootstrap boost technology, the voltage of the G terminal is raised by a V DD voltage during charge transmission, so that the upper limit of the V CK1n voltage can be raised to the V DD voltage, thereby achieving the purpose of increasing the BCT signal swing. The V CK1n voltage is raised to V' CK1n , and the theoretical upper limit can be raised to V DD . It can be seen that the signal swing V' A of the BCT circuit increases (V' CK1n -V CK1n ); after stepping down by using a negative voltage , the VR voltage is reduced to V' R , and the minimum value of the S terminal voltage is a negative voltage . It can be seen that the signal swing V A of the BCT circuit increases the difference voltage of VR -V'R; at the same time, the negative voltage and After the grid voltage bootstrap boost technology, the signal swing at the output terminal of the low-voltage charge transfer circuit using negative voltage and grid voltage bootstrap in the present invention has increased by (V' CK1n -V CK1n )+(V R -V ' R ) swing.

图5所示为一种可以用于本发明的栅压自举增压电路的原理图。其原理如下:时钟Ck1为高电平时,MOS管Mb2、Mb6导通,MOS管Mb7截至,Mb4导通,使得MOS管Mb1也导通;电路通过MOS管Mb1和Mb2对电容Cb1充电,使得电容Cb1两端的电压接近电源电压VDD,从而在电容Cbl上存储了VDD*Cb1的电量,栅压自举增压电路处于充电状态。当时钟Ck1从高变低时,MOS管Mb2、Mb6截止,MOS管Mb7导通,Mb4导通;电源通过MOS管Mb4、Mb7对结点Vboost的对地寄生电容充电,使得结点Vboost电压升高,MOS管Mb1截止,Mb5、Mb3导通;输入信号通过MOS管Mb3抬升电容Cb1下极板电压直到其值等于输入电压VNi;由于电容Cb1上存储的电荷在时钟CK变化过程中没有放电回路,存储在其上的电荷保持不变,电容Cbl上极板的电压就会同步上升,直到其值等于VDD+VNi,实现了栅压自举功能,栅压自举增压电路处于增压状态。FIG. 5 is a schematic diagram of a grid voltage bootstrap booster circuit that can be used in the present invention. The principle is as follows: when the clock Ck1 is at a high level, the MOS transistors Mb2 and Mb6 are turned on, the MOS transistor Mb7 is turned off, and the Mb4 is turned on, so that the MOS transistor Mb1 is also turned on; the circuit charges the capacitor Cb1 through the MOS transistors Mb1 and Mb2, so that the capacitor The voltage at both ends of Cb1 is close to the power supply voltage V DD , so that the electric quantity of V DD *Cb1 is stored on the capacitor Cbl, and the gate voltage bootstrap booster circuit is in a charging state. When the clock Ck1 changes from high to low, the MOS transistors Mb2 and Mb6 are turned off, the MOS transistor Mb7 is turned on, and Mb4 is turned on; the power supply charges the parasitic capacitance of the node V boost to the ground through the MOS transistors Mb4 and Mb7, so that the node V boost When the voltage rises, the MOS transistor Mb1 is turned off, and Mb5 and Mb3 are turned on; the input signal passes through the MOS transistor Mb3 to raise the voltage of the lower plate of the capacitor Cb1 until its value is equal to the input voltage V Ni ; because the charge stored on the capacitor Cb1 is in the process of changing the clock CK There is no discharge circuit, the charge stored on it remains unchanged, and the voltage on the upper plate of the capacitor Cbl will rise synchronously until its value is equal to V DD +V Ni , realizing the gate voltage bootstrap function and boosting the gate voltage The circuit is boosted.

结合图4的波形示意图可以知道。当进行电荷传输时,栅压自举增压电路处于增压状态,所述电荷传输MOSFET管的栅极为高电平VDD+VNi,电荷传输MOSFET管S处于导通状态;当电荷传输结束后,栅压自举增压电路处于充电状态,所述电荷传输MOSFET管S的栅极接地电平,所述电荷传输MOSFET管处于关断状态。其中,VDD为电源电压,VNi为电荷传输MOSFET管S的源极电压。It can be known from the waveform schematic diagram in FIG. 4 . When performing charge transfer, the gate voltage bootstrap booster circuit is in a boost state, the gate of the charge transfer MOSFET is at a high level V DD +V Ni , and the charge transfer MOSFET S is in a conduction state; when the charge transfer ends Afterwards, the gate voltage bootstrap booster circuit is in a charging state, the gate of the charge transfer MOSFET S is grounded, and the charge transfer MOSFET S is in an off state. Among them, V DD is the power supply voltage, and V Ni is the source voltage of the charge transfer MOSFET S.

图6所示为一种可以用于本发明中为图3中电荷传输MOSFET管S衬底提供负偏置电压的一种负电压产生电路的原理图。该电路采用类似的电容充放电和MOS开关的导通和关断特性实现负电压输出,详细的电路工作原理可以参考美国专利US5831844,在此不再阐述。FIG. 6 is a schematic diagram of a negative voltage generating circuit that can be used in the present invention to provide a negative bias voltage for the substrate of the charge transfer MOSFET S in FIG. 3 . The circuit adopts similar capacitor charging and discharging and MOS switch turn-on and turn-off characteristics to realize negative voltage output. For detailed circuit working principle, please refer to US Patent No. 5,831,844, which will not be elaborated here.

本发明中负电压产生电路输出的负电压通过一个负电压传输MOSFET管B来进行传输。当所述输入信号摆幅增强型信号传输电路开始进行电荷传输时,负电压传输MOSFET管B的栅极接高电平,负电压传输MOSFET管B处于导通状态,电荷传输MOSFET管S的衬底接负电压;当所述输入信号摆幅增强型信号传输电路电荷传输结束后,负电压传输MOSFET管B的栅极接负电压,负电压传输MOSFET管B处于关断状态,电荷传输MOSFET管S的衬底在电荷传输控制信号Ck1控制下接地电平。In the present invention, the negative voltage output by the negative voltage generating circuit is transmitted through a negative voltage transmission MOSFET B. When the input signal swing enhanced signal transmission circuit starts charge transmission, the gate of the negative voltage transmission MOSFET B is connected to a high level, the negative voltage transmission MOSFET B is in the conduction state, and the lining of the charge transmission MOSFET S The bottom is connected to the negative voltage; when the charge transmission of the input signal swing enhanced signal transmission circuit is completed, the gate of the negative voltage transmission MOSFET B is connected to the negative voltage, the negative voltage transmission MOSFET B is in the off state, and the charge transmission MOSFET The substrate of S is grounded under the control of the charge transfer control signal Ck1.

本发明采用正负电压时钟来控制负电压传输MOSFET管B的信号传输,主要原因是在负电压传输MOSFET管B的源端和衬底均为负电压时,要将负电压传输MOSFET管B关断,必须使负电压传输MOSFET管B的栅端和源端电压差小于其开启的阈值电压(VthB)。若采用普通电压时钟控制负电压传输MOSFET管B的栅端,则会出现时钟低电平时,负电压传输MOSFET管B的栅端和源端电压大于其开启的阈值电压(VthB)的状态,导致负电压传输MOSFET管B不能关断。因此,负电压传输MOSFET管B的栅端控制时钟必须采用正负电压时钟来进行控制。The present invention uses positive and negative voltage clocks to control the signal transmission of the negative voltage transmission MOSFET tube B. The main reason is that when the source terminal and the substrate of the negative voltage transmission MOSFET tube B are both negative voltages, the negative voltage transmission MOSFET tube B must be turned off. To turn off, the voltage difference between the gate terminal and the source terminal of the negative voltage transmission MOSFET B must be smaller than its turn-on threshold voltage (V thB ). If an ordinary voltage clock is used to control the gate terminal of the negative voltage transmission MOSFET B, when the clock is at a low level, the voltage at the gate terminal and the source terminal of the negative voltage transmission MOSFET B is greater than its threshold voltage (V thB ), As a result, the negative voltage transmission MOSFET tube B cannot be turned off. Therefore, the gate terminal control clock of the negative voltage transmission MOSFET B must be controlled by positive and negative voltage clocks.

本发明所述高电平为大于零电位的正电压;所述地电平为零电压;所述负电位为小于地电平的负电压;述电荷传输控制信号Ck1和电荷传输控制信号Ck1n为高电平不交叠脉冲信号。The high level of the present invention is a positive voltage greater than zero potential; the ground level is zero voltage; the negative potential is a negative voltage lower than the ground level; the charge transmission control signal Ck1 and the charge transmission control signal Ck1n are High level non-overlapping pulse signal.

图7(a)和图7(b)所示为一种可以用于本发明中为图3中的一种正负电压时钟产生电路的电路原理和工作电压波形图。图7(a)为所述正负电压时钟产生电路的电路原理,图7(b)为所述正负电压时钟产生电路工作时仿真得到的输入电荷传输控制信号Ck1n和输出信号Ck1nout的电压波形图。该电路采用类似的电容充放电和数字触发器电路的特性实现正负电压时钟输出,详细的电路工作原理可以参考中国专利ZL201010175033.1(一种适用于标准CMOS工艺的负电压有效传输电路),其原理在此不再阐述。FIG. 7(a) and FIG. 7(b) show a circuit principle and working voltage waveform diagram of a positive and negative voltage clock generating circuit in FIG. 3 that can be used in the present invention. Fig. 7 (a) is the circuit principle of the positive and negative voltage clock generation circuit, and Fig. 7 (b) is the voltage waveform of the input charge transmission control signal Ck1n and the output signal Ck1nout simulated when the positive and negative voltage clock generation circuit is working picture. The circuit adopts similar characteristics of capacitor charging and discharging and digital trigger circuit to realize positive and negative voltage clock output. For detailed circuit working principle, please refer to Chinese patent ZL201010175033.1 (a negative voltage effective transmission circuit suitable for standard CMOS technology). Its principle will not be elaborated here.

图8为本发明在电荷域流水线ADC中的应用。图中所示为电荷域流水线模数转换器中1.5位/级电荷域子级流水线电路具体实现和前后级电荷域子级流水线电路的具体连接关系。电荷域子级流水线电路由全差分的信号处理通道100p和100n构成,电荷域子级流水线电路包括2个本发明所述的采用负电压和栅压自举的低电压电荷传输电路(101p和101n)、2个电荷存储节点(104p和104n)、2个连接到前级子级电路电荷存储节点的电荷存储电容(106p和106n)、6个连接到本级1.5位/级子级电路电荷存储节点的电荷存储电容(107p、107n、108p、108n)、2个比较器,2个受比较器输出结果控制的基准电荷选择电路,2个连接到本级电荷存储节点的下一级子级电路的本发明所述采用负电压和栅压自举的低电压电荷传输电路(102p和102n),2个连接到下一级子级电路电荷存储节点的电荷存储电容(109p和109n)。FIG. 8 is an application of the present invention in a charge-domain pipeline ADC. The figure shows the specific implementation of the 1.5-bit/stage charge domain sub-stage pipeline circuit in the charge domain pipeline analog-to-digital converter and the specific connection relationship between the front and rear charge domain sub-stage pipeline circuits. The charge domain sub-stage pipeline circuit is composed of fully differential signal processing channels 100p and 100n, and the charge domain sub-stage pipeline circuit includes two low-voltage charge transfer circuits (101p and 101n ), 2 charge storage nodes (104p and 104n), 2 charge storage capacitors (106p and 106n) connected to the previous stage sub-level circuit charge storage nodes, 6 charge storage capacitors (106p and 106n) connected to the current level 1.5 bit/level sub-level circuit Node charge storage capacitors (107p, 107n, 108p, 108n), 2 comparators, 2 reference charge selection circuits controlled by the output results of the comparators, and 2 next-level sub-level circuits connected to the current-level charge storage nodes Low-voltage charge transfer circuits (102p and 102n) using negative voltage and gate voltage bootstrapping according to the present invention, and two charge storage capacitors (109p and 109n) connected to the charge storage nodes of the next sub-level circuit.

以上所述仅为本发明的较佳实施例,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (3)

1.一种采用负电压和栅压自举的低电压电荷传输电路,其特征是:包括一个电荷传输MOSFET管S、一个栅压自举增压电路、一个负电压传输MOSFET管B、一个电压开关K、一个负电压产生电路、一个正负电压时钟产生电路、第一NMOS管M1、第二NMOS管M2、PMOS管M3、第一电容C1和第二电容C2;所述采用负电压和栅压自举的低电压电荷传输电路对应连接关系为:第一NMOS管M1的栅端连接到电荷待传输节点Ni,即电荷传输MOSFET管S的源极,还连接到栅压自举增压电路的电压输入端;第一NMOS管M1的源端和衬底连接到地电平,第一NMOS管M1的漏端连接到第二NMOS管M2的源端;第二NMOS管M2的漏端连接到PMOS管M3的漏端和电荷传输MOSFET管S的栅端,第二NMOS管M2的栅端连接到第一偏置电压,第二NMOS管M2的衬底接地电平;PMOS管M3的栅端连接到第二偏置电压,PMOS管M3的源端和衬底连接到栅压自举增压电路的电压输出端Vboost;电荷传输目标节点No,即电荷传输MOSFET管S的漏极,通过第二电容C2接电荷传输控制信号Ck1n;电荷待传输节点Ni通过第一电容C1接电荷传输控制信号Ck1;电荷传输MOSFET管S的衬底连接到电压开关K的上端,电荷传输MOSFET管S的衬底还连接到负电压传输MOSFET管B的漏端;电压开关K的下端接地电平,其导通和关断受电荷传输控制信号Ck1控制;负电压传输MOSFET管B的衬底和源端连接到负电压产生电路的输出端,负电压传输MOSFET管B的栅端连接到正负电压时钟产生电路的输出端;负电压产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n,正负电压时钟产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n;栅压自举增压电路的时钟输入端连接电荷传输控制信号Ck1;其中,述电荷传输控制信号Ck1和电荷传输控制信号Ck1n为高电平不交叠脉冲信号;所述高电平为大于零电位的正电压;所述地电平为零电位;所述负电位为小于地电平的负电压。1. A low-voltage charge transfer circuit using negative voltage and grid voltage bootstrap, characterized in that it includes a charge transfer MOSFET tube S, a grid voltage bootstrap booster circuit, a negative voltage transfer MOSFET tube B, a voltage switch K, a negative voltage generating circuit, a positive and negative voltage clock generating circuit, a first NMOS transistor M1, a second NMOS transistor M2, a PMOS transistor M3, a first capacitor C1 and a second capacitor C2; the negative voltage and gate The corresponding connection relationship of the voltage bootstrap low-voltage charge transfer circuit is as follows: the gate terminal of the first NMOS transistor M1 is connected to the charge transfer node Ni, that is, the source of the charge transfer MOSFET S, and is also connected to the gate voltage bootstrap booster circuit The voltage input terminal of the first NMOS transistor M1 is connected to the ground level, the drain of the first NMOS transistor M1 is connected to the source of the second NMOS transistor M2; the drain of the second NMOS transistor M2 is connected to To the drain terminal of the PMOS transistor M3 and the gate terminal of the charge transfer MOSFET S, the gate terminal of the second NMOS transistor M2 is connected to the first bias voltage, and the substrate of the second NMOS transistor M2 is connected to the ground level; the gate terminal of the PMOS transistor M3 terminal is connected to the second bias voltage, the source terminal and the substrate of the PMOS transistor M3 are connected to the voltage output terminal V boost of the gate voltage bootstrap booster circuit; the target node No of the charge transfer is the drain of the charge transfer MOSFET S, The charge transmission control signal Ck1n is connected through the second capacitor C2; the charge transmission node Ni is connected to the charge transmission control signal Ck1 through the first capacitor C1; the substrate of the charge transmission MOSFET S is connected to the upper end of the voltage switch K, and the charge transmission MOSFET S The substrate of the negative voltage transmission MOSFET tube B is also connected to the drain terminal; the lower end of the voltage switch K is grounded, and its on and off are controlled by the charge transmission control signal Ck1; the substrate and source of the negative voltage transmission MOSFET tube B The terminal is connected to the output terminal of the negative voltage generating circuit, and the gate terminal of the negative voltage transmission MOSFET B is connected to the output terminal of the positive and negative voltage clock generating circuit; the first and second input terminals of the negative voltage generating circuit are respectively connected to the charge transmission control signal Ck1 and the charge transfer control signal Ck1n, the first and second input ends of the positive and negative voltage clock generation circuit are connected to the charge transfer control signal Ck1 and the charge transfer control signal Ck1n respectively; the clock input end of the gate voltage bootstrap booster circuit is connected to the charge transfer Control signal Ck1; wherein, the charge transmission control signal Ck1 and the charge transmission control signal Ck1n are high-level non-overlapping pulse signals; the high level is a positive voltage greater than zero potential; the ground level is zero potential; The negative potential is a negative voltage lower than the ground level. 2.根据权利要求1所述采用负电压和栅压自举的低电压电荷传输电路,其特征在于:当进行电荷传输时,所述栅压自举增压电路处于增压状态,所述电荷传输MOSFET管S的栅极为高电平VDD+VNi,电荷电压传输MOSFET管S处于导通状态;当电荷传输结束后,所述栅压自举增压电路处于充电状态,所述电荷传输MOSFET管S的栅极接地电平,所述电荷传输MOSFET管S处于关断状态;其中,VDD为电源电压,VNi为MOSFET管的源极电压。2. The low-voltage charge transfer circuit using negative voltage and grid voltage bootstrap according to claim 1, characterized in that: when carrying out charge transfer, the grid voltage bootstrap booster circuit is in a boosted state, and the charge The gate of the transmission MOSFET S is at a high level V DD +V Ni , and the charge voltage transmission MOSFET S is in a conduction state; when the charge transmission is completed, the gate voltage bootstrap booster circuit is in a charging state, and the charge transmission The gate of the MOSFET S is at ground level, and the charge transfer MOSFET S is in an off state; wherein, V DD is the power supply voltage, and V Ni is the source voltage of the MOSFET. 3.根据权利要求1所述输入信号摆幅增强型信号传输电路,其特征在于:当进行电荷传输时,所述负电压传输MOSFET管B的栅极接高电平,负电压传输MOSFET管B处于导通状态,所述电荷传输MOSFET管S的衬底接负电压;当电荷传输结束后,所述负电压传输MOSFET管B的栅极接负电压,所述负电压传输MOSFET管B处于关断状态,所述电荷传输MOSFET管S的衬底接地电平。3. The input signal swing enhanced signal transmission circuit according to claim 1, characterized in that: when performing charge transmission, the gate of the negative voltage transmission MOSFET B is connected to a high level, and the negative voltage transmission MOSFET B In the conduction state, the substrate of the charge transfer MOSFET S is connected to a negative voltage; when the charge transfer is completed, the gate of the negative voltage transfer MOSFET B is connected to a negative voltage, and the negative voltage transfer MOSFET B is turned off In the off state, the substrate of the charge transfer MOSFET S is grounded.

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