CN109150170A - Phase-locked loop circuit - Google Patents

The present invention provides a kind of phase-locked loop circuit, the phase-locked loop circuit includes phase frequency detector and controller, in which: reference clock signal and frequency-divided feedback signal are provided to the input terminal of the phase frequency detector；The controller provides first control signal and second control signal to the phase frequency detector；When the phase-locked loop circuit initialization, the first control signal and the second control signal of the controller output are the first level；When the reference clock signal and the frequency-divided feedback signal are jumped to the first level, the first control signal of the controller output and second control signal jump are second electrical level, and keeping jump after a certain period of time is the first level；First level is higher than the second electrical level.

Phase-locked loop circuit

Technical field

The present invention relates to technical field of integrated circuits, in particular to a kind of phase-locked loop circuit.

Background technique

Phaselocked loop is a kind of typical feedback control circuit, utilizes externally input reference signal control loop internal oscillator The frequency and phase of signal realize that output signal frequency automatically tracks frequency input signal, are generally used for Closed loop track electricity Road.It is a kind of method for keeping frequency relatively stable in radio transmitting, mainly having voltage controlled oscillator and PLL IC, (phaselocked loop is integrated Circuit), voltage controlled oscillator provides a signal, and a part of as output, another part passes through caused by frequency dividing and PLL IC Local oscillation signal makees phase bit comparison, in order to which keep frequency is constant, it is desirable to which phase difference does not change, if dephased change Change, then the voltage of the voltage output end of PLL IC changes, and removes control VCO, until phase difference recovery, reaches the mesh of locking phase , so that the frequency of controlled oscillator and phase is kept determining the close loop electronic circuit of relationship with input signal.

It is not no burr that the phaselocked loop of low jitter, which requires input reference clock signal,.But due to the reflection of plate grade, quilt The interference of other clock signals or other disturbing factors, the reference clock of phaselocked loop often have a large amount of burr.As shown in Figure 1, The information of mistake can be passed to phase frequency detector by these burr signals, lead to its phase demodulation mistake.

The refclk of Fig. 1 is the reference clock signal of phaselocked loop, it is with jagged.Fbclk is voltage controlled oscillator (DCO) warp Feedback signal after frequency divider frequency dividing.Width is the phase error of refclk and fbclk.Phaselocked loop has been in the lock state, The only fixed skew of very little.But working as has small burr in refclk, when short pulse as shown in Figure 1 can be treated as reference The rising edge and fbclk of clock carry out phase demodulation, generate a phase error.When the normal rising edge of refclk arrives, it is recognized For anticipating signal, width exports high level, until the arrival of next feedback clock rising edge.So its phase error becomes At reference clock cycle or so.This phase error, which needs phaselocked loop after a period of time, to be corrected, to generate Big shake.

The method of traditional elimination burr is to be followed by shaping circuit by RC analog circuit to filter input reference clock Wave.It is disadvantageous in that, if burr is stronger, RC filter does not filter burr, via shaping circuit shaping, can generate High-frequency signal, this will affect the locking of phaselocked loop, and generate biggish shake.

Summary of the invention

The purpose of the present invention is to provide a kind of phase-locked loop circuits, to solve existing phase-locked loop circuit reference clock signal There is the problem of burr.

In order to solve the above technical problems, the present invention provides a kind of phase-locked loop circuit, the phase-locked loop circuit includes frequency discrimination mirror Phase device and controller, in which:

Reference clock signal and frequency-divided feedback signal are provided to the input terminal of the phase frequency detector；

The controller provides first control signal and second control signal to the phase frequency detector；

When the phase-locked loop circuit initialization, the first control signal and described second of the controller output Control signal is the first level；

When the reference clock signal and the frequency-divided feedback signal are jumped to the first level, the controller output The first control signal and second control signal jump are second electrical level, and keep jump after a certain period of time for the first electricity It is flat；

First level is higher than the second electrical level.

Optionally, in the phase-locked loop circuit, the phase frequency detector includes the first d type flip flop, the second d type flip flop And NAND gate, in which:

The first control signal and the reference clock signal are provided to the input terminal of first d type flip flop；

The second control signal and the frequency-divided feedback signal are provided to the input terminal of second d type flip flop；

First d type flip flop exports the first trigger signal, and second d type flip flop exports the second trigger signal；

First trigger signal and second trigger signal are provided to the NAND gate, the NAND gate output signal It is provided to the controller；

When the phase-locked loop circuit initialization, the first control signal and described second of the controller output Control signal is the first level；

When the phase-locked loop circuit is in the lock state, the reference clock signal and the frequency-divided feedback signal jump to When the first level, the first control signal of the controller output and second control signal jump are second electrical level.

Optionally, in the phase-locked loop circuit, the phase-locked loop circuit further includes voltage controlled oscillator, the voltage-controlled vibration It swings device and provides the frequency-divided feedback signal for the phase frequency detector.

Optionally, in the phase-locked loop circuit, the phase-locked loop circuit further includes counter, the counter connection The controller, in which:

The clock of the counter is the output clock of voltage controlled oscillator, the frequency of the output clock of the voltage controlled oscillator It is N times of the frequency of the reference clock signal, wherein N is the loop divide multiple of phaselocked loop, and the counter counts multiple The period of the output clock of voltage controlled oscillator；

The first control signal of the controller output and second control signal jump are institute after second electrical level Counter is stated to start counting until 3/4N, the first control signal and the second control signal of the controller output are jumped Become the first level, the counter O reset.

Optionally, in the phase-locked loop circuit, the phase-locked loop circuit further includes frequency detection circuit, the frequency Detection circuit detects whether the phaselocked loop is in the lock state,

If so, the locking signal that the frequency detection circuit is sent to the controller is the first level, the control The first control signal and second control signal that device is provided to the phase frequency detector are the first level or second electrical level；

If it is not, the locking signal that then frequency detection circuit is sent to the controller is second electrical level, the control The first control signal and second control signal that device is provided to the phase frequency detector are the first level.

Optionally, in the phase-locked loop circuit, the frequency detection circuit includes thick step detector and fine detection Device, in which:

The thick step detector is composed in series by multiple edge triggered flip flops, and the thick step detector counts several pressures After the period of output clock for controlling oscillator, enables the fine detector and open.

Optionally, in the phase-locked loop circuit, rising edge of the fine detector in each reference clock signal The control word of the voltage controlled oscillator is detected, and the control word is successively stored in register, in which:

The control word that detects and the control word for being put into a register compare, if it is different, the then control word Effectively, which is put into corresponding register, then abandons the control word if they are the same, continue to test next control word, Next control word is continued compared with the control word for being put into a upper register；

After all having control word in six registers, six control words in register are compared, if wherein Difference between maximum control word and wherein the smallest control word is less than 3, then the frequency detection circuit is sent out to the controller The locking signal sent is the first level.

In phase-locked loop circuit provided by the invention, by when phase-locked loop circuit initialization, the of controller output One control signal and second control signal are the first level；When reference clock signal and frequency-divided feedback signal are jumped to the first level When, the first control signal of controller output and second control signal jump are second electrical level, and keep jumping after a certain period of time For the first level, realizes phase frequency detector and only just start after first control signal and second control signal become high level Work, therefore will not be detected by the adjacent rising edges that burr exists and generates, prevent burr signal from the information of mistake can be passed Phase frequency detector is passed, its phase demodulation mistake is caused.

Detailed description of the invention

Fig. 1 is the reference clock signal burr schematic diagram of existing phase-locked loop circuit；

Fig. 2 is the phase-locked loop circuit schematic diagram of one embodiment of the invention；

Fig. 3 is the reference clock signal burr schematic diagram of the phase-locked loop circuit of one embodiment of the invention；

Fig. 4 is the counter waveform diagram of the phase-locked loop circuit of one embodiment of the invention；

Fig. 5 is the frequency detection circuit schematic diagram of the phase-locked loop circuit of one embodiment of the invention；

It is as shown in the figure: 10- phase frequency detector；The first d type flip flop of 11-；The second d type flip flop of 12-；13- NAND gate；20- control Device processed；30- counter；40- frequency detection circuit.

Specific embodiment

Phase-locked loop circuit proposed by the present invention is described in further detail below in conjunction with the drawings and specific embodiments.According to Explanation and claims, advantages and features of the invention will become apparent from below.Simplify very much it should be noted that attached drawing is all made of Form and use non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.

Core of the invention thought is to provide a kind of phase-locked loop circuit, to solve existing phase-locked loop circuit reference clock Signal has the problem of burr.

To realize above-mentioned thought, the present invention provides a kind of phase-locked loop circuit, the phase-locked loop circuit includes frequency and phase discrimination Device and controller, in which: reference clock signal and frequency-divided feedback signal are provided to the input terminal of the phase frequency detector；The control Device processed provides first control signal and second control signal to the phase frequency detector；When the phase-locked loop circuit initialization When, the first control signal and the second control signal of the controller output are the first level；When the reference When clock signal and the frequency-divided feedback signal are jumped to the first level, the first control signal of the controller output and institute Stating second control signal jump is second electrical level, and keeping jump after a certain period of time is the first level；First level is higher than The second electrical level.

The embodiment of the present invention provides a kind of phase-locked loop circuit, as shown in Fig. 2, the phase-locked loop circuit includes frequency and phase discrimination Device 10 and controller 20, in which: reference clock signal refclk and frequency-divided feedback signal fbclk are provided to the phase frequency detector 10 input terminal；The controller 20 provides first control signal D1 and second control signal D2 to the phase frequency detector 10； When the phase-locked loop circuit initialization, the first control signal D1 and second control that the controller 20 exports Signal D2 is the first level；When the reference clock signal refclk and the frequency-divided feedback signal fbclk are jumped to the first electricity Usually, the first control signal D1 and second control signal D2 jump that the controller 20 exports are second electrical level, And keeping jump after a certain period of time is the first level；First level (high level) is higher than the second electrical level (low level).

Specifically, as shown in Fig. 2, the phase frequency detector 10 includes the first d type flip flop in the phase-locked loop circuit 11, the second d type flip flop 12 and NAND gate 13, in which: the first control signal D1 and the reference clock signal refclk are mentioned It is supplied to the input terminal of first d type flip flop 11；The second control signal D2 and the frequency-divided feedback signal fbclk are provided to The input terminal of second d type flip flop 12；First d type flip flop 11 exports the first trigger signal up, second d type flip flop 12 the second trigger signal dn of output；The first trigger signal up and the second trigger signal dn are provided to the NAND gate 13,13 output signal of NAND gate is provided to the controller 20；As shown in figure 3, working as the phase-locked loop circuit initialization When, the first control signal D1 and the second control signal D2 that the controller 20 exports are the first level；When described When phase-locked loop circuit is in the lock state, and when the reference clock signal refclk and frequency-divided feedback signal fbclk is jumped When fading to the first level, the first control signal D1 and second control signal D2 jump that the controller 20 exports are Second electrical level.

Further, in the phase-locked loop circuit, the phase-locked loop circuit further includes voltage controlled oscillator, described voltage-controlled Oscillator is that the phase frequency detector 10 provides the frequency-divided feedback signal fbclk.The phase-locked loop circuit further includes counter 30, the counter 30 connects the controller 20, in which: as shown in figure 4, the clock of the counter 30 is voltage controlled oscillator Output clock, the output clock frequency of voltage controlled oscillator is N times of the frequency of reference clock signal refclk, then the counting The clock frequency of device 30 is N times of the frequency of reference clock signal refclk, and wherein N is the loop divide multiple of phaselocked loop, institute The period t_vco that counter 30 counts the output clock of multiple voltage controlled oscillators is stated, is then made in first control signal D1 jump Edge is risen, the frequency of first control signal D1 is identical as the frequency of the reference clock signal refclk；The controller 20 exports The first control signal D1 and the second control signal D2 jump be second electrical level after, the counter 30 starts counting Until 3/4N, the first control signal D1 and second control signal D2 jump that the controller 20 exports are the first electricity Flat, the counter 30 is reset.

Further, in the phase-locked loop circuit, the phase-locked loop circuit further includes frequency detection circuit 40, described Frequency detection circuit 40 detects whether the phaselocked loop is in the lock state, if so, the frequency detection circuit 40 is to described Controller 20 send locking signal lock be the first level, the controller 20 provided to the phase frequency detector 10 first Controlling signal D1 and second control signal D2 is the first level or second electrical level；If it is not, then the frequency detection circuit 40 is to institute The locking signal lock for stating the transmission of controller 20 is second electrical level, the controller 20 provided to the phase frequency detector 10 the One control signal D1 and second control signal D2 is the first level.

Specifically, the frequency detection circuit 40 includes thick step detector and fine inspection in the phase-locked loop circuit Survey device, in which: the thick step detector is composed in series by multiple edge triggered flip flops, and the thick step detector counts described in several After the period t_vco of the output clock of voltage controlled oscillator, enables the fine detector and open.The fine detector is each The rising edge of reference clock signal refclk detects the control word of the voltage controlled oscillator, and the control word is successively stored to and is posted In storage, in which: the control word that detects and the control word for being put into a register compare, if it is different, the then control Word processed is effective, which is put into corresponding register, then abandons the control word if they are the same, continues to test next control Word continues next control word compared with the control word for being put into a upper register；All have when in six registers After control word, six control words in register are compared, if maximum control word and wherein the smallest control word Between difference less than 3, then the frequency detection circuit 40 is sent to the controller 20 locking signal is the first level.

Frequency detector in Fig. 2 is made of a thick step detector and fine detector.Thick step detector is gone here and there by DFF The counter connect, it counts the period of several reference frequencies, and then providing a signal makes fine sensors work.Fine detection Device detects the control word of DCO in the rising edge of each reference clock, as shown in figure 5, first control word word1 is stored to deposit In device word1_reg, second control word and word1_reg detected compares, if it is different, then word2 be it is effective, it is put Into word2_reg, then abandon if they are the same.After waiting there are 6 control words to be stored to register, they are compared, if variation Amount less than 3, then it is assumed that loop be it is stable, provide lock signal be 1.

In phase-locked loop circuit provided by the invention, by when phase-locked loop circuit initialization, what controller 20 exported First control signal D1 and second control signal D2 is the first level；When reference clock signal refclk and frequency-divided feedback signal When fbclk is jumped to the first level, first control signal D1 and second control signal the D2 jump that controller 20 exports are second Level, and keeping jump after a certain period of time is the first level, realize phase frequency detector 10 only in first control signal D1 and Second control signal D2 just starts to work after becoming high level, therefore will not be detected by the adjacent rising edges that burr exists and generates It surveys, prevents burr signal from the information of mistake can be passed to phase frequency detector 10, lead to its phase demodulation mistake.

To sum up, the various configuration of phase-locked loop circuit is described in detail in above-described embodiment, certainly, the present invention include but Be not limited in above-mentioned implementation cited configuration, it is any converted on the basis of configuration provided by the above embodiment in Hold, belongs to the range that the present invention is protected.Those skilled in the art can draw inferences about other cases from one instance according to the content of above-described embodiment.

Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims Range.