CN109150170B - Phase-locked loop circuit - Google Patents

The invention provides a phase-locked loop circuit, which comprises a phase frequency detector and a controller, wherein: a reference clock signal and a frequency division feedback signal are provided to an input end of the phase frequency detector; the controller provides a first control signal and a second control signal to the phase frequency detector; when the phase-locked loop circuit initially works, the first control signal and the second control signal output by the controller are in a first level; when the reference clock signal and the frequency division feedback signal jump to a first level, the first control signal and the second control signal output by the controller jump to a second level, and jump to the first level after keeping for a certain time; the first level is higher than the second level.

Phase-locked loop circuit

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a phase-locked loop circuit.

Background

The phase-locked loop is a typical feedback control circuit, and utilizes an externally input reference signal to control the frequency and phase of an internal oscillation signal of the loop, so as to realize automatic tracking of the frequency of an output signal to the frequency of an input signal, and is generally used for a closed-loop tracking circuit. The method is mainly characterized by that it includes voltage-controlled oscillator and PLL IC (phase-locked loop integrated circuit), the voltage-controlled oscillator can give out a signal, one portion can be used as output, another portion can be compared with local oscillator signal produced by PLL IC by means of frequency division, in order to keep frequency constant, it must make phase difference do not change, if the phase difference is changed, the voltage of voltage output end of PLL IC can be changed, and can be used for controlling VCO, and can attain the goal of phase-locking, and can make the frequency and phase of controlled oscillator and input signal retain a definite relationship.

A low-jitter phase-locked loop requires that the input reference clock signal be glitch-free. However, the reference clock of the phase locked loop often has a large number of glitches due to reflections at the board level, interference from other clock signals, or other interference factors. As shown in fig. 1, these glitches may pass wrong information to the phase frequency detector, causing it to detect a wrong phase.

Refclk of fig. 1 is the reference clock signal of the phase locked loop, which carries glitches. fbclk is the feedback signal of a voltage controlled oscillator (DCO) divided by a frequency divider. width is the phase error of refclk and fbclk. The phase locked loop is already in lock with only a small fixed phase difference. However, when a glitch is in refclk, the short pulse shown in FIG. 1 can be used as the rising edge of the reference clock and phase-detect fbclk, resulting in a phase error. When the normal rising edge of refclk arrives, it is considered an advanced signal and width outputs a high level until the arrival of the next rising edge of the feedback clock. Its phase error becomes around one reference clock cycle. This phase error requires the phase locked loop to correct over time, resulting in large jitter.

The traditional method for eliminating the glitch is to filter an input reference clock by an RC analog circuit and a shaping circuit connected behind the RC analog circuit. The disadvantage is that if the glitch is strong, the RC filter does not filter the glitch, and shaping by the shaping circuit generates a high frequency signal, which affects the locking of the phase locked loop and generates large jitter.

Disclosure of Invention

The invention aims to provide a phase-locked loop circuit to solve the problem that a reference clock signal of the traditional phase-locked loop circuit has burrs.

In order to solve the above technical problem, the present invention provides a phase-locked loop circuit, which includes a phase frequency detector and a controller, wherein:

a reference clock signal and a frequency division feedback signal are provided to an input end of the phase frequency detector;

the controller provides a first control signal and a second control signal to the phase frequency detector;

when the phase-locked loop circuit initially works, the first control signal and the second control signal output by the controller are in a first level;

when the reference clock signal and the frequency division feedback signal jump to a first level, the first control signal and the second control signal output by the controller jump to a second level, and jump to the first level after keeping for a certain time;

the first level is higher than the second level.

Optionally, in the phase-locked loop circuit, the phase frequency detector includes a first D flip-flop, a second D flip-flop, and a nand gate, where:

the first control signal and the reference clock signal are provided to an input of the first D flip-flop;

the second control signal and the frequency division feedback signal are provided to an input terminal of the second D flip-flop;

the first D trigger outputs a first trigger signal, and the second D trigger outputs a second trigger signal;

the first trigger signal and the second trigger signal are provided to the nand gate, and the nand gate output signal is provided to the controller;

when the phase-locked loop circuit initially works, the first control signal and the second control signal output by the controller are in a first level;

when the phase-locked loop circuit is in a locked state and the reference clock signal and the frequency division feedback signal jump to a first level, the first control signal and the second control signal output by the controller jump to a second level.

Optionally, in the phase-locked loop circuit, the phase-locked loop circuit further includes a voltage-controlled oscillator, and the voltage-controlled oscillator provides the frequency division feedback signal for the phase frequency detector.

Optionally, in the phase-locked loop circuit, the phase-locked loop circuit further includes a counter, the counter is connected to the controller, wherein:

the clock of the counter is the output clock of the voltage-controlled oscillator, the frequency of the output clock of the voltage-controlled oscillator is N times of the frequency of the reference clock signal, wherein N is the loop frequency division multiple of the phase-locked loop, and the counter counts the period of the output clocks of the voltage-controlled oscillators;

after the first control signal and the second control signal output by the controller jump to the second level, the counter starts counting until 3/4N, the first control signal and the second control signal output by the controller jump to the first level, and the counter is cleared.

Optionally, in the phase-locked loop circuit, the phase-locked loop circuit further includes a frequency detection circuit, the frequency detection circuit detects whether the phase-locked loop is in a locked state,

if yes, the locking signal sent by the frequency detection circuit to the controller is at a first level, and a first control signal and a second control signal provided by the controller to the phase frequency detector are at the first level or a second level;

if not, the locking signal sent by the frequency detection circuit to the controller is at a second level, and the first control signal and the second control signal provided by the controller to the phase frequency detector are at a first level.

Optionally, in the phase-locked loop circuit, the frequency detection circuit includes a coarse step detector and a fine detector, wherein:

the coarse step detector is formed by connecting a plurality of edge triggers in series, and the fine step detector is enabled to be started after the coarse step detector counts a plurality of periods of output clocks of the voltage-controlled oscillator.

Optionally, in the phase-locked loop circuit, the fine detector detects a control word of the voltage-controlled oscillator at a rising edge of each reference clock signal, and stores the control word in a register in sequence, where:

comparing the detected control word with the control word put in the last register, if the control word is different, the control word is valid, putting the control word into the corresponding register, if the control word is the same, discarding the control word, continuously detecting the next control word, and continuously comparing the next control word with the control word put in the last register;

and when the six registers are all stored with control words, the six control words in the registers are compared, and if the difference between the largest control word and the smallest control word is less than 3, the locking signal sent by the frequency detection circuit to the controller is at a first level.

In the phase-locked loop circuit provided by the invention, when the phase-locked loop circuit initially works, a first control signal and a second control signal output by a controller are at a first level; when the reference clock signal and the frequency division feedback signal jump to the first level, the first control signal and the second control signal output by the controller jump to the second level and jump to the first level after keeping for a certain time, so that the phase frequency detector only starts to work after the first control signal and the second control signal change to the high level, and therefore adjacent rising edges generated by the existence of burrs cannot be detected, and the burr signals are prevented from transmitting wrong information to the phase frequency detector to cause phase detection errors of the phase frequency detector.

Drawings

FIG. 1 is a diagram of reference clock signal glitches of a prior art phase-locked loop circuit;

FIG. 2 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the invention;

FIG. 3 is a diagram illustrating reference clock glitches of a PLL circuit according to one embodiment of the present invention;

FIG. 4 is a diagram illustrating a counter waveform of a PLL circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a frequency detection circuit of a PLL circuit according to an embodiment of the present invention;

shown in the figure: 10-a phase frequency detector; 11-a first D flip-flop; 12-a second D flip-flop; 13-nand gate; 20-a controller; 30-a counter; 40-frequency detection circuit.

Detailed Description

The phase-locked loop circuit proposed by the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

The core idea of the invention is to provide a phase-locked loop circuit to solve the problem that the reference clock signal of the existing phase-locked loop circuit has glitches.

In order to achieve the above idea, the present invention provides a phase-locked loop circuit, which includes a phase frequency detector and a controller, wherein: a reference clock signal and a frequency division feedback signal are provided to an input end of the phase frequency detector; the controller provides a first control signal and a second control signal to the phase frequency detector; when the phase-locked loop circuit initially works, the first control signal and the second control signal output by the controller are in a first level; when the reference clock signal and the frequency division feedback signal jump to a first level, the first control signal and the second control signal output by the controller jump to a second level, and jump to the first level after keeping for a certain time; the first level is higher than the second level.

The frequency detector in fig. 2 consists of a coarse step detector and a fine detector. The coarse step detector is a counter concatenated by DFFs that counts a number of cycles of a reference frequency and then gives a signal to operate the fine detector. The fine detector detects the control word of the DCO at every rising edge of the reference clock, as shown in fig. 5, the first control word1 is stored in the register word1_ reg, the second control word detected is compared with word1_ reg, if different, word2 is valid, it is put in word2_ reg, if identical, it is discarded. After waiting for 6 control words to be stored in the register, they are compared, and if the variance is less than 3, the loop is considered to be stable, giving a lock signal of 1.

In summary, the above embodiments describe the different configurations of the phase-locked loop circuit in detail, and it goes without saying that the present invention includes but is not limited to the configurations listed in the above embodiments, and any modifications based on the configurations provided by the above embodiments are within the scope of the present invention. One skilled in the art can take the contents of the above embodiments to take a counter-measure.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.