CN109302057A - One kind times source circuit, charge pump circuit and electronic equipment - Google Patents

This application discloses a kind of times source circuits, charge pump circuit and electronic equipment, wherein, described times of source circuit uses transmission transistor of the P-type transistor as voltage, and P-type transistor is using N trap as substrate, and N trap can connect any current potential above Ground, therefore the substrate of P-type transistor can directly be connect with the source electrode of P-type transistor, the source voltage for avoiding N-type transistor of the existing CMOS type times potential source due to playing voltage transfer function is higher than bulk effect caused by underlayer voltage, improve the efficiency of transistor transfer overvoltage, to improve the whole efficiency of times source circuit；And by giving the suitable dynamic bias circuit of P-type transistor gate design, based on the non-overlapping clock of two-phase orderly control the first transistor, second transistor, third transistor and the 4th transistor on and off, described times of source circuit can effectively avoid the current reflux problem that classical CMOS type times source circuit switching moments occur.

Voltage-multiplying source circuit, charge pump circuit and electronic equipment

Technical Field

The present disclosure relates to the field of circuit design technologies, and more particularly, to a voltage-doubling source circuit, a charge pump circuit, and an electronic device.

Background

The voltage doubling source circuit is a circuit for amplifying an input voltage, and generally, the amplification factor of the voltage doubling source circuit is 2, that is, for example, when the input voltage of the voltage doubling source circuit is VDD, the output voltage processed by the voltage doubling source circuit is 2 VDD.

The voltage doubling source circuit is widely applied to chips of various electronic devices such as a Flash Memory (Flash), a Dynamic Random Access Memory (DRAM), a driving circuit of a liquid crystal display and the like. In the existing voltage doubling source circuit, because the doping types of a transistor for transmitting voltage and a wafer for preparing the voltage doubling source circuit are different, the substrate of the transistor can only be grounded, so that the source voltage of the transistor is greater than the substrate voltage, a serious body effect is caused, the voltage transmission efficiency of the transistors is reduced, and the overall efficiency of the voltage doubling source circuit is further reduced.

Disclosure of Invention

In order to solve the technical problem, the application provides a voltage-multiplying source circuit, a charge pump circuit and an electronic device, so as to achieve the purpose of improving the efficiency of the voltage-multiplying source circuit.

In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:

a voltage doubler source circuit comprising: the circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, a first selective bias module, a second selective bias module, a first clock module and a second clock module; wherein,

the first clock module comprises a first clock output end and a second clock output end, wherein the first clock output end is used for outputting a first clock signal, and the second clock output end is used for outputting a second clock signal;

the second clock module comprises a third clock output end and a fourth clock output end, the third clock output end is used for outputting a third clock signal, the fourth clock output end is used for outputting a fourth clock signal, the time sequences of the first clock signal and the second clock signal are opposite, the time sequences of the third clock signal and the fourth clock signal are opposite, and the time sequences of the first clock signal and the third clock signal are opposite;

the first selective bias module comprises a first input end, a first output end and a second output end, the first input end is connected with the first clock output end, the first output end is connected with the grid electrode of the first transistor, the second output end is connected with the source electrode of the first transistor and one end of the first capacitor, which is far away from the second output end, is connected with the second clock output end;

the drain electrode of the first transistor is connected with a first power supply input end;

the first selective bias module is used for turning on the first transistor when the first clock signal is at a high level and the second clock signal is at a low level; when the first clock signal is at a low level and the second clock signal is at a high level, the first transistor is turned off;

the second selective bias module comprises a second input end, a third output end and a fourth output end, the second input end is connected with the third clock output end, the third output end is connected with the grid electrode of the second transistor, the fourth output end is connected with the source electrode of the second transistor and one end of the second capacitor, which is far away from the fourth output end, is connected with the fourth clock output end;

the drain electrode of the second transistor is connected with a second power supply input end;

the second selective bias module is configured to turn on the second transistor when the third clock signal is at a high level and the fourth clock signal is at a low level; when the third clock signal is at a low level and the fourth clock signal is at a high level, turning off the second transistor;

the grid electrode of the third transistor is connected with the second output end, the source electrode of the third transistor is connected with the fourth output end, and the drain electrode of the third transistor is connected with the drain electrode of the fourth transistor and serves as a signal output end;

the grid electrode of the fourth transistor is connected with the fourth output end, and the source electrode of the fourth transistor is connected with the second output end;

the first transistor, the second transistor, the third transistor and the fourth transistor are all P-type transistors.

Optionally, the first selective bias module includes: a fifth transistor and a sixth transistor;

a gate of the fifth transistor is connected with a gate of the sixth transistor to serve as the first input end, a drain of the fifth transistor is used for receiving a first fixed potential, a substrate of the fifth transistor is used for receiving the first fixed potential, and a source of the fifth transistor is connected with the drain of the sixth transistor to serve as the first output end;

and the substrate of the sixth transistor is connected with the source electrode of the sixth transistor and used as the second output end.

Optionally, the first fixed potential is a low level or a zero potential.

Optionally, the second selective bias module includes: a seventh transistor and an eighth transistor;

a gate of the seventh transistor is connected with a gate of the eighth transistor to serve as the first input terminal, a drain of the seventh transistor is used for receiving a second fixed potential, a substrate of the seventh transistor is used for receiving the second fixed potential, and a source of the seventh transistor is connected with the drain of the eighth transistor to serve as the first output terminal;

and the substrate of the eighth transistor is connected with the source electrode of the eighth transistor and used as the second output end.

Optionally, the second fixed potential is a low level or a zero potential.

Optionally, the first clock module is a first inverter;

an input end of the first inverter is used for receiving the first clock signal and is used as the first clock output end; the output end of the first inverter is used as the second clock output end;

the first inverter is used for outputting the second clock signal after processing the first clock signal.

Optionally, the second clock module is a second inverter;

the input end of the second inverter is used for receiving the third clock signal and is used as the third clock output end; the output end of the second inverter is used as the output end of the fourth clock;

the second inverter is used for outputting the fourth clock signal after processing the third clock signal.

Optionally, the method further includes: a third capacitor;

one end of the third capacitor is connected with the drain electrode of the third transistor, and the other end of the third capacitor is grounded.

A charge pump circuit comprises a plurality of voltage-multiplying source circuits which are sequentially connected in series, wherein the voltage-multiplying source circuit is any one of the voltage-multiplying source circuits.

An electronic device comprising a voltage-multiplying source circuit as claimed in any one of the preceding claims.

As can be seen from the foregoing technical solutions, an embodiment of the present application provides a voltage doubling source circuit, a charge pump circuit, and an electronic device, wherein the voltage doubling source circuit employs a first transistor and a second transistor as transfer transistors for an input voltage, a third transistor as a transfer transistor for an output voltage obtained by voltage doubling of an input voltage by a first capacitor, and a fourth transistor as a transfer transistor for an output voltage obtained by voltage doubling of an input voltage by a second capacitor, and the first transistor, the second transistor, the third transistor, and the fourth transistor are P-type transistors, and the P-type transistor uses an N-well as a base, and the N-well can be connected to any potential higher than ground, so that the base of the P-type transistor can be directly connected to a source of the P-type transistor, thereby avoiding a bulk effect of an existing CMOS-type voltage doubling source due to a source voltage of the N-type transistor having a voltage transfer function higher than a substrate voltage, the efficiency of the transistor for transmitting voltage is improved, and therefore the overall efficiency of the voltage-multiplying source circuit is improved.

And by designing a proper dynamic bias circuit for the grid electrode of the P-type transistor and sequentially controlling the on and off of the first transistor, the second transistor, the third transistor and the fourth transistor based on a two-phase non-overlapping clock, the voltage-multiplying source circuit can effectively avoid the current backflow problem which occurs at the moment of switching of a classical CMOS (complementary metal oxide semiconductor) type voltage-multiplying source circuit.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a voltage-doubling source circuit in the prior art;

FIG. 2 is a timing diagram of two phase non-overlapping clock signals;

fig. 3 is a schematic circuit diagram of a voltage-doubling source circuit according to an embodiment of the present application;

fig. 4 is a schematic circuit diagram of a voltage-doubling source circuit according to another embodiment of the present application;

fig. 5 is a schematic circuit diagram of a voltage-doubling source circuit according to another embodiment of the present application;

fig. 6 is a schematic circuit diagram of a voltage-doubling source circuit according to still another embodiment of the present application.

Detailed Description

As described in the background, in the conventional voltage doubling source circuit, the problem of the body effect caused by the difference of doping types between the transistors for transmitting the voltage and the wafer for preparing the voltage doubling source circuit is reduced, so that the efficiency of transmitting the voltage of the transistors is reduced, and the overall efficiency of the voltage doubling source circuit is further reduced.

As shown in fig. 1, fig. 1 is a schematic circuit structure diagram of a voltage-doubling source circuit in the prior art, where the voltage-doubling source circuit is composed of a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, and a second capacitor C2, where the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are cross-coupled, and a specific connection relationship is as shown in fig. 1; in fig. 1, one end of the first capacitor C1 away from the first transistor M1 is used for inputting the first clock signal CK, and one end of the second capacitor C2 away from the second transistor M2 is used for inputting the second clock signal CKB, and the timings of the first clock signal CK and the second clock signal CKB are opposite. In operation, when the first clock signal CK is at a high level and the second clock signal CKB is at a low level, the second transistor M2 and the fourth transistor M4 are turned on, the first transistor M1 and the third transistor M3 are turned off, the input voltage VDD is transferred to one end of the second capacitor C2 by the second transistor M2, the first capacitor C1 is multiplied by the voltage to form 2VDD, and the 2VDD is output to the output terminal through the turned-on fourth transistor M4. When the first clock signal CK is at a low level and the second clock signal CKB is at a high level, the first transistor M1 and the third transistor M3 are turned on, the second transistor M2 and the fourth transistor M4 are turned off, the input voltage VDD is transferred to one end of the first capacitor C1 by the first transistor M1, the second capacitor C2 is multiplied by voltage to form 2VDD, and the 2VDD is output to the output terminal VOUT through the turned-on third transistor M3.

However, in the circuit structure shown in fig. 1, since the wafer used in the integrated circuit manufacturing process is usually a P-type wafer, the first transistor M1 and the second transistor M2 are N-type transistors, the N-type transistor needs to be based on a P-well, the P-well can only be Grounded (GND), while the sources of the first transistor M1 and the second transistor M2 need to receive the input voltage VDD, the source voltage is greater than the substrate voltage, which causes a severe body effect in the first transistor M1 and the second transistor M2, resulting in an increase in the threshold voltage and the equivalent resistance of the first transistor M1 and the second transistor M2, not only increasing the on-time of the first transistor M1 and the second transistor M2, and the amplitude of the voltage transferred by the first transistor M1 and the second transistor M2 is reduced, so that the efficiency of transferring the voltage by the first transistor M1 and the second transistor M2 is reduced, thereby reducing the overall efficiency of the voltage-doubler circuit. This problem is particularly acute at certain process corner and temperature conditions.

It should be noted that, since the first clock signal CK and the second clock signal CKB are not ideal inverted clocks, there is usually a delay when the clock signal transitions from high level to low level or from low level to high level (fig. 2 shows two-phase non-overlapped clocks, which is a clock delay introduced by a common inverter), which may cause the current backflow problem of the first transistor M1 and the second transistor M2, and the current backflow problem of the third transistor M3 and the current backflow problem of the fourth transistor M4 to different degrees, further reducing the efficiency of the voltage-doubling source circuit.

As with the two-phase non-overlapping clock shown in fig. 2, assuming that the first clock signal CK is a clock signal shown by a waveform C11 and the second clock signal CKB is a clock signal shown by a waveform C22, when the first clock signal CK is converted from a high level to a low level, the second clock signal CKB is still at a low level due to a delay T1, at this time, the first transistor M1 and the second transistor M2 are both turned off, but the source voltage of the fourth transistor M4 is 2VDD, the gate voltage is VDD, and the drain voltage is VDD, so that the second clock signal CKB is kept in an on state, and since there is no input voltage, the output voltage of the 2VDD at the output terminal flows into the voltage doubling source circuit through the fourth transistor M4, which causes the amplitude of the output voltage of the voltage doubling source circuit to be reduced, and the efficiency of the voltage doubling source circuit is further reduced.

Likewise, when the first clock signal CK is switched from low level to high level, due to the delay T2, the second clock signal CKB is switched from high level to low level early by T2 time, and the output voltage of 2VDD at the output terminal flows into the voltage doubling source circuit through the opened third transistor M3, which causes the amplitude of the output voltage of the voltage doubling source circuit to be reduced, further reducing the efficiency of the voltage doubling source circuit.

Assume that when the first clock signal CK is first switched from low level to high level and the second clock signal CKB is switched from high level to low level at time T1, the second transistor M2 remains turned on for the delay time T1, so that leakage current occurs. Therefore, when the voltage-doubling source circuit in the prior art applies a two-phase non-overlapping clock, a current backflow situation also occurs, and the efficiency of the voltage-doubling source circuit is reduced.

In view of the above, embodiments of the present application provide a voltage doubling source circuit, a charge pump circuit and an electronic device, wherein the voltage doubling source circuit employs a first transistor and a second transistor as transfer transistors for an input voltage, a third transistor as a transfer transistor for an output voltage obtained by multiplying the input voltage by a first capacitor, and a fourth transistor as a transfer transistor for an output voltage obtained by multiplying the input voltage by a second capacitor, and the first transistor, the second transistor, the third transistor and the fourth transistor are P-type transistors, and the P-type transistor is based on an N-well, and the N-well can be connected to any potential higher than ground, so that the base of the P-type transistor can be directly connected to the source of the P-type transistor, a bulk effect caused by the source voltage higher than the substrate voltage is avoided, and the efficiency of the transfer voltage of the transistor is improved, thereby improving the overall efficiency of the voltage-multiplying source circuit.

And when the voltage-doubling source circuit uses the two-phase non-overlapping clock as shown in fig. 2, the third transistor and the fourth transistor are turned off in advance in the delay time, so that the situation of voltage backflow of the output end is avoided, and the overall efficiency of the voltage-doubling source circuit is further improved.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

An embodiment of the present application provides a voltage-doubling source circuit, as shown in fig. 3, including: a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first capacitor C1, a second capacitor C2, a first selective bias module 10, a second selective bias module 20, a first clock module 30 and a second clock module 40; wherein,

the first clock module 30 includes a first clock output end and a second clock output end, the first clock output end is used for outputting a first clock signal, and the second clock output end is used for outputting a second clock signal;

the second clock module 40 includes a third clock output end and a fourth clock output end, the third clock output end is configured to output a third clock signal, the fourth clock output end is configured to output a fourth clock signal, the timings of the first clock signal and the second clock signal are opposite, the timings of the third clock signal and the fourth clock signal are opposite, and the timings of the first clock signal and the third clock signal are opposite;

the first selective bias module 10 includes a first input terminal connected to the first clock output terminal, a first output terminal connected to the gate of the first transistor Q1, and a second output terminal connected to the source of the first transistor Q1 and one end of the first capacitor C1, wherein one end of the first capacitor C1 away from the second output terminal is connected to the second clock output terminal;

the drain electrode of the first transistor Q1 is connected with a first power supply input end;

the first selective bias module 10 is configured to turn on the first transistor Q1 when the first clock signal is at a high level and the second clock signal is at a low level; when the first clock signal is at a low level and the second clock signal is at a high level, the first transistor Q1 is turned off;

the second selective bias module 20 includes a second input terminal connected to the third clock output terminal, a third output terminal connected to the gate of the second transistor Q2, and a fourth output terminal connected to the source of the second transistor Q2 and one end of the second capacitor C2, one end of the second capacitor C2 remote from the fourth output terminal is connected to the fourth clock output terminal;

the drain electrode of the second transistor Q2 is connected with a second power supply input end;

the second selective bias module 20 is configured to turn on the second transistor Q2 when the third clock signal is at a high level and the fourth clock signal is at a low level; when the third clock signal is at a low level and the fourth clock signal is at a high level, turning off the second transistor Q2;

a gate of the third transistor Q3 is connected to the second output terminal, a source thereof is connected to the fourth output terminal, and a drain thereof is connected to a drain of the fourth transistor Q4, as a signal output terminal VOUT;

the gate of the fourth transistor Q4 is connected to the fourth output terminal, and the source is connected to the second output terminal;

the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 are all P-type transistors.

In the actual operation of the voltage-doubling source circuit provided by this embodiment, when the first clock signal and the fourth clock signal are at a high level and the second clock signal and the third clock signal are at a low level, the first selection bias module 10 turns on the first transistor Q1, and the input voltage VDD is efficiently transmitted to the node N because the first transistor Q1 is a P-type transistor. At this time, the node NB is at 2VDD, the second clock signal and the third clock signal are at low level, the 2VDD potential at the node NB is biased to the gate of the second transistor Q2, the second transistor Q2 is turned off, and in the process, the third transistor Q3 transmits 2VDD voltage to the signal output terminal, and the fourth transistor Q4 is turned off.

When the first and fourth clock signals are at a low level and the second and third clock signals are at a high level, the first selection bias block 10 turns off the first transistor Q1, the second selection bias block 20 turns on the second transistor Q2, and the low level is biased to the gate of the second transistor Q2. Since the second transistor Q2 is a P-type transistor, the input voltage VDD is efficiently transmitted to the node NB. At this time, the node N is at 2VDD, the first clock signal and the fourth clock signal are at ground potential, the second selective bias module 20 biases the 2VDD potential of the N node to the gate of the first transistor Q1, and the first transistor Q1 is turned off. At this stage, the fourth transistor Q4 transmits the 2VDD voltage to the signal output terminal, and the third transistor Q3 is turned off.

Still referring to fig. 2, when the first clock signal is the clock signal shown as C11 and the third clock signal is the clock signal shown as C22, the second clock signal is the inverse clock signal of the first clock signal and the fourth clock signal is the inverse clock signal of the third clock signal. When the first clock signal is converted from high level to low level and the third clock signal is converted from low level to high level, assuming that there is a delay T1, in the time period T1, the first clock signal and the third clock signal are both low level, the second clock signal and the fourth clock signal are both high level, the third transistor Q3 is turned off first, at this time, the fourth transistor Q4 is also in an off state, only after the delay T1, the third clock signal is converted to high level, and when the fourth clock signal is converted to low level, the fourth transistor Q4 is turned on to perform normal output of 2VDD, thereby avoiding the situation that the 2VDD voltage at the signal output end flows back to the inside of the voltage doubling source through the third transistor Q3 during the switching conversion process.

Similarly, when the third clock signal is switched from high level to low level and the first clock signal is switched from low level to high level, the third clock signal is switched to low level earlier than T2, and similarly, in this embodiment, the fourth transistor Q4 is turned off first, and the third transistor Q3 is also turned off at this time, and only after the delay T2, when the first clock signal is switched to high level, the third transistor Q3 will turn on the normal 2VDD output, so that the situation that the 2VDD voltage at the signal output terminal flows back to the voltage doubling source through the fourth transistor Q4 during the switching conversion process is avoided.

On the basis of the above embodiments, an embodiment of the present application provides a possible configuration of the first bias module and the second bias module, as shown in fig. 4, where the first selective bias module 10 includes: a fifth transistor Q5 and a sixth transistor Q6;

the gate of the fifth transistor Q5 is connected to the gate of the sixth transistor Q6 as the first input terminal, the drain of the fifth transistor Q5 is configured to receive a first fixed potential, the substrate of the fifth transistor Q5 is configured to receive the first fixed potential, and the source of the fifth transistor Q5 is connected to the drain of the sixth transistor Q6 as the first output terminal;

the substrate of the sixth transistor Q6 is connected to the source of the sixth transistor Q6 as the second output terminal.

The second selection bias module 20 includes: a seventh transistor Q7 and an eighth transistor Q8;

the gate of the seventh transistor Q7 is connected to the gate of the eighth transistor Q8 as the first input terminal, the drain of the seventh transistor Q7 is configured to receive a second fixed potential, the substrate of the seventh transistor Q7 is configured to receive the second fixed potential, and the source of the seventh transistor Q7 is connected to the drain of the eighth transistor Q8 as the first output terminal;

the substrate of the eighth transistor Q8 is connected to the source of the eighth transistor Q8 as the second output terminal.

Optionally, the first fixed potential is a low level or a zero potential.

Optionally, the second fixed potential is a low level or a zero potential. In fig. 4, reference VSS denotes a zero potential or a ground potential.

Optionally, the fifth transistor Q5 and the seventh transistor Q7 are N-type transistors, and the substrate of the N-type transistor is grounded; the sixth transistor Q6 and the eighth transistor Q8 are P-type transistors, the substrate of which is connected to the source.

On the basis of the above embodiments, another embodiment of the present application provides a feasible configuration of the first clock module 30 and the second clock module 40, as shown in fig. 5, where the first clock module 30 is a first inverter 31;

an input end of the first inverter 31 is configured to receive the first clock signal as the first clock output end; the output end of the first inverter 31 is used as the second clock output end;

the first inverter 31 is configured to process the first clock signal and output the second clock signal.

The second clock module 40 is a second inverter 41;

an input end of the second inverter 41 is configured to receive the third clock signal as the third clock output end; the output end of the second inverter 41 serves as the fourth clock output end;

the second inverter 41 is configured to output the fourth clock signal after processing the third clock signal.

Still referring to fig. 5, a first operating voltage input terminal of the first inverter 31 is configured to receive a high level (for example, may be an operating voltage VDD), and a second operating voltage input terminal of the first inverter 31 is configured to receive a low level (for example, may be a zero potential or a ground potential VSS); a first operating voltage input terminal of the second inverter 41 is configured to receive a high level, and a second operating voltage input terminal of the second inverter 41 is configured to receive a low level.

On the basis of the above embodiment, in a further embodiment of the present application, as shown in fig. 6, the voltage doubling source circuit further includes:

a third capacitance C3;

one end of the third capacitor C3 is connected to the drain of the third transistor Q3, and the other end of the third capacitor C3 is grounded.

The third capacitor C3 is used for decoupling the voltage signal output by the signal output terminal.

Correspondingly, the embodiment of the application also provides a charge pump circuit, which comprises a plurality of voltage-multiplying source circuits which are sequentially connected in series, wherein the voltage-multiplying source circuits are the voltage-multiplying source circuits in any embodiment.

Correspondingly, an embodiment of the present application further provides an electronic device, including the voltage-doubling source circuit according to any of the above embodiments.

In summary, the present invention provides a voltage doubling source circuit, a charge pump circuit and an electronic device, wherein the voltage doubling source circuit employs a first transistor and a second transistor as transfer transistors of an input voltage, a third transistor as a transfer transistor of an output voltage obtained by doubling the input voltage with a first capacitor, and a fourth transistor as a transfer transistor of an output voltage obtained by doubling the input voltage with a second capacitor, and the first transistor, the second transistor, the third transistor and the fourth transistor are P-type transistors, and the P-type transistor uses an N-well as a base, and the N-well can be connected to any potential higher than ground, so that the base of the P-type transistor can be directly connected to the source of the P-type transistor, thereby avoiding a bulk effect caused by the source voltage of the N-type transistor functioning as a voltage transfer function being higher than the substrate voltage in the conventional CMOS voltage doubling source, the efficiency of the transistor for transmitting voltage is improved, and therefore the overall efficiency of the voltage-multiplying source circuit is improved.

And by designing a proper dynamic bias circuit for the grid electrode of the P-type transistor and sequentially controlling the on and off of the first transistor, the second transistor, the third transistor and the fourth transistor based on a two-phase non-overlapping clock, the voltage-multiplying source circuit can effectively avoid the current backflow problem which occurs at the moment of switching of a classical CMOS (complementary metal oxide semiconductor) type voltage-multiplying source circuit.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.