CN109492740B - Voltage converter and radio frequency identification device - Google Patents

To reduce the on-resistance, the overdrive voltage of the transistors or the number of transistors in the critical path can be increased on the one hand, and the size of the transistors can be increased on the other hand. However, as the size of the tft increases, the parasitic capacitance between the gate and drain of the tft increases accordingly, which makes the voltage value at which the clock signal CLKA/CLKB can be capacitively coupled to the nodes a1, a2, B1, B2 smaller. In addition, the diode-connected transistors N3, N4, N7, and N8 have threshold voltage loss during voltage transmission, which leads to a decrease in the output voltage of the

100 and a decrease in energy conversion efficiency.

As shown in fig. 2, the

200 includes a

210 and 220 and an

230, wherein the

210 receives the voltage signal VIN to perform a first voltage boosting, and the

220 is used to boost the boosted voltage signal again and then output the boosted voltage signal to the

230 to output a voltage signal VOUT which is boosted twice.

It is understood that in other embodiments, the

200 may further include other numbers of boosting units connected in series to boost the received voltage signal VIN step by step.

The

300 includes

310 and 320 and an

330 connected in series. Specifically, the

310 includes symmetrically disposed

311, 312, the

320 includes symmetrically disposed

321, 322, and the

330 includes symmetrically disposed

331, 332. The clock signal CLKA is coupled to the output terminal a1 of the voltage boosting unit 310 (i.e., the common node between the

311 and 321) and the output terminal B2 of the voltage boosting unit 320 (i.e., the common node between the

322 and 332) through capacitors C1, C4, respectively, and similarly, the clock signal CLKB is coupled to the output terminal a2 of the voltage boosting unit 310 (i.e., the common node between the

312 and 321) and the output terminal B1 of the voltage boosting unit 320 (i.e., the common node between the

321 and 331) through capacitor C2, respectively. Input terminal V of

310_INFor receiving the voltage signal VDD. The

330 receives a signal from the

320, is coupled to the reference potential GND via the resistor R and the capacitor C5, and provides a stable direct voltage at a common node (i.e., an output terminal) of the

331, 332.

As can be seen from fig. 3, the boosting

310 and 320 in the

300 each include two symmetrical transistors and capacitors. By the cascade mode shown in fig. 3, the number of transistors on the critical path from the input terminal to the output terminal can be reduced, and the overdrive voltage of the transistors can be increased by controlling the thin film transistors in the booster cell with high potential. For a transistor operating in the linear region, its on-resistance r_onCan be approximately expressed as:

The voltage conversion circuit provided by the invention overcomes the threshold voltage loss of the transistor in the multi-stage boosting unit, and only the

330 has the threshold voltage loss which is not increased along with the order number, so the output voltage of the voltage conversion circuit can be expressed as:

When the clock signal CLKA is at the low potential 0V, it is coupled to the node a1 through the capacitor C1, thereby turning off the

312; when the clock signal CLKB is at the high potential of 5V, it is coupled to the node a2 through the capacitor C2, so that the

311 is turned on. In this state, the low potential of the node a1 is initialized to 5V.

When the clock signal CLKA is at the high potential of 5V, it is coupled to the node a1 through the capacitor C1, thereby causing the potential of the node a1 to be pulled up to 10V (2VDD), causing the

312 to be turned on; meanwhile, the clock signal CLKB is at a low level of 0V, coupled to node A2 through capacitor C2, causing

311 to turn off. In this state, the low potential of the node a2 is initialized to 5V.

Therefore, since the

310 and 320 are connected in series, the output of the

310 serves as the input of the

320, and charges the nodes B1 and B2.

When the clock signal CLKA is at the low potential of 0V, it is coupled to the node B2 through the capacitor C4, so that the

321 is turned off; meanwhile, the clock signal CLKB is at a high potential of 5V, coupled to the node B1 through the capacitor C3, and controls the

322 to be turned on. In this state, the high potential 10V (2VDD) of the node a2 charges the node B2 through the

322, so that the low potential of the node B2 is initialized to 10V (2 VDD).

When the clock signal CLKA is at the high potential of 5V, it is coupled to the node B2 through the capacitor C4, and the

321 is turned on; meanwhile, the clock signal CLKB is at a low level of 0V, coupled to node B1 through capacitor C3, causing

322 to turn off. In this state, the high potential of the node a1, 10V, charges the node B1, initializing the low potential of the node B1 to 10V (2 VDD).

Through the above process, the

300 is initialized so that the low potential of the nodes a1, a2 is 5V and the low potential of the nodes B1, B2 is 10V. In the subsequent working period, the potentials of the nodes A1 and A2 can be bootstrapped due to the capacitive coupling effect of the clock signal and change along with the change of the clock signal between 5V and 10V, and similarly, the potentials of the nodes B1 and B2 change along with the change of the clock signal between 10V and 15V.

The

330 receives the signals output by the nodes B1 and B2, and alternately charges and outputs the signals through the capacitor C5.

The inventors also simulated the

100, 300 and provided the following simulation comparison. The simulation conditions here are all load resistance of 100k Ω, and the transistor size and capacitance are the same, the threshold voltage of the TFT used for the simulation is 2.5V,

fig. 4b is a diagram showing an output simulation of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment. In the figure, a curve S1 is an output curve of the

300, and a curve S2 is an output curve of the

100. As can be seen from comparison of the curves S1 and S2, the output voltage of the

300 is significantly higher than the output voltage of the

100.

Fig. 4c is a simulation diagram of the output voltage of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment as a function of the load current. In the figure, a curve S3 corresponds to the

300, and a curve S4 corresponds to the

100. As can be seen from the figure, as the load current increases, the output voltage of the

100 significantly decreases, and the

300 can still output a voltage of about 18.5V when the load current is about 400 μ a, which is sufficient to drive the memory circuit EEPROM and the like in the RFID tag. Therefore, the

300 has stronger driving capability.

Fig. 4d is a simulation diagram of the output voltage of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment as a function of the threshold voltage. In the figure, a curve S5 corresponds to the

300, and a curve S6 corresponds to the

100. As can be seen from the figure, the output voltage of the

100 significantly decreases when the amount of threshold voltage shift is positive, whereas the output voltage of the

300 does not significantly decrease when the amount of threshold voltage shift is-6 to + 2V. As described above, the threshold voltage of the TFT used in the simulation is 2.5V, and when the threshold voltage shifts by +2V, the threshold voltage of the transistor is significantly biased, and the output voltage drop caused by the loss of the threshold voltage is dominant, so that the transistor connected in the form of a diode in the

100 causes the output voltage to drop significantly. In contrast, the

300 has a loss of the threshold voltage only in the output unit, and the influence of the threshold voltage on the output voltage is greatly improved.

Fig. 4e is a simulation diagram of the energy conversion efficiency of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment under different load currents. In the figure, a curve S7 corresponds to the

300, and a curve S8 corresponds to the

100. As can be seen, the intersection of the curve S7 and the curve S8 corresponds to a load current of 315 microamps. When the load current is less than 315 microampere, the energy conversion efficiency of the

100 is slightly higher than that of the

300, and when the load current is greater than 315 microampere, the opposite is true. For example, when the driving current of the

300 is 400 microamperes, the output voltage is 18.5V, and the energy conversion efficiency reaches 45%. In addition, when the load current is too large or too small, the energy conversion efficiency of the

100 is decreased, and the energy conversion efficiency of the

300 is increased, so that the

300 has strong driving capability and higher energy utilization rate.

Compared to the first embodiment, an

540 is also connected in series between the two boosting

510 and 520 of the present embodiment. As shown, the boosting

510 includes symmetrically disposed

511, 512, the boosting

520 includes symmetrically disposed

521, 522, the

530 includes symmetrically disposed

531, 532, and the

540 includes symmetrically disposed

541, 542.

Specifically, a first pole of

541 is coupled between the second pole of

511 and a first pole of

521, a first pole of

542 is coupled between the second pole of

512 and a first pole of

522, the second poles of

541 and 542 are connected, and the control poles of

541 and 542 are coupled to the control poles of

521 and 522, respectively.

When the clock signal CLKA is at the low potential 0V, the node a1 is at the low potential, so that the

512 is turned off; meanwhile, the clock signal CLKB is high at 5V, so that the node a2 is high, and the

511 is controlled to be turned on. In this state, the low potential of the node a1 is initialized to 5V.

When the clock signal CLKA is at the high potential of 5V, the potential of the node a1 is bootstrapped to the high potential of 10V, controlling the

512 to turn on; meanwhile, the clock signal CLKB is at the low potential of 0V, and the

511 is turned off. In this state, the power supply VDD charges the node a2, and the low potential of a2 is initialized to 5V.

The low potential of the output terminals B1, B2 of the boosting

520 is initialized by the

540 of the node a1 or a 2:

when the clock signal CLKA is at the low potential of 0V, the node B2 is at the low potential, so that the

521 and 541 are turned off; meanwhile, the clock signal CLKB is high at 5V, and the node B1 is high, so that the

522 and 545 are turned on. In this state, the node a2 charges the node B2, and the low potential of the node B2 is initialized to 10V.

When the clock signal CLKA is at a high voltage level of 5V, the voltage level at the node B2 is 15V, so that the

521 and 541 are turned on; meanwhile, the clock signal CLKB is at the low level 0V, and the node B1 is at the low level, so that the

522 and 542 are turned off. In this state, the node a1 charges the node B1, and the low potential of B1 is initialized to 10V.

Through the above process, the

400 is initialized so that the low potential of the nodes a1, a2 is 5V and the low potential of the nodes B1, B2 is 10V. In the subsequent working period, the potentials of the nodes A1 and A2 change with the change of the clock signal between 5V and 10V, and the potentials of the nodes B1 and B2 change with the change of the clock signal between 10V and 15V.

Please continue to refer to fig. 5. When CLKA is high, the potentials of the nodes B1 and B2 are 10V and 15V, respectively, and at this time, the

541 is turned on, so that the first electrode of the

522 is 10V and the second electrode is 15V, and is in an off state. Thus, node B2 can only leak in the reverse direction by the leakage current of the

522 that is turned off, and for transistors with negative threshold voltages, the reverse leakage current I_leakThe size is as follows:

where μ is the channel surface mobility, Cox is the gate oxide capacitance per unit area, W is the effective channel width, and L is the effective channel length. Therefore, with the above arrangement, the

522 can be made to be in the off state, and the reverse leakage current I discharging the node B2 can be made to occur_leakLess than the leakage current of

522 in saturation, thereby reducing the leakage current I due to reverse_leakThe resulting voltage drop increases the range of output voltages.

As can be seen from the above, the

540 can reduce the reverse leakage of the two transistors of the

520, and reduce the voltage ripple output by the

530.

Compared to the first embodiment, the transistors in the

600 in this embodiment are dual-gate transistors. Specifically, the boosting

610 includes two

611, 612, and Bottom Gates (BG) of the two transistors are cross-connected to output terminals a2, a1 of the boosting

610, respectively, and Top Gates (TG) are connected to an input terminal VIN (i.e., power supply VDD), respectively. The clock signals CLKA, CLKB are coupled to nodes a1, a2 via capacitors C1, C2, respectively.

Similarly, the bottom gates of

621, 622 in the

620 are cross-coupled to the output terminals B2, B1 of the boost unit, and the top gates are coupled to clock signals CLKA, CLKB, respectively. The clock signal CLKA is coupled to the node B2 through a capacitor C4 and the clock signal CLKB is coupled to the node B1 through a capacitor C3.

The

630 includes symmetrically arranged transistors 631, 632 having bottom gates coupled to nodes B1, B2, respectively, and top gates coupled to clock signals CLKB, CLKA, respectively.

Similar to the first embodiment, the low potential of the nodes a1 and a2 is initialized to 5V, and since the top gate potentials of the

611 and 612 are VDD, the threshold voltages of the

611 and 612 can be adjusted to be negative, so that the transistors can be completely turned on and the power voltage VDD can be transmitted to the node a1 or a2 without loss.

Also similar to the first embodiment, the low potential of both the nodes B1, B2 is initialized to 10V. In the initialization process, when the clock signal CLKA is at the low potential of 0V, the

621 is turned off, and the clock signal CLKA makes the top gate of the

621 be at the low potential, so as to adjust the threshold voltage of the

621 to be floating, which is beneficial to turning off the

621. Meanwhile, the clock signal CLKB is at a high potential of 5V, the node B1 is at a high potential, the

622 is turned on, and the top gate of the

622 controlled by the clock signal CLKB is at a high potential, so that the threshold voltage of the

622 is floated negatively, which is beneficial to turning on the

622.

Similarly, when the clock signal CLKA is at a high potential of 5V, the top gate of the

621 is at a high potential, so that the

621 is floated negatively, which is favorable for turning on the

621. The clock signal CLKB causes the top gate of the

622 to be at a low potential, which causes the threshold voltage of the

622 to be floating, facilitating the turn-off of the

622.

It is understood that the

611 and 612 in the

610 can also be replaced by single-gate thin film transistors, thereby avoiding the problem of reverse leakage that may be caused by the negative threshold voltage of the transistors, and meanwhile, there is no loss of threshold voltage.

In another embodiment, the top gates of the

611, 612 in the

610 are coupled to the clock signals CLKB, CLKA, respectively, so that the transistors in the

610, 620 can use the same dynamic voltage regulation manner, thereby turning on and off the

611, 612 more fully.

Similar to

500,

600 may also include an isolation cell (not shown), and accordingly, the top gates of the symmetrically disposed transistors in the isolation cell are capacitively coupled to their own first poles, respectively, i.e., receive clock signals CLKA, CLKB, respectively. It can be understood that in practical application, the top gate and the bottom gate as two control electrodes of the transistor can be replaced with each other as required without affecting the circuit function.

As shown, the

700 includes a transmitter 710 for receiving the RFID signal, a processor 720 for generating a reply signal based on the RFID signal, and a

730. In particular, the

730 generates a voltage signal under the influence of the radio frequency signal to power the processor 720.

In one embodiment, the processor 720 further includes a frequency divider 721 for generating clock signals, such as the first clock signal CLKA and the second clock signal CLKB, required for the operation of the

730 based on the rf signal.