CN109660219A - Calibration circuit, method, apparatus, equipment and the storage medium of power amplifier - Google Patents

Disclosure of Invention

In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a calibration circuit, a method, an apparatus, a device and a storage medium for a power amplifier, which can achieve accurate calibration of the power amplifier and can monitor the performance of the power amplifier in real time.

In a first aspect, the present invention provides a calibration circuit for a power amplifier, the calibration circuit comprising: little the control unit MCU, power amplifier, current sampling detection resistance and current detection chip, wherein:

the drain electrode input end of the power amplifier is connected with one end of the current sampling detection resistor, the grid electrode input end of the power amplifier is connected with the digital-to-analog conversion interface of the MCU, the output end of the current detection chip is connected with the digital-to-analog conversion interface of the MCU, and the input end of the current detection chip is connected with two ends of the current sampling detection resistor.

In a second aspect, the present invention provides a calibration method for a power amplifier, the method comprising:

turning off the radio frequency modulation signal of the power amplifier;

calibrating the quiescent current of the power amplifier by adjusting the gate voltage of the power amplifier;

turning on a radio frequency modulation signal of the power amplifier;

and calibrating the output power of the power amplifier by adjusting the input power of the power amplifier.

In one embodiment, the calibrating the quiescent current of the power amplifier by adjusting the gate voltage of the power amplifier includes:

circularly executing a first specified operation until the first quiescent current of the power amplifier is within a first preset range value;

the first specifying operation includes:

determining a first quiescent current according to a first present gate voltage of the power amplifier; when the first specified operation is executed for the first time, the first current gate voltage is an initial gate voltage, and when the first specified operation is not executed for the first time, the first current gate voltage is an adjusted first gate voltage obtained when the first specified operation is executed for the previous time;

judging whether the first quiescent current is within a first preset range value;

when the first static current is not in the first preset range value, adjusting the first current grid voltage to obtain an adjusted first grid voltage, and controlling to enter the next first appointed operation;

and when the first quiescent current is within a first preset range value, controlling not to enter the first appointed operation next time.

In one embodiment, determining the first quiescent current from a first present gate voltage of the power amplifier comprises:

acquiring the output voltage of the current detection chip; the output voltage and the first present gate voltage are positively correlated;

determining a first quiescent current of the power amplifier according to a formula Ids ═ Vout/(Gain ═ Rsense); and Ids is a first static current of the power amplifier, Vout is an output voltage of the current detection chip, Gain is a Gain of the current detection chip, and Rsense is a resistance value of the current sampling detection resistor.

In one embodiment, when the first static current is not within the first preset range, adjusting the current gate voltage value to obtain an adjusted first gate voltage includes:

when the first quiescent current is greater than the maximum value of the first preset range value, reducing the first current gate voltage by a first preset step length;

and when the first static current is smaller than the minimum value of the first preset range value, increasing the first current gate voltage by the first preset step length.

In one embodiment, after the cycling performs the first specified operation until the first quiescent current of the power amplifier is within the first preset range of values, the method further comprises:

circularly executing a second specified operation until a second quiescent current of the power amplifier is within a second preset range value; wherein:

the second designated operation includes:

determining a second quiescent current according to the second present gate voltage of the power amplifier; when the second specified operation is executed for the first time, the second current gate voltage is the adjusted first gate voltage, and when the second specified operation is not executed for the first time, the second current gate voltage is the adjusted second gate voltage;

judging whether the second quiescent current is within the second preset range value; the maximum value in the second preset range value is smaller than the maximum value in the first preset range value; the minimum value in the second preset range value is larger than the minimum value in the first preset range value;

when the second static current is not within the second preset range value, adjusting the second current grid voltage to obtain an adjusted second grid voltage, and controlling to enter the next second specified operation;

and when the second quiescent current is within the second preset range value, controlling not to enter the second specified operation next time.

In one embodiment, when the second quiescent current is not within the second preset range, adjusting the second present gate voltage to obtain an adjusted second gate voltage includes:

when the second quiescent current is greater than the maximum value of the second preset range value, reducing the second current gate voltage by the second preset step length; the second preset step length is smaller than the first preset step length;

and when the second quiescent current is smaller than the minimum value of the second preset range value, increasing the second current gate voltage by the second preset step length.

In one embodiment, the calibrating the output power of the power amplifier by adjusting the input power of the power amplifier comprises:

circularly executing a third specified operation until the dynamic current of the power amplifier is within a third preset range value;

the third specifying operation includes:

determining a dynamic current according to the current input power of the power amplifier; when the third designated operation is executed for the first time, the current input power is initial input power, and when the third operation is not executed for the first time, the current input power is adjusted input power obtained when the third designated operation is executed for the previous time;

judging whether the dynamic current is within a third preset range value or not;

when the dynamic current is not in a third preset range value, adjusting the current input power to obtain an adjusted input power, and controlling to enter a next third appointed operation;

and when the dynamic current is within a third preset threshold range, controlling not to enter the third appointed operation next time.

In one embodiment, when the dynamic current is not within a third preset range, adjusting the present input power to obtain an adjusted input power includes:

when the dynamic current is larger than the maximum value of the third preset range value, reducing the current input power by the third preset step length;

and when the dynamic current is smaller than the minimum value of the third preset range value, increasing the current input power by the third preset step length.

In one embodiment, the method further comprises:

determining an adjusted second gate voltage and the adjusted input power;

determining the current dynamic current of the power amplifier according to the second grid voltage and the regulated input power;

judging whether the current dynamic current is within a fourth preset range value or not;

when the current dynamic current is not within the fourth preset range, adjusting the second grid voltage to be zero, and turning off the radio frequency modulation signal.

In a third aspect, an embodiment of the present application provides an apparatus for calibrating an amplifier, where the apparatus includes:

a shutdown module configured to shut down a radio frequency modulation signal of the power amplifier;

the current calibration module is configured to calibrate the quiescent current of the power amplifier by adjusting the gate voltage of the power amplifier;

a starting module configured to start a radio frequency modulation signal of the power amplifier;

a power calibration module configured to calibrate an output power of the power amplifier by adjusting an input power of the power amplifier.

In a fourth aspect, an embodiment of the present application provides an apparatus, which includes a memory and a processor, where the memory stores a computer program, and the processor implements the calibration method of the power amplifier when executing the computer program.

In a fifth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the calibration method for a power amplifier.

The calibration circuit, the calibration method, the calibration device, the calibration equipment and the storage medium of the power amplifier provided by the embodiment of the invention are used for turning off the radio frequency modulation signal of the power amplifier, calibrating the quiescent current of the power amplifier by adjusting the grid voltage of the power amplifier, turning on the radio frequency modulation signal of the power amplifier, and calibrating the output power of the power amplifier by adjusting the input power of the power amplifier. According to the technical scheme, the influence of other current consumption devices in the calibration circuit on current detection can be eliminated, so that the calibration precision of the quiescent current can be improved, and the calibration of the quiescent current and the output power of the power amplifier can be simultaneously realized without additional test equipment, so that the calibration process is simpler and more convenient.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

As mentioned in the background art, as shown in fig. 1, the calibration circuit includes a power amplifier 10 and an MCU30, wherein the programmable power supply 20 is connected to a main board to be calibrated where the power amplifier 10 is located, a gate input terminal of the power amplifier 10 is connected to one end of an MCU30, and the other end of the MCU30 is connected to the upper computer 40, so as to implement serial port communication. The calibration of the power amplifier is generally realized by adopting a programmable power supply to be matched with an upper computer and an MCU (microprogrammed control Unit), wherein the programmable power supply is a standard power supply with stronger application, and the microcomputer technology is adopted to control the magnitude of current provided by the power supply to a circuit in real time; the upper computer is a computer capable of directly sending control commands, can adopt serial communication to send commands to the MCU to realize communication, and realizes bidirectional communication between the General-Purpose IO ports (General-Purpose IO ports for short) and the programmable power supply. The specific calibration process can be shown in fig. 2, firstly setting the gate voltage of the power amplifier to zero, collecting the whole machine current value of the main board to be calibrated through the programmable power supply, recording the current value as Ia, sending Ia to the upper computer, controlling and adjusting the output voltage of the digital-to-analog converter in the MCU through the upper computer, reading the corresponding whole machine current value by the upper computer, recording the current value as Ib, judging whether the difference value is within a preset range value according to the difference value between Ib and Ia, if not, increasing or decreasing the gate voltage by a preset step length through controlling the digital-to-analog converter in the MCU through the upper computer, as shown in fig. 2, the preset range is 240-260 mA, and the preset step length is 0.05v, so as to calibrate the quiescent current of the power amplifier, and implement the calibration of the output power of the power amplifier by adopting devices such as a spectrometer.

However, in the prior art, when the quiescent current is calibrated, the current sampling value includes current consumption of other components in the circuit to be calibrated, and the other components may cause large fluctuation of the sampling current in different operating modes, which results in low current calibration precision, and requires other additional test equipment in the output power calibration process, which results in high calibration cost and complex calibration process.

In view of the above defects in the prior art, the present application provides a calibration method for a power amplifier, which does not need to perform a difference calculation mode on current sampling values, eliminates the influence of other current consuming devices in a calibration circuit on current detection, directly adjusts the gate voltage to calibrate the quiescent current of the power amplifier, and adjusts the input power of the power amplifier to further calibrate the output power, thereby avoiding using other test equipment.

Fig. 3 is a schematic structural diagram of a calibration circuit of a power amplifier according to an embodiment of the present invention, and as shown in fig. 3, the circuit to be calibrated includes a micro control unit MCU30, a power amplifier 10, a current sampling detection resistor 60, and a current detection chip 50, where a drain input end of the power amplifier 10 is connected to one end of the current sampling detection resistor 60, a gate input end of the power amplifier 10 is connected to a digital-to-analog conversion interface (DAC) of the MCU30, an output end of the current detection chip 50 is connected to an analog-to-digital conversion interface (ADC) of the MCU30, and an input end of the current detection chip 50 is connected to two ends of the current sampling detection resistor 60.

Specifically, the current detection chip 50 may select a voltage output type chip MAX44284, an input end of the current detection chip is connected to two ends of the current sampling resistor 60, the current detection chip may be used to detect the drain current of the power amplifier 10, and the output voltage is proportional to the voltage drop of the current sampling resistor, so as to obtain the output voltage of the current detection chip 50, an analog-to-digital conversion interface in the MCU30 converts an analog signal into a digital signal, and acquires the output voltage of the current detection chip 50, in the calibration process, the digital signal is converted into an analog signal through the digital-to-analog conversion interface of the MCU30, and since the static current and the gate voltage are in a positive correlation, the static current of the power amplifier 10 may be calibrated by adjusting the gate voltage.

Optionally, the analog-to-digital conversion interface may be 16 bits or 12 bits, where when the analog-to-digital conversion interface is 16 bits, the current detection resolution is 1.26 milliamperes (mA), the current detection resolutions corresponding to different bit widths are also different, and the greater the bit width is, the greater the current detection resolution is, so that the current detection is more accurate; similarly, the digital-to-analog conversion interface may be 16 bits or 12 bits, wherein when the digital-to-analog conversion interface is 12 bits, the gate voltage detection resolution is 0.8 mA.

Fig. 4 is a schematic flowchart of a calibration method of a power amplifier according to an embodiment of the present invention, as shown in fig. 4, the method includes:

and S101, turning off the radio frequency modulation signal of the power amplifier.

S102, regulating the grid voltage of the power amplifier to calibrate the quiescent current of the power amplifier.

Generally, a modulation transmitter firstly modulates an audio signal and a high-frequency carrier into a modulation wave to change the frequency of the high-frequency carrier with the audio signal, and amplifies, excites, amplifies and matches a series of impedances the generated high-frequency signal through a power amplifier to output the signal to an antenna. The static current of the power amplifier cannot meet the normal working requirement of the power amplifier due to the deviation of the manufacturing process, and the grid voltage can be adjusted by closing the radio frequency modulation signal, so that the static current of the power amplifier is calibrated.

Specifically, a positive correlation exists between the drain current and the gate voltage of the power amplifier, as shown in fig. 5, where the current consumed by the power amplifier is a static current when the radio frequency modulation signal is turned off, and the current consumed by the power amplifier is a dynamic current when the radio frequency modulation signal is turned on, optionally, the gate voltage may be controlled and adjusted through a digital-to-analog conversion interface of the MCU, so as to calibrate the static current of the power amplifier.

And S103, turning on the radio frequency modulation signal of the power amplifier.

And S104, calibrating the output power of the power amplifier by adjusting the input power of the power amplifier.

Specifically, after the static current of the power amplifier is calibrated, the radio frequency modulation signal of the power amplifier can be turned on, the power amplifier outputs a dynamic current, and the dynamic current is within a preset range by adjusting the input power of the power amplifier, so that the output power of the power amplifier is calibrated.

In the calibration method for the power amplifier provided in this embodiment, the radio frequency modulation signal of the power amplifier is turned off, the quiescent current of the power amplifier is calibrated by adjusting the gate voltage of the power amplifier, the radio frequency modulation signal of the power amplifier is turned on, and the output power of the power amplifier is calibrated by adjusting the input power of the power amplifier. According to the technical scheme, the influence of other current consumption devices in the calibration circuit on current detection can be eliminated, so that the calibration precision of the quiescent current can be improved, and the calibration of the quiescent current and the output power of the power amplifier can be simultaneously realized without additional test equipment, so that the calibration process is simpler and more convenient.

Fig. 6 is a schematic flowchart of a coarse calibration process for a quiescent current of a power amplifier according to an embodiment of the present invention, where as shown in fig. 6, the method includes:

circularly executing the first specified operation until the first quiescent current of the power amplifier is within a first preset range value; the first specifying operation includes:

s201, determining a first static current according to a first current grid voltage of a power amplifier; when the first appointed operation is executed for the first time, the first current grid voltage is the initial grid voltage, and when the first appointed operation is not executed for the first time, the first current grid voltage is the regulated first grid voltage obtained when the first appointed operation is executed for the previous time;

optionally, as an implementation manner for determining the first quiescent current, as shown in fig. 7, it may include:

s301, acquiring the output voltage of the current detection chip; the output voltage is positively correlated with the present gate voltage.

S302, determining a first quiescent current of the power amplifier according to a formula Ids ═ Vout/(Gain ═ Rsense); ids is a first static current of the power amplifier, Vout is an output voltage of the current detection chip, Gain is a Gain of the current detection chip, and Rsense is a resistance value of the current sampling detection resistor.

Specifically, in the process of calibrating the quiescent current, the output voltage of the current detection chip may be collected through an analog-to-digital conversion interface in the MCU, and after the output voltage of the current detection chip is obtained, the first quiescent current of the power amplifier may be determined according to a formula Ids ═ Vout/(Gain × Rsense), optionally, in this embodiment, the Gain of the current detection chip is 50, and the resistance Rsense of the current sampling detection resistor is 40m Ω. It should be noted that, since the output voltage of the current detection chip is directly proportional to the first quiescent current, and the first quiescent current of the power amplifier is positively correlated to the first present gate voltage, the output voltage of the current detection chip is positively correlated to the first present gate voltage.

S202, judging whether the first static current is in a first preset range value or not;

and S203, when the first static current is not in the first preset range value, adjusting the first current gate voltage to obtain an adjusted first gate voltage, and returning to continue to execute the step 201.

Specifically, when the first static current is not within the first preset range value, the adjusted first gate voltage may be obtained by increasing or decreasing the current gate voltage value, wherein when the first static current is greater than the maximum value of the first preset range value, the first current gate voltage is decreased by a first preset step length, and when the first static current is less than the minimum value of the first preset range value, the first current gate voltage is increased by the first preset step length.

And S204, when the first quiescent current is within the first preset range value, ending the process.

Specifically, when calibration is started, the radio frequency modulation signal is turned off, the first static current is determined according to the initial gate voltage of the power amplifier, whether the first static current is within a first preset range value or not is judged, if the first static current is not within the first preset range value, the adjusted first gate voltage is obtained by adjusting a first current gate voltage value, and if the first static current is within the first preset range value, coarse adjustment of the power amplifier is completed.

It should be noted that the calibration process in the embodiment of the present application may be divided into coarse tuning and fine tuning, where the adjustment range is large and the accuracy is small during the coarse tuning, and the adjustment range is small and the accuracy is high during the fine tuning. The first designated operation is a process of roughly adjusting the static current, and the first preset range is a preset range set when the static current is roughly adjusted.

Specifically, when the quiescent current of the power amplifier is within a first preset range, it indicates that the coarse adjustment of the quiescent current is completed, and if the quiescent current is to be more accurate, the fine adjustment of the quiescent current is required.

Fig. 8 is a schematic diagram of a process of performing fine-tuning calibration on a quiescent current according to an embodiment of the present application. The method comprises the following steps:

circularly executing a second specified operation until the quiescent current of the power amplifier is within a second preset range value; wherein: the second designated operation includes:

s401, determining a second static current according to a second current grid voltage of the power amplifier; when the second specified operation is executed for the first time, the second current gate voltage is the adjusted first gate voltage, and when the second specified operation is not executed for the first time, the second current gate voltage is the adjusted second gate voltage.

The process of determining the second quiescent current is the same as the implementation process of determining the first quiescent current, and is not described herein again.

S402, judging whether the second quiescent current is within a second preset range value;

the second preset range value is a preset range value set during the fine adjustment of the quiescent current, so that the maximum value of the second preset range value is required to be smaller than the maximum value of the first preset range value, and the minimum value of the second preset range value is required to be larger than the minimum value of the first preset range value.

S403, when the second static current is not in a second preset range value, adjusting the current grid voltage to obtain an adjusted second grid voltage, and returning to continue to execute the step 401;

specifically, when the second quiescent current is not within the second preset range value, the adjusted second gate voltage may be obtained by increasing or decreasing the second present gate voltage, when the second quiescent current is greater than the maximum value of the second preset range value, the second present gate voltage is decreased by the second preset step size, and when the second quiescent current is less than the minimum value of the second preset range value, the second present gate voltage is increased by the second preset step size.

The second preset step length should be smaller than the first preset step length.

And S404, when the second static current is within a second preset range value, ending the process.

For example, when the quiescent current of the power amplifier is specifically calibrated, the initial gate voltage may be set to 1.3V, the normal quiescent current of the power amplifier is 250mA, the convergence range of the quiescent current during coarse adjustment is 240 to 260mA, the step value during adjustment of the gate voltage is 0.05, the convergence range of the quiescent current during fine adjustment is 248 to 252mA, the step value during adjustment of the gate voltage is 0.01, that is, the first preset range value is 240 to 260mA, the first preset step size is 0.05, the second preset range value is 248 to 252mA, and the second preset step size is 0.01. By adjusting the gate voltage, the quiescent current is made to be smaller discretely, and the quiescent current approaches 250mA more.

For example, in the adjusting process, the radio frequency modulation signal is turned off, the gate voltage is input to the power amplifier by 1.3V, the output voltage of the current detection chip is collected through the analog-to-digital conversion interface, and the quiescent current is determined according to the formula Ids ═ Vout/(Gain × Rsense), wherein the current detection chip Gain ═ 50, the current sampling resistance value Rsense ═ 40m Ω, the quiescent current is compared with 260mA, if the current sampling resistance value Rsense is greater than 260mA, the adjusting gate voltage is controlled to be reduced by 0.05V, if the current sampling resistance value Rsense is less than 260mA, the quiescent current is compared with 240mA, if the quiescent current is greater than 240mA, the adjusting gate voltage does not need to be coarsely adjusted, and if the quiescent current is less than 240mA, the adjusting gate voltage is controlled to be increased by 0.05V. Similarly, the fine tuning process is consistent with the coarse tuning process, the step of the grid voltage is smaller than that of the coarse tuning process, so that the quiescent current is converged to 248-252 mA, and the calibration of the quiescent current of the power amplifier is realized.

The calibration method for the quiescent current of the power amplifier provided by the embodiment includes a coarse tuning process and a fine tuning process for the quiescent current, so that the calibrated quiescent current is more accurate.

Fig. 9 is a schematic flowchart of calibrating the output power of the power amplifier according to an embodiment of the present invention. As shown in fig. 9, the method includes:

circularly executing the third specified operation until the dynamic current of the power amplifier is within a third preset range value; the third specifying operation includes:

s501, determining dynamic current according to the current input power of the power amplifier; when the third designated operation is executed for the first time, the current input power is the initial input power, and when the third operation is not executed for the first time, the current input power is the adjusted input power obtained when the third designated operation is executed for the previous time.

And S502, judging whether the dynamic current is in a third preset range value.

S503, adjusting the current input power to obtain the adjusted input power, and returning to execute S501.

Specifically, after the static current calibration process of the power amplifier is completed, a radio frequency adjustment signal is input to the power amplifier to obtain a dynamic current, for example, 15dBm of power may be input to the power amplifier, the dynamic current is compared with a third preset range value, the dynamic current is converged within the third preset range value by adjusting the current input power, and when the dynamic current is not within the third preset range value, the current input power is adjusted to obtain an adjusted input power; when the dynamic current is within a third preset range value, the calibration of the output power of the power amplifier is completed. Alternatively, the output power may be brought within a third preset range of values by increasing or decreasing the input power in a third step.

Illustratively, if the normal output power range of the power amplifier is 1.8-1.85 w, according to the test experience value, the corresponding dynamic current range is 700-720 mA, the obtained dynamic current is firstly compared with 720mA, if the dynamic current is larger than 720mA, the input power value is reduced by 0.1dB, if the current value is smaller than 700mA, the input power is increased by 0.1dB, so that the dynamic current is converged at 700-720 mA, and the output power calibration of the power amplifier is completed.

The calibration method for the power amplifier provided by the embodiment can realize the calibration of the output power of the power amplifier without additional test equipment, and the implementation process is simple and convenient.

Fig. 10 is a schematic flow chart illustrating a status monitoring and protection of a power amplifier according to an embodiment of the present invention. As shown in fig. 10, the method includes:

s601, determining the regulated second grid voltage and the regulated input power;

s602, determining the current dynamic current of the power amplifier according to the second grid voltage and the regulated input power;

s603, judging whether the current dynamic current is within a fourth preset range value;

and S604, when the current dynamic current is not in the fourth preset range, adjusting the second grid voltage to zero, and turning off the radio frequency modulation signal.

Specifically, when the power amplifier works, the power amplifier may be monitored in real time, whether the power amplifier is in a normal state is determined, the adjusted second gate voltage and the adjusted input power are determined through the calibration of the quiescent current and the output power of the power amplifier, so as to obtain the current dynamic current of the power amplifier, and whether the current dynamic current is within a fourth preset range value is determined, where the fourth preset range is a threshold range in which the power amplifier is in a safe working state, and when the current dynamic current is greater than a maximum value in the fourth preset range or less than a minimum value in the fourth preset range value, the second gate voltage is adjusted to zero, and the radio frequency modulation signal is turned off, so that the power amplifier stops working.

It should be noted that, in the actual working process of the power amplifier, the power amplifier may be abnormal or damaged due to no connection with the antenna or lack of a load, and the present dynamic current may be sampled in real time and is determined whether to be within a fourth preset range value, so as to protect the power device in time.

According to the calibration method of the power amplifier provided by the embodiment, the current dynamic current is detected in real time, so that the power amplifier can be automatically closed under an abnormal condition, the safe use of the power amplifier is ensured, and the power amplifier can be protected in time.

It should be noted that while the operations of the method of the present invention are depicted in the drawings in a particular order, this does not require or imply that the operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Rather, the steps depicted in the flowcharts may change the order of execution. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.

Fig. 11 is a schematic structural diagram of a calibration apparatus for a power amplifier according to an embodiment of the present invention. As shown in fig. 11, the apparatus may implement the methods shown in fig. 4 to 10, and the apparatus may include:

a shutdown module 10 configured to shut down the radio frequency modulation signal of the power amplifier;

a current calibration module 20 configured to calibrate a quiescent current of the power amplifier by adjusting a gate voltage of the power amplifier;

a turn-on module 30 configured to turn on the radio frequency modulation signal of the power amplifier;

a power calibration module 40 configured to calibrate the output power of the power amplifier by adjusting the input power of the power amplifier.

Preferably, the current calibration module 20 may be specifically configured to:

circularly executing a first specified operation until the first quiescent current of the power amplifier is within a first preset range value; wherein,

the first specifying operation includes:

determining a first quiescent current according to a first present gate voltage of the power amplifier; when the first specified operation is executed for the first time, the first current gate voltage is an initial gate voltage, and when the first specified operation is not executed for the first time, the first current gate voltage is an adjusted first gate voltage obtained when the first specified operation is executed for the previous time;

judging whether the first quiescent current is within a first preset range value;

when the first static current is not in the first preset range value, adjusting the first current grid voltage to obtain an adjusted first grid voltage, and controlling to enter the next first appointed operation;

and when the first quiescent current is within a first preset range value, controlling not to enter the first appointed operation next time.

Preferably, the current calibration module 20 is configured to, when determining the first quiescent current according to a first present gate voltage of the power amplifier, specifically:

acquiring the output voltage of the current detection chip; the output voltage and the first present gate voltage are positively correlated; determining a first quiescent current of the power amplifier according to a formula Ids ═ Vout/(Gain ═ Rsense); and Ids is a first static current of the power amplifier, Vout is an output voltage of the current detection chip, Gain is a Gain of the current detection chip, and Rsense is a resistance value of the current sampling detection resistor.

Preferably, the current calibration module 20 is configured to, when the first static current is not within the first preset range, adjust the current gate voltage value to obtain an adjusted first gate voltage, specifically:

when the first quiescent current is greater than the maximum value of the first preset range value, reducing the first current gate voltage by a first preset step length; and when the first static current is smaller than the minimum value of the first preset range value, increasing the first current gate voltage by the first preset step length.

Optionally, the apparatus may further include:

a current recalibration module 50 for: circularly executing a second specified operation until a second quiescent current of the power amplifier is within a second preset range value; wherein:

the second designated operation includes:

determining a second quiescent current according to a second present gate voltage of the power amplifier; when the second specified operation is executed for the first time, the second current gate voltage is the adjusted first gate voltage, and when the second specified operation is not executed for the first time, the second current gate voltage is the adjusted second gate voltage;

judging whether the second quiescent current is within the second preset range value; the maximum value in the second preset range value is smaller than the maximum value in the first preset range value; the minimum value in the second preset range value is larger than the minimum value in the first preset range value;

when the second static current is not within the second preset range value, adjusting the second current grid voltage to obtain an adjusted second grid voltage, and controlling to enter the next second specified operation;

and when the second quiescent current is within the second preset range value, controlling not to enter the second specified operation next time.

Preferably, the current recalibration module 50 is configured to, when the second static current is not within the second preset range, adjust the second current gate voltage to obtain an adjusted second gate voltage, specifically:

when the second quiescent current is greater than the maximum value of the second preset range value, reducing the second current gate voltage by the second preset step length; the second preset step length is smaller than the first preset step length; and when the second quiescent current is smaller than the minimum value of the second preset range value, increasing the second current gate voltage by the second preset step length.

Optionally, the power calibration module 40 may be configured to:

circularly executing a third specified operation until the dynamic current of the power amplifier is within a third preset range value; wherein,

the third specifying operation includes:

determining a dynamic current according to the current input power of the power amplifier; when the third designated operation is executed for the first time, the current input power is the initial input power, and when the third operation is not executed for the first time, the current input power is the adjusted input power obtained when the third designated operation is executed for the previous time.

Judging whether the dynamic current is within a third preset range value or not;

when the dynamic current is not in a third preset range value, adjusting the input power to obtain the adjusted input power, and controlling to enter a next third appointed operation;

and when the dynamic current is within a third preset threshold range, controlling not to enter the third appointed operation next time.

Preferably, the power calibration module 40 is configured to, when the dynamic current is not within a third preset range, adjust the current input power to obtain an adjusted input power, specifically:

when the dynamic current is larger than the maximum value of the third preset range value, reducing the current input power by the third preset step length; and when the dynamic current is smaller than the minimum value of the third preset range value, increasing the current input power by the third preset step length.

Optionally, the apparatus may further include: a monitoring module 60, the monitoring module 60 comprising:

a first determining unit 601, configured to determine an adjusted second gate voltage and the adjusted input power;

a second determining unit 602, configured to determine a current dynamic current of the power amplifier according to the second gate voltage and the adjusted input power;

a judging unit 603, configured to judge whether the current dynamic current is within a fourth preset range value;

an adjusting unit 604, configured to adjust the second gate voltage to zero and turn off the rf modulation signal when the current dynamic current is not within the fourth preset range.

The calibration apparatus for a power amplifier provided in this embodiment may implement the embodiments of the method described above, and the implementation principle and the technical effect are similar, which are not described herein again.

Fig. 12 is a schematic structural diagram of a computer device according to an embodiment of the present invention. As shown in fig. 12, a schematic structural diagram of a computer system 500 suitable for implementing the terminal device or the server of the embodiment of the present application is shown.

As shown in fig. 12, the computer system 500 includes a Central Processing Unit (CPU)501 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM)502 or a program loaded from a storage section 508 into a Random Access Memory (RAM) 503. In the RAM503, various programs and data necessary for the operation of the system 500 are also stored. The CPU501, ROM502, and RAM603 are connected to each other via a bus 504. An input/output (I/O) interface 506 is also connected to bus 504.

The following components are connected to the I/O interface 505: an input portion 506 including a keyboard, a mouse, and the like; an output portion 507 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker; a storage portion 508 including a hard disk and the like; and a communication section 509 including a network interface card such as a LAN card, a modem, or the like. The communication section 509 performs communication processing via a network such as the internet. A driver 510 is also connected to the I/O interface 506 as needed. A removable medium 511 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 510 as necessary, so that a computer program read out therefrom is mounted into the storage section 508 as necessary.

In particular, the processes described above with reference to fig. 4-10 may be implemented as computer software programs, according to embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program tangibly embodied on a machine-readable medium, the computer program comprising program code for performing the methods of fig. 4-10. In such an embodiment, the computer program may be downloaded and installed from a network through the communication section 509, and/or installed from the removable medium 511.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units or modules described in the embodiments of the present application may be implemented by software or hardware. The described units or modules may also be provided in a processor, and may be described as: a processor includes a shutdown module, a current calibration module, a startup module, and a power calibration module. Where the names of these units or modules do not in some cases constitute a limitation of the unit or module itself, for example, the current calibration module may also be described as "for calibrating the quiescent current of the power amplifier by adjusting the gate voltage of the power amplifier".

As another aspect, the present application also provides a computer-readable storage medium, which may be the computer-readable storage medium included in the foregoing device in the foregoing embodiment; or it may be a separate computer readable storage medium not incorporated into the device. The computer readable storage medium stores one or more programs for use by one or more processors in performing the calibration method for a power amplifier described herein.

In summary, the calibration circuit, method, device, apparatus, and readable storage medium of a power amplifier provided in the embodiments of the present invention turn off a radio frequency modulation signal of the power amplifier, calibrate a quiescent current of the power amplifier by adjusting a gate voltage of the power amplifier, turn on the radio frequency modulation signal of the power amplifier, and calibrate an output power of the power amplifier by adjusting an input power of the power amplifier. According to the technical scheme, the influence of other current consumption devices in the calibration circuit on current detection can be eliminated, so that the calibration precision of the quiescent current can be improved, and the calibration of the quiescent current and the output power of the power amplifier can be simultaneously realized without additional test equipment, so that the calibration process is simpler and more convenient.

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.