CN109962696A - A kind of pierce circuit that duty ratio is controllable - Google Patents

The present invention provides a kind of pierce circuits that duty ratio is controllable, the pierce circuit includes oscillating loop circuit, level sensitive circuit, turn threshold detection circuit and application condition circuit, wherein, oscillating loop circuit is by odd level phase inverter, charging current source and discharge current source composition, level sensitive circuit and turn threshold detection circuit connect application condition circuit simultaneously, the oscillator signal that oscillating loop circuit generates is input to level sensitive circuit, level sensitive circuit outputs level signals, turn threshold detection circuit output voltage signal, voltage signal is input in application condition circuit together with level signal, the output end of application condition circuit is connected to oscillating loop circuit, adjust the size of charging current in oscillating loop circuit.The clock signal duty cycle value that the present invention realizes pierce circuit final output is maintained at 50%, and the dutyfactor value does not change with the waveform of technique.

A kind of pierce circuit that duty ratio is controllable

Technical field

The present invention relates to Analogous Integrated Electronic Circuits technical field more particularly to a kind of pierce circuit, specially a kind of duty Than controllable pierce circuit.

Background technique

Oscillator is a kind of common circuit in Analogous Integrated Electronic Circuits, and effect is generation system clock, one of weight The index wanted is exactly duty ratio (Duty Cycle, abbreviation DC).Duty ratio definition is in a clock cycle, when high level Between account for the ratio of clock period time, the duty ratio of ideal square wave is 50%.In fact, in actual pierce circuit, to reality Now the duty ratio near accurate 50% is highly difficult.

As shown in Figure 1, being a kind of existing ring oscillator structure schematic diagram.In the ring oscillator structure, three The output terminals A of phase inverter 101,102,103, B, C input join end to end, and form the oscillating condition that annular reaches oscillator, are formed Rectilinear oscillation signal, wherein the signal of output end C point exports clock signal clk by phase inverter 104.Reference current 114 passes through Leakage, grid be shorted NMOS transistor 113 generate biasing voltage signal VBN, biased electrical pressure side VBN be connected to NMOS transistor 109, 110,111,112 grid；The drain and gate that the drain electrode of NMOS transistor 109 is connected to PMOS transistor 105 generates biasing Voltage VBP, biased electrical pressure side VBP are connected to the grid of PMOS transistor 106,107,108.In this way, the reverse phase in oscillating loop The charging current of device 101,102,103 is provided by PMOS transistor current source 106,107,108 respectively, and discharge current is distinguished It is provided by NMOS transistor current source 110,111,112.

The period that the oscillator exports clock signal clk is linearly related with reference current source 114, but its duty ratio DC, It is then directly related with the centered level of the turn threshold Vto of output stage phase inverter 104 and oscillating loop A, B, C point.In circuit When design, meet following two o'clock, that is, duty ratio may make to be equal at 50%: the first point, designs the overturning threshold of output stage phase inverter 104 Value Vto is equal to the central value VDD/2 of supply voltage VDD, at this time, it is desirable that NMOS transistor and PMOS crystal in phase inverter 104 Pipe ducting capacity is equal, i.e. μ n* (VDD-Vtn) * (W/L) n=μ p* (VDD-Vtp) * (W/L) p；Second point designs oscillating loop In phase inverter 101,102,103 in charging current it is equal with discharge current, i.e. (W/L) 109=(W/L) 110=(W/L) 111= (W/L) 112, (W/L) 105=(W/L) 106=(W/L) 107=(W/L) 108, to realize in oscillating loop, oscillator signal A, B, C The centered level VS of point is VDD/2.But in actual process production, since NMOS transistor and PMOS transistor are by technique wave It is dynamic to influence different, the centered level of oscillator signal A, B, C point in the turn threshold Vto and oscillating loop of output stage phase inverter 104 VS can not maintain always VDD/2, such as: in SF(NMOS Slow, the PMOS Fast of technique) when, output stage reverse phase The turn threshold of device 104 becomes > VDD/2, in this way, the clock signal clk duty ratio of final output is bigger than 50%；Equally, in work FS(NMOS Fast, the PMOS Slow of skill) when, the turn threshold of output stage phase inverter 104 becomes < VDD/2, in this way, finally The clock signal clk duty ratio of output is smaller than 50%.

Summary of the invention

In view of the above-mentioned deficiencies in the prior art, the invention proposes a kind of pierce circuit that duty ratio is controllable, Wherein, level sensitive circuit and turn threshold detection circuit connect application condition circuit simultaneously, and it is final to realize pierce circuit The clock signal duty cycle of output is maintained at 50%, and the dutyfactor value does not change with the waveform of technique.

In order to reach above-mentioned technical purpose, the technical scheme adopted by the invention is that:

A kind of pierce circuit that duty ratio is controllable, the pierce circuit include oscillating loop circuit, level sensitive circuit, turn over Turn threshold detection circuit and application condition circuit, wherein oscillating loop circuit is by odd level phase inverter, charging current source and electric discharge Current source composition, level sensitive circuit and turn threshold detection circuit connect application condition circuit simultaneously, and oscillating loop circuit produces Raw oscillator signal is input to level sensitive circuit, level sensitive circuit outputs level signals, the output of turn threshold detection circuit Voltage signal, voltage signal are input in application condition circuit together with level signal, the output end connection of application condition circuit To oscillating loop circuit, the size of charging current in oscillating loop circuit is adjusted.

Preferably, in the pierce circuit, turn threshold detection circuit be by with the complete phase of output stage phase inverter size Same PMOS transistor and NMOS transistor is constituted, and the source electrode of PMOS transistor connects power supply, the source electrode connection of NMOS transistor The grid of ground wire, PMOS transistor and NMOS transistor is together with drain series.

Preferably, in the pierce circuit, level sensitive circuit is low-pass filter.

Preferably, in the pierce circuit, the turn threshold of turn threshold detection circuit is set as fixed value.

Preferably, in the pierce circuit, the charging current source in oscillating loop circuit is by PMOS transistor current source It provides.

Preferably, in the pierce circuit, the grid connection application condition electricity of PMOS transistor in oscillating loop circuit Road output end.

The present invention connects simultaneously since pierce circuit uses above-mentioned level sensitive circuit and turn threshold detection circuit The structure of application condition circuit, beneficial effect obtained are the clock signal duties for realizing pierce circuit final output Ratio is maintained at 50%, and the dutyfactor value does not change with the waveform of technique.

The present invention will be further described with reference to the accompanying drawings and detailed description.

Detailed description of the invention

Fig. 1 is existing oscillator circuit structure schematic diagram.

Fig. 2 is the oscillator circuit structure schematic diagram of one of present invention specific implementation.

Fig. 3 is two oscillator circuit structure schematic diagram of specific implementation of the invention.

Specific embodiment

Referring to Fig. 2, for the oscillator circuit structure schematic diagram of one of present invention specific implementation.In the controllable vibration of the duty ratio It swings in device circuit structure, the output terminals A of three odd level phase inverters 201,202,203, B, C input join end to end, and form annular Reach the oscillating condition of oscillator, and form rectilinear oscillation signal, the signal of the output end C of odd level phase inverter 203 is by defeated Grade phase inverter 204 exports clock signal clk out.Reference current 214 generates biasing by the drain and gate of NMOS transistor 213 Voltage VBN, biased electrical pressure side VBN are connected to the grid of NMOS transistor 210,211,212；VREF and VS is input to error amplification 205 output voltage VBP of device circuit is signally attached to the grid of PMOS transistor 206,207,208.In this way, in oscillating loop circuit The charging current of odd level phase inverter 201,202,203 is provided by PMOS transistor current source 206,207,208 respectively, and Discharge current is provided by NMOS tube current source 210,211,212 respectively.

Oscillator signal A, B, C of oscillating loop circuit are input in level sensitive circuit 209, and level sensitive circuit 209 is defeated Level signal VS out.215 output voltage signal VREF of turn threshold detection circuit.Voltage signal VREF is together with level signal VS It is input in error amplifier circuit 205, error amplifier circuit 205 output signal VBP, output end VBP are connected to oscillation The grid of PMOS transistor 206,207,208 in loop circuit.

As shown in figure 3, for two oscillator circuit structure schematic diagram of specific implementation of the invention.The oscillator circuit structure In, 301 be level sensitive circuit, and 302 be application condition circuit, and 303 be turn threshold detection circuit.Level sensitive circuit 301 It is brilliant by the PMOS transistor 303a and NMOS that are connect with the above-mentioned 204 identical diode of size of Fig. 2 output stage phase inverter Body pipe 303b, connects between power vd D and ground wire, i.e., PMOS transistor source electrode connects power vd D, the source electrode ground connection of NMOS transistor The grid of line, PMOS transistor and NMOS transistor and drain electrode all link together, in this way the center voltage VREF of the two, this Voltage VREF value is equal to the turn threshold Vto of output stage phase inverter.

In Fig. 3,301 be level sensitive circuit, is by connecting oscillation rings by three one end resistance 301a, 301b, 301c Oscillator signal A, B, C in road, other end is shorted to be grounded with after capacitor 301d series connection together, to constitute one Low-pass filter circuit, the top crown of capacitor 301d are the level VS for being approximately D. C. value, this level VS value and oscillating loop The central value of middle oscillator signal is equal.

In Fig. 3,302 be application condition circuit AMP.Level signal VS and voltage signal VREF are input to error amplifier Positive-negative input end NMOS transistor 302b, 302c grid；PMOS transistor 302d, 302e forms current mirror, and grid connects It is connected to together and is connect with the drain electrode of 302d, 302b；The drain electrode of 302e and the drain electrode of 302c are commonly connected to application condition circuit 302 output end VBP export bias voltage VBP；Tail current source of the NMOS transistor 302a as amplifier, grid and partially Voltage end VBN connection is set, drain electrode is connected together with the source electrode of 302b, 302c, and source electrode is connected with ground wire.

206,207,208 grid voltage of PMOS transistor in the output end VBP control oscillating loop of error amplifier, from And adjust charging current.When level VS value is greater than voltage VREF value, bias voltage VBP value increases, and charging current reduces, To which oscillator signal centered level reduces in oscillating loop, i.e., level VS value reduces；When level VS value is less than voltage VREF value, Bias voltage VBP value reduces, and charging current increases, thus the increase of oscillator signal centered level, i.e. level VS value in oscillating loop It improves.In this way, realize level VS clock dynamic follows the value of voltage VREF, and is equal to it by this structure. To realize that final output clock signal clk duty ratio DC clock is maintained at 50%, which does not become with the waveform of technique Change.

The present invention is not limited to embodiment discussed above, the above description to specific embodiment is intended to retouch State and illustrate technical solution of the present invention.The obvious transformation or substitution enlightened based on the present invention should also be as being considered Fall into protection scope of the present invention；Above specific embodiment is used to disclose best implementation method of the invention, so that this The those of ordinary skill in field can reach of the invention using numerous embodiments of the invention and a variety of alternatives Purpose.