CN110045774A - A kind of digital LDO circuit of fast transient response - Google Patents
- ️Tue Jul 23 2019
CN110045774A - A kind of digital LDO circuit of fast transient response - Google Patents
A kind of digital LDO circuit of fast transient response Download PDFInfo
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- CN110045774A CN110045774A CN201910264898.6A CN201910264898A CN110045774A CN 110045774 A CN110045774 A CN 110045774A CN 201910264898 A CN201910264898 A CN 201910264898A CN 110045774 A CN110045774 A CN 110045774A Authority
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Abstract
本发明公开了一种快速瞬态响应的数字LDO电路，包括钟控比较器阵列、控制器、功率开关阵列、采样电阻网络和片内电容，控制器用于控制功率开关阵列中导通的功率开关数目，进而调整输出电压的大小，当负载跳变导致输出电压大幅波动时，控制器开启二分法调整将输出电压快速恢复至趋于电路的额定输出电压的稳定状态。本发明数字LDO电路在面对不同负载变化造成的输出电压跳变时，均具有较快的瞬态响应速度，且在瞬态响应中，经过近乎固定的快速的调整周期，使得输出电压恢复到额定值。相对于其他LDO电路，本发明数字LDO电路采用纯数字单元的电路结构，能够工作于亚1V的低电源电压环境中，具有静态功耗低、集成度高、瞬态响应快的优点。
The invention discloses a digital LDO circuit with fast transient response, which includes a clock-controlled comparator array, a controller, a power switch array, a sampling resistor network and an on-chip capacitor. When the load jump causes the output voltage to fluctuate greatly, the controller turns on the dichotomy adjustment to quickly restore the output voltage to a stable state that is close to the rated output voltage of the circuit. The digital LDO circuit of the present invention has a fast transient response speed when facing the output voltage jump caused by different load changes, and in the transient response, the output voltage is restored to rated value. Compared with other LDO circuits, the digital LDO circuit of the present invention adopts a circuit structure of pure digital units, can work in a low power supply voltage environment of sub-1V, and has the advantages of low static power consumption, high integration and fast transient response.
Description
技术领域technical field
本发明涉及集成电路电源管理以及模拟和数模混合信号电路与系统(Analog andmixed-signal circuit and system,AMSCS)技术领域，具体是一种快速瞬态响应的数字LDO电路。The invention relates to the technical field of integrated circuit power management and analog and digital-analog mixed-signal circuit and system (AMSCS), in particular to a digital LDO circuit with fast transient response.
背景技术Background technique
近年来，手机、电子手环、平板电脑等一些电子设备做得越发轻薄，同时内部的片上系统(SoC)集成度越来越高，这就意味着这些设备运行所需的能耗大幅增加而电池容量没有随之提升。为了提高这些设备的续航能力以及提供一个良好的工作电压，就需要在电源和这些模块之间引入电源管理芯片，担负起对电能的变换、分配、检测以及稳压、降噪的职能，同时这些电源管理芯片需要满足自身的低功耗要求，使得设备能够更长时间的运行。In recent years, some electronic devices such as mobile phones, electronic bracelets, and tablet computers have become thinner and lighter, and the internal system-on-chip (SoC) integration has become higher and higher, which means that the energy consumption required for these devices to operate has increased significantly. The battery capacity has not increased accordingly. In order to improve the battery life of these devices and provide a good working voltage, it is necessary to introduce a power management chip between the power supply and these modules to undertake the functions of power conversion, distribution, detection, voltage regulation and noise reduction. The power management chip needs to meet its own low power consumption requirements, so that the device can run for a longer time.
低压差线性稳压器(Low Dropout Regulator,LDO)由于其电路简单、噪声与功耗低等优点，在电源管理芯片中获得广泛的应用。传统的模拟LDO(ALDO)在片外需要一个μF量级的去耦电容，以获得良好的纹波抗扰度及优异的瞬态响应特性。而系统级封装技术发展对LDO的功耗及尺寸提出了很高的要求，为了减小芯片面积并且保持较好的稳定性，无片外电容的ALDO需要额外的复杂的补偿网络。同时随着CMOS工艺尺寸的不断缩减以及低功耗的要求不断提高，超大规模集成电路(Very Large Scale Integration Circuit,VLSI)甚至被要求工作在低电压(0.5V)状态下，而这个接近MOS管阈值电压水平的工作电压将导致ALDO难以设计。Low dropout linear regulator (Low Dropout Regulator, LDO) is widely used in power management chips due to its advantages of simple circuit, low noise and power consumption. Traditional analog LDOs (ALDOs) require an off-chip decoupling capacitor of the order of μF to obtain good ripple immunity and excellent transient response characteristics. The development of system-in-package technology has put forward high requirements on the power consumption and size of LDOs. In order to reduce the chip area and maintain better stability, ALDOs without off-chip capacitors require additional complex compensation networks. At the same time, with the continuous reduction of CMOS process size and the continuous improvement of low power consumption requirements, Very Large Scale Integration Circuit (VLSI) is even required to work in a low voltage (0.5V) state, which is close to MOS transistors. The operating voltage at the threshold voltage level will make the ALDO difficult to design.
为了解决低电压环境无法工作的问题，数字LDO(DLDO)被提出。图1展示了ALDO的简化结构示意图，主要包含误差放大器和功率管。图2展示了DLDO的结构示意图，与ALDO相比，DLDO用钟控比较器取代了ALDO中的误差放大器、用一组功率开关阵列取代了ALDO中单一的大功率管，并使用以一组双向移位寄存器为基础的控制器来改变功率开关阵列的导通数目使得输出电压保持稳定。全数字结构使得DLDO获得了更低的工作电压、更高的工艺可扩展性和更低的静态功耗。尽管如此，DLDO存在较差的瞬态响应，即当LDO的负载突然发生变化时，其输出电压将会产生跳变(跳变幅度随负载变化大小而变化)。ALDO能够通过误差放大器和功率管很快调整输出电压至额定水平，而DLDO只能通过采样时钟的采样结果来调整功率开关数目，其恢复速度受限于时钟频率和功率开关的单位时钟变化数目。由于最早的DLDO每个时钟周期只能调谐一个功率开关，导致其瞬态响应速度非常慢。提高采样时钟的频率，能够增加瞬态响应速度，但是会相应的增加LDO的动态功耗。而增大功率开关宽长比同样可以增加瞬态响应的速度，但会影响LDO最后稳定电压的精度。采用粗调加细调相结合的控制方式，通过前期单位时钟改变N倍的功率开关数目实现快速调整，后期单位时钟改变1倍的功率开关数目实现精度控制，是一种常见的DLDO控制方案。但这种方案具有一定的局限性，在应对不同负载变化时，存在瞬态响应速度优化不佳的可能。In order to solve the problem that the low voltage environment cannot work, a digital LDO (DLDO) is proposed. Figure 1 shows a simplified schematic diagram of an ALDO, which mainly includes an error amplifier and a power tube. Figure 2 shows the schematic diagram of the structure of DLDO. Compared with ALDO, DLDO replaces the error amplifier in ALDO with a clocked comparator, replaces a single high-power tube in ALDO with a set of power switch arrays, and uses a set of bidirectional A shift register-based controller is used to change the conduction number of the power switch array to keep the output voltage stable. The all-digital structure enables DLDO to obtain lower operating voltage, higher process scalability and lower static power consumption. However, DLDO has poor transient response, that is, when the LDO's load changes suddenly, its output voltage will jump (the jump amplitude varies with the magnitude of the load change). ALDO can quickly adjust the output voltage to the rated level through the error amplifier and power tube, while DLDO can only adjust the number of power switches through the sampling result of the sampling clock, and its recovery speed is limited by the clock frequency and the number of unit clock changes of the power switch. Since the earliest DLDOs can only tune one power switch per clock cycle, their transient response is very slow. Increasing the frequency of the sampling clock can increase the transient response speed, but will correspondingly increase the dynamic power consumption of the LDO. And increasing the power switch width to length ratio can also increase the speed of the transient response, but it will affect the accuracy of the LDO's final stable voltage. A control method combining coarse adjustment and fine adjustment is used to achieve rapid adjustment by changing the number of power switches by N times per unit clock in the early stage, and achieve precision control by changing the number of power switches by one time per unit clock in the later stage. It is a common DLDO control scheme. However, this scheme has certain limitations. When dealing with different load changes, there is a possibility of poor optimization of the transient response speed.
发明内容SUMMARY OF THE INVENTION
本发明提供一种新的更具有复用性的快速瞬态响应的DLDO电路，该数字LDO电路采用二分法调整作为控制器的核心控制方案，在瞬态响应中，经过近乎固定的快速的调整周期，使得输出电压恢复到额定值；该数字LDO电路采用纯数字单元的电路结构，能够工作于亚1V的低电源电压环境中，具有静态功耗低、集成度高、瞬态响应快的优点。The invention provides a new and more reusable DLDO circuit with fast transient response. The digital LDO circuit adopts dichotomy adjustment as the core control scheme of the controller. In the transient response, after almost fixed fast adjustment cycle, so that the output voltage returns to the rated value; the digital LDO circuit adopts the circuit structure of pure digital unit, can work in the low power supply voltage environment of sub-1V, and has the advantages of low static power consumption, high integration and fast transient response. .
本发明所采用的技术方案为：一种快速瞬态响应的数字LDO电路，包括钟控比较器阵列、控制器、功率开关阵列、采样电阻网络和片内电容，所述的钟控比较器阵列的正输入端与所述的采样电阻网络的输出端连接，所述的钟控比较器阵列的负输入端与外部参考电压连接，所述的钟控比较器阵列的信号输出端与所述的控制器的信号输入端连接，所述的钟控比较器阵列的时钟使能端和所述的控制器的时钟输入端分别与外部采样时钟连接，所述的控制器的信号输出端与所述的功率开关阵列的输入端连接，所述的功率开关阵列的输出端分别与所述的采样电阻网络的输入电极和所述的片内电容的输入电极及输出电压连接，所述的采样电阻网络的输出电极和所述的片内电容的输出电极连接并接地，所述的输出电压与负载相连，所述的负载接地，所述的控制器用于控制所述的功率开关阵列中导通的功率开关数目，进而调整所述的输出电压的大小，当负载跳变导致输出电压大幅波动时，所述的控制器开启二分法调整将输出电压快速恢复至趋于电路的额定输出电压的稳定状态。The technical scheme adopted by the present invention is: a digital LDO circuit with fast transient response, including a clock-controlled comparator array, a controller, a power switch array, a sampling resistor network and an on-chip capacitor, and the clock-controlled comparator array The positive input terminal is connected to the output terminal of the sampling resistor network, the negative input terminal of the clocked comparator array is connected to the external reference voltage, and the signal output terminal of the clocked comparator array is connected to the The signal input end of the controller is connected, the clock enable end of the clock control comparator array and the clock input end of the controller are respectively connected with an external sampling clock, and the signal output end of the controller is connected to the The input terminal of the power switch array is connected to the input terminal of the power switch array, and the output terminal of the power switch array is respectively connected to the input electrode of the sampling resistor network and the input electrode and output voltage of the on-chip capacitor. The output electrode of the on-chip capacitor is connected and grounded, the output voltage is connected to the load, the load is grounded, and the controller is used to control the power that is conducted in the power switch array The number of switches is used to adjust the magnitude of the output voltage. When the load jump causes the output voltage to fluctuate greatly, the controller turns on the dichotomy adjustment to quickly restore the output voltage to a stable state close to the rated output voltage of the circuit.
作为优选，所述的功率开关阵列为一组数量以二进制分布的并联的PMOS晶体管阵列，所述的控制器的信号输出端与所述的PMOS晶体管阵列的各个栅端连接，所述的PMOS晶体管阵列的各个源端与外部输入电压连接，所述的PMOS晶体管阵列的各个漏端分别与所述的采样电阻网络的输入电极和所述的片内电容的输入电极及输出电压连接。Preferably, the power switch array is a group of parallel PMOS transistor arrays distributed in binary numbers, the signal output terminal of the controller is connected to each gate terminal of the PMOS transistor array, and the PMOS transistors Each source terminal of the array is connected to an external input voltage, and each drain terminal of the PMOS transistor array is respectively connected to the input electrode of the sampling resistor network and the input electrode and output voltage of the on-chip capacitor.
作为优选，所述的PMOS晶体管阵列包括n列PMOS晶体管组，根据二进制分布，第j列的PMOS晶体管组由2j-1个相同的PMOS晶体管并联构成，其中1≤j≤n，j∈Z；各列PMOS晶体管组的宽长比W/L从小到大依次为：δ、2δ、22·δ、23·δ、…、2n-1·δ，其中δ为单个PMOS晶体管的宽长比；所述的控制器输出一组n-bit的二进制信号控制所述的功率开关阵列中导通的功率开关数目。PMOS晶体管阵列包含2n-1个宽长比为δ的相同的PMOS晶体管，这些PMOS晶体管的数量近似为2n。将PMOS晶体管导通视为二进制的“1”，关断视为“0”，则功率开关阵列的开关状态以及功率开关阵列中导通的功率开关数目可以用一组n-bit的二进制数组表示，因此控制器产生一组n-bit的二进制信号控制功率开关阵列中导通的功率开关数目。随着数字LDO电路的输出电压的改变，n-bit的二进制信号也会由控制器改变，实现数字LDO电路输出电压的动态调节，使得输出电压在瞬态响应中快速恢复并保持在额定输出电压上下。其中，n决定了数字LDO电路的瞬态响应速度快慢，δ决定了数字LDO电路的输出电压的精度，n和δ共同决定了数字LDO电路的负载范围。Preferably, the PMOS transistor array includes n columns of PMOS transistor groups. According to the binary distribution, the PMOS transistor group in the jth column is composed of 2 j-1 identical PMOS transistors in parallel, where 1≤j≤n, j∈Z ; The width-to-length ratio W/L of each column of PMOS transistor groups from small to large is: δ, 2δ, 2 2 ·δ, 2 3 ·δ, ..., 2 n-1 ·δ, where δ is the width of a single PMOS transistor length ratio; the controller outputs a set of n-bit binary signals to control the number of power switches that are turned on in the power switch array. The PMOS transistor array contains 2n -1 identical PMOS transistors with an aspect ratio of [delta], the number of these PMOS transistors being approximately 2n . Considering that the PMOS transistor is turned on as a binary "1" and turned off as a "0", the switching state of the power switch array and the number of power switches that are turned on in the power switch array can be represented by a set of n-bit binary arrays , so the controller generates a set of n-bit binary signals to control the number of power switches that are turned on in the power switch array. With the change of the output voltage of the digital LDO circuit, the n-bit binary signal will also be changed by the controller to realize the dynamic adjustment of the output voltage of the digital LDO circuit, so that the output voltage quickly recovers in the transient response and remains at the rated output voltage up and down. Among them, n determines the transient response speed of the digital LDO circuit, δ determines the output voltage accuracy of the digital LDO circuit, and n and δ together determine the load range of the digital LDO circuit.
作为优选，所述的采样电阻网络包括串联的第一采样电阻、第二采样电阻、第三采样电阻和第四采样电阻，所述的第一采样电阻的一端分别与所述的PMOS晶体管阵列的各个漏端和所述的片内电容的输入电极连接，所述的第一采样电阻的另一端与所述的第二采样电阻的一端连接，所述的第二采样电阻的另一端与所述的第三采样电阻的一端连接，所述的第三采样电阻的另一端与所述的第四采样电阻的一端连接，所述的第四采样电阻的另一端与所述的片内电容的输出电极连接并接地。Preferably, the sampling resistor network includes a first sampling resistor, a second sampling resistor, a third sampling resistor and a fourth sampling resistor connected in series, and one end of the first sampling resistor is respectively connected to the other end of the PMOS transistor array. Each drain terminal is connected to the input electrode of the on-chip capacitor, the other end of the first sampling resistor is connected to one end of the second sampling resistor, and the other end of the second sampling resistor is connected to the One end of the third sampling resistor is connected to one end of the third sampling resistor, the other end of the third sampling resistor is connected to one end of the fourth sampling resistor, and the other end of the fourth sampling resistor is connected to the output of the on-chip capacitor. The electrodes are connected and grounded.
作为优选，所述的钟控比较器阵列包括第一钟控比较器、第二钟控比较器和第三钟控比较器，所述的第一钟控比较器的正输入端与所述的第一采样电阻的另一端连接，所述的第一钟控比较器的负输入端与所述的外部参考电压连接，所述的第二钟控比较器的正输入端与所述的第二采样电阻的另一端连接，所述的第二钟控比较器的负输入端与所述的外部参考电压连接，所述的第三钟控比较器的正输入端与所述的第三采样电阻的另一端连接，所述的第三钟控比较器的负输入端与所述的外部参考电压连接，所述的第一钟控比较器、第二钟控比较器和第三钟控比较器的时钟使能端分别与所述的外部采样时钟连接，所述的第一钟控比较器、第二钟控比较器和第三钟控比较器的信号输出端分别与所述的控制器的信号输入端连接。当采样时钟上升沿到来时，第一钟控比较器、第二钟控比较器和第三钟控比较器分别比较其正负两输入端的电压值，根据比较结果分别输出高电平“1”或低电平“0”，即若各个钟控比较器的正输入端的电压值大于负输入端的电压值，则各个钟控比较器分别输出高电平“1”；若各个钟控比较器的正输入端的电压值小于负输入端的电压值，则各个钟控比较器分别输出低电平“0”。Preferably, the clocked comparator array includes a first clocked comparator, a second clocked comparator and a third clocked comparator, and the positive input end of the first clocked comparator is connected to the The other end of the first sampling resistor is connected, the negative input end of the first clocked comparator is connected to the external reference voltage, and the positive input end of the second clocked comparator is connected to the second The other end of the sampling resistor is connected, the negative input end of the second clocked comparator is connected to the external reference voltage, and the positive input end of the third clocked comparator is connected to the third sampling resistor The other end of the clock control comparator is connected to the negative input terminal of the third clock control comparator, and the negative input terminal of the third clock control comparator is connected to the external reference voltage. The first clock control comparator, the second clock control comparator and the third clock control comparator The clock enable terminals of the clock are respectively connected with the external sampling clock, and the signal output terminals of the first clocked comparator, the second clocked comparator and the third clocked comparator are respectively connected with the controller's signal output terminals. Signal input connection. When the rising edge of the sampling clock arrives, the first clocked comparator, the second clocked comparator and the third clocked comparator compare the voltage values of the positive and negative input terminals respectively, and output a high level "1" according to the comparison results. Or low level "0", that is, if the voltage value of the positive input terminal of each clock-controlled comparator is greater than the voltage value of the negative input terminal, then each clock-controlled comparator outputs a high level "1"; If the voltage value of the positive input terminal is smaller than the voltage value of the negative input terminal, each clock-controlled comparator outputs a low level "0" respectively.
作为优选，所述的第一钟控比较器用于判断所述的输出电压是否达到开启二分法调整的高阈值电压，所述的第三钟控比较器用于判断所述的输出电压是否达到开启二分法调整的低阈值电压，所述的第二钟控比较器用于通过比较所述的输出电压与所述的额定输出电压的大小来判断每个调整周期中是否需要增减功率开关的导通数目，并以信号形式发送给所述的控制器的信号输入端，在开启二分法调整后，所述的控制器根据所述的第二钟控比较器的信号，在固定的n个时钟周期内经过n轮调整，将所述的输出电压快速调整至趋于所述的额定输出电压。Preferably, the first clocked comparator is used for judging whether the output voltage reaches the high threshold voltage adjusted by the turn-on dichotomy, and the third clocked comparator is used for judging whether the output voltage reaches the turn-on bisector The low threshold voltage adjusted by the method, the second clocked comparator is used to judge whether it is necessary to increase or decrease the conduction number of the power switch in each adjustment cycle by comparing the output voltage and the rated output voltage. , and send it to the signal input terminal of the controller in the form of a signal. After the dichotomy adjustment is turned on, the controller will, according to the signal of the second clock control comparator, within a fixed n clock cycles After n rounds of adjustment, the output voltage is quickly adjusted to approach the rated output voltage.
作为优选，开启二分法调整后，所述的控制器在第1轮调整中导通的功率开关数目的变化量为所述的功率开关阵列中功率开关总数的二分之一，即2n-1；所述的控制器在第2轮调整中导通的功率开关数目的变化量为上一轮调整中导通的功率开关数目的变化量的二分之一，即2n-2；以此类推，所述的控制器在第n轮调整中导通的功率开关数目的变化量为1，二分法调整结束。Preferably, after the dichotomy adjustment is enabled, the amount of change in the number of power switches turned on by the controller in the first round of adjustment is one-half of the total number of power switches in the power switch array, that is, 2 n- 1 ; the variation of the number of power switches that is turned on in the second round of adjustment by the controller is one-half of the variation of the number of power switches that are turned on in the previous round of adjustment, that is, 2 n-2 ; By analogy, the variation of the number of power switches turned on by the controller in the nth round of adjustment is 1, and the dichotomy adjustment ends.
作为优选，将触发所述的第一钟控比较器、第二钟控比较器和第三钟控比较器翻转的阈值电压分别记为VOUT1、VOUT2和VOUT3，将电路的输出电压记为VOUT，将电路的额定输出电压记为VRATED，VOUT3即为所述的高阈值电压，VOUT1即为所述的低阈值电压，其中：Preferably, the threshold voltages that trigger the flipping of the first clocked comparator, the second clocked comparator and the third clocked comparator are recorded as V OUT 1, V OUT 2 and V OUT 3, respectively, and the circuit The output voltage is denoted as V OUT , the rated output voltage of the circuit is denoted as V RATED , V OUT 3 is the high threshold voltage, and V OUT 1 is the low threshold voltage, where:
VRATED＝VOUT2V RATED = V OUT 2
式中，VREF为所述的外部参考电压，R1为所述的第一采样电阻，R2为所述的第二采样电阻，R3为所述的第三采样电阻，R4为所述的第四采样电阻；In the formula, V REF is the external reference voltage, R1 is the first sampling resistor, R2 is the second sampling resistor, R3 is the third sampling resistor, and R4 is the fourth sampling resistor. sampling resistance;
当电路工作在稳定状态时，在每个时钟周期，输出电压VOUT的大小在VOUT2附近上下波动，波动幅度为单个功率开关导通数目的增减所产生的电压幅度；When the circuit works in a stable state, in each clock cycle, the magnitude of the output voltage V OUT fluctuates around V OUT 2, and the fluctuation range is the voltage range generated by the increase or decrease of the number of conduction of a single power switch;
当负载跳变时，VOUT随之跳变，若VOUT1<VOUT<VOUT3，则说明负载跳变导致输出电压小幅波动，则VOUT在n个时钟周期内通过单个功率开关导通数目的增减使输出电压恢复至稳定状态；若VOUT由VOUT1<VOUT<VOUT3变化到VOUT<VOUT1或VOUT>VOUT3，则说明负载跳变导致输出电压大幅波动，触发第一钟控比较器或第三钟控比较器向所述的控制器发出信号，所述的控制器即开启二分法调整，当VOUT<VOUT2，所述的第二钟控比较器向所述的控制器发出需要增加功率开关的导通数目的信号；当VOUT>VOUT2，所述的第二钟控比较器向所述的控制器发出需要减少功率开关的导通数目的信号。When the load jumps, V OUT jumps along with it. If V OUT 1 < V OUT < V OUT 3, it means that the load jump causes the output voltage to fluctuate slightly, then V OUT is conducted through a single power switch within n clock cycles. The increase or decrease of the number of passes restores the output voltage to a stable state; if V OUT changes from V OUT 1 < V OUT < V OUT 3 to V OUT < V OUT 1 or V OUT > V OUT 3, it means that the load jump causes the output When the voltage fluctuates greatly, the first clocked comparator or the third clocked comparator is triggered to send a signal to the controller, and the controller turns on the dichotomy adjustment. When V OUT < V OUT 2, the first The second clocked comparator sends a signal to the controller that the conduction number of the power switch needs to be increased; when V OUT >V OUT 2, the second clocked comparator sends a signal to the controller that the power needs to be reduced The switch's conduction number signal.
判断两种负载跳变的依据为：VOUT2-VOUT1＝VOUT3-VOUT2≈n×Vδ，其中Vδ为单个功率开关变化的电压幅度。不管负载如何跳变，本发明数字LDO电路的瞬态响应恢复时间都在n个时钟周期以内，实现快速瞬态响应。The basis for judging two kinds of load jumps is: V OUT 2-V OUT 1=V OUT 3-V OUT 2≈n×V δ , where V δ is the voltage amplitude of a single power switch change. No matter how the load jumps, the transient response recovery time of the digital LDO circuit of the present invention is within n clock cycles, thereby realizing fast transient response.
作为优选，在二分法调整期间的任意一轮调整中，若调整后导通的功率开关数目大于所述的功率开关阵列中功率开关总数或小于零，则所述的控制器保持该轮调整前的功率开关数目不变直到下一轮调整。Preferably, in any round of adjustment during the dichotomy adjustment period, if the number of power switches that are turned on after the adjustment is greater than the total number of power switches in the power switch array or less than zero, the controller keeps the number of power switches before the adjustment round. The number of power switches remains unchanged until the next round of adjustment.
与现有技术相比，本发明的优点在于：Compared with the prior art, the advantages of the present invention are:
(1)本发明公开的快速瞬态响应的数字LDO电路，采用二分法调整作为控制器的核心控制方案。在输出电压具有大跳变时，启动二分法调整调节功率管数目，能够在较短的固定的周期内将输出电压调节至额定水平；在输出电压具有小跳变时，采用传统逐步调节功率管数目的模式，将输出电压调节至额定水平。因此，本发明数字LDO电路在面对不同负载变化造成的输出电压跳变时，均具有较快的瞬态响应速度，且在瞬态响应中，经过近乎固定的快速的调整周期，使得输出电压恢复到额定值。(1) The digital LDO circuit with fast transient response disclosed in the present invention adopts dichotomy adjustment as the core control scheme of the controller. When the output voltage has a large jump, start the dichotomy to adjust the number of power tubes, and the output voltage can be adjusted to the rated level in a short fixed cycle; when the output voltage has a small jump, the traditional step-by-step adjustment of the power tubes is used. number of modes to regulate the output voltage to the rated level. Therefore, the digital LDO circuit of the present invention has a fast transient response speed when facing the output voltage jump caused by different load changes, and in the transient response, after a nearly fixed and fast adjustment period, the output voltage return to rated value.
(2)相对于其他LDO电路，本发明公开的快速瞬态响应的数字LDO电路，采用纯数字单元的电路结构，能够工作于亚1V的低电源电压环境中，具有静态功耗低、集成度高、瞬态响应快的优点。(2) Compared with other LDO circuits, the digital LDO circuit with fast transient response disclosed in the present invention adopts the circuit structure of pure digital unit, can work in the low power supply voltage environment of sub-1V, and has low static power consumption and high integration. The advantages of high and fast transient response.
附图说明Description of drawings
图1为现有模拟LDO电路的简化结构示意图；1 is a simplified schematic diagram of an existing analog LDO circuit;
图2为现有数字LDO电路的简化结构示意图；2 is a simplified schematic diagram of an existing digital LDO circuit;
图3为实施例的数字LDO电路的结构示意图；3 is a schematic structural diagram of a digital LDO circuit of an embodiment;
图4为实施例中钟控比较器阵列的工作状态示意图；4 is a schematic diagram of a working state of a clocked comparator array in an embodiment;
图5为实施例的数字LDO电路的负载瞬态响应特性曲线；5 is a load transient response characteristic curve of the digital LDO circuit of the embodiment;
图6为本发明中二分法调整的流程示意图。FIG. 6 is a schematic flowchart of the dichotomy adjustment in the present invention.
具体实施方式Detailed ways
以下结合实施例对本发明作进一步详细描述。The present invention will be described in further detail below in conjunction with the embodiments.
实施例的快速瞬态响应的数字LDO电路，如图3所示，包括钟控比较器阵列、控制器、功率开关阵列、采样电阻网络和片内电容，钟控比较器阵列的正输入端与采样电阻网络的输出端连接，钟控比较器阵列的负输入端与外部参考电压连接，钟控比较器阵列的信号输出端与控制器的信号输入端连接，钟控比较器阵列的时钟使能端和控制器的时钟输入端分别与外部采样时钟连接，控制器的信号输出端与功率开关阵列的输入端连接，功率开关阵列的输出端分别与采样电阻网络的输入电极和片内电容的输入电极及输出电压连接，采样电阻网络的输出电极和片内电容的输出电极连接并接地，输出电压与负载相连，负载接地，控制器用于控制功率开关阵列中导通的功率开关数目，进而调整输出电压的大小，当负载跳变导致输出电压大幅波动时，控制器开启二分法调整将输出电压快速恢复至趋于电路的额定输出电压的稳定状态。The fast transient response digital LDO circuit of the embodiment, as shown in Figure 3, includes a clocked comparator array, a controller, a power switch array, a sampling resistor network and an on-chip capacitor. The positive input of the clocked comparator array is connected to The output terminal of the sampling resistor network is connected, the negative input terminal of the clocked comparator array is connected to the external reference voltage, the signal output terminal of the clocked comparator array is connected to the signal input terminal of the controller, and the clock of the clocked comparator array is enabled The terminal and the clock input terminal of the controller are respectively connected with the external sampling clock, the signal output terminal of the controller is connected with the input terminal of the power switch array, and the output terminal of the power switch array is respectively connected with the input electrode of the sampling resistor network and the input of the on-chip capacitor. The electrode is connected to the output voltage. The output electrode of the sampling resistor network is connected to the output electrode of the on-chip capacitor and grounded. The output voltage is connected to the load, and the load is grounded. The controller is used to control the number of power switches that are turned on in the power switch array, and then adjust the output. The size of the voltage, when the load jump causes the output voltage to fluctuate greatly, the controller turns on the dichotomy adjustment to quickly restore the output voltage to a stable state that tends to the rated output voltage of the circuit.
本实施例中，功率开关阵列为一组数量以二进制分布的并联的PMOS晶体管阵列，控制器的信号输出端与PMOS晶体管阵列的各个栅端连接，PMOS晶体管阵列的各个源端与外部输入电压连接，PMOS晶体管阵列的各个漏端分别与采样电阻网络的输入电极和片内电容的输入电极及输出电压连接。In this embodiment, the power switch array is a group of parallel PMOS transistor arrays distributed in binary numbers, the signal output end of the controller is connected to each gate end of the PMOS transistor array, and each source end of the PMOS transistor array is connected to an external input voltage , each drain terminal of the PMOS transistor array is respectively connected with the input electrode of the sampling resistor network and the input electrode and output voltage of the on-chip capacitor.
PMOS晶体管阵列包括7列PMOS晶体管组，根据二进制分布，第j列的PMOS晶体管组由2j-1个相同的PMOS晶体管并联构成，其中1≤j≤7，j∈Z；各列PMOS晶体管组的宽长比W/L从小到大依次为：δ、2δ、22·δ、23·δ、24·δ、25·δ、26·δ，其中δ为单个PMOS晶体管的宽长比；将PMOS晶体管导通视为二进制的“1”，关断视为“0”，则功率开关阵列的开关状态以及功率开关阵列中导通的功率开关数目可以用一组7-bit的二进制数组表示，即控制器输出一组7-bit的二进制信号控制功率开关阵列中导通的功率开关数目。The PMOS transistor array includes 7 columns of PMOS transistor groups. According to the binary distribution, the PMOS transistor group of the jth column is composed of 2 j-1 identical PMOS transistors in parallel, where 1≤j≤7, j∈Z; each column of PMOS transistor groups The width to length ratio W/L from small to large is: δ, 2δ, 2 2 ·δ, 2 3 ·δ, 2 4 ·δ, 2 5 ·δ, 2 6 ·δ, where δ is the width of a single PMOS transistor The length ratio; the on-state of the PMOS transistor is regarded as binary "1" and the off-state is regarded as "0", then the switching state of the power switch array and the number of power switches that are turned on in the power switch array can be determined by a set of 7-bit Binary array representation, that is, the controller outputs a set of 7-bit binary signals to control the number of power switches that are turned on in the power switch array.
采样电阻网络包括串联的第一采样电阻R1、第二采样电阻R2、第三采样电阻R3和第四采样电阻R4，第一采样电阻R1的一端分别与PMOS晶体管阵列的各个漏端和片内电容的输入电极连接，第一采样电阻R1的另一端与第二采样电阻R2的一端连接，第二采样电阻R2的另一端与第三采样电阻R3的一端连接，第三采样电阻R3的另一端与第四采样电阻R4的一端连接，第四采样电阻R4的另一端与片内电容的输出电极连接并接地。The sampling resistor network includes a first sampling resistor R1, a second sampling resistor R2, a third sampling resistor R3 and a fourth sampling resistor R4 connected in series. One end of the first sampling resistor R1 is connected to each drain end of the PMOS transistor array and the on-chip capacitance respectively. The other end of the first sampling resistor R1 is connected to one end of the second sampling resistor R2, the other end of the second sampling resistor R2 is connected to one end of the third sampling resistor R3, and the other end of the third sampling resistor R3 is connected to One end of the fourth sampling resistor R4 is connected, and the other end of the fourth sampling resistor R4 is connected to the output electrode of the on-chip capacitor and grounded.
钟控比较器阵列包括第一钟控比较器CP1、第二钟控比较器CP2和第三钟控比较器CP3，第一钟控比较器CP1的正输入端VH与第一采样电阻R1的另一端连接，第一钟控比较器CP1的负输入端与外部参考电压连接，第二钟控比较器CP2的正输入端VM与与第二采样电阻R2的另一端连接，第二钟控比较器CP2的负输入端与外部参考电压连接，第三钟控比较器CP3的正输入端VL与与第三采样电阻R3的另一端连接，第三钟控比较器CP3的负输入端与外部参考电压连接，第一钟控比较器CP1、第二钟控比较器CP2和第三钟控比较器CP3的时钟使能端分别与外部采样时钟连接，第一钟控比较器CP1、第二钟控比较器CP2和第三钟控比较器CP3的信号输出端分别与控制器的信号输入端连接。The clocked comparator array includes a first clocked comparator CP1, a second clocked comparator CP2, and a third clocked comparator CP3. The positive input terminal VH of the first clocked comparator CP1 is connected to the first sampling resistor R1. The other end is connected, the negative input end of the first clocked comparator CP1 is connected to the external reference voltage, the positive input end VM of the second clocked comparator CP2 is connected to the other end of the second sampling resistor R2, and the second clocked comparator CP2 is connected to the other end of the second sampling resistor R2. The negative input end of the comparator CP2 is connected to the external reference voltage, the positive input end VL of the third clocked comparator CP3 is connected to the other end of the third sampling resistor R3, and the negative input end of the third clocked comparator CP3 is connected to the other end of the third sampling resistor R3. The external reference voltage is connected. The clock enable terminals of the first clocked comparator CP1, the second clocked comparator CP2 and the third clocked comparator CP3 are respectively connected to the external sampling clock. The first clocked comparator CP1, the second clocked comparator CP1 and the second clocked comparator CP3 The signal output terminals of the clocked comparator CP2 and the third clocked comparator CP3 are respectively connected to the signal input terminals of the controller.
第一钟控比较器CP1用于判断输出电压是否达到开启二分法调整的高阈值电压，第三钟控比较器CP3用于判断输出电压是否达到开启二分法调整的低阈值电压，第二钟控比较器CP2用于通过比较输出电压与额定输出电压的大小来判断每个调整周期中是否需要增减功率开关的导通数目，并以信号形式发送给控制器的信号输入端，在开启二分法调整后，控制器根据第二钟控比较器CP2的信号，在固定的7个时钟周期内经过7轮调整，将输出电压快速调整至趋于额定输出电压。The first clock-controlled comparator CP1 is used to judge whether the output voltage reaches the high threshold voltage for turning on the dichotomy adjustment, the third clock-controlled comparator CP3 is used to judge whether the output voltage reaches the low threshold voltage for turning on the dichotomy adjustment, and the second clock-controlled comparator CP3 Comparator CP2 is used to judge whether it is necessary to increase or decrease the conduction number of the power switch in each adjustment cycle by comparing the output voltage and the rated output voltage, and send it to the signal input terminal of the controller in the form of a signal. After the adjustment, the controller quickly adjusts the output voltage to the rated output voltage through 7 rounds of adjustment within a fixed 7 clock cycles according to the signal of the second clocked comparator CP2.
开启二分法调整后，控制器在第1轮调整中导通的功率开关数目的变化量为功率开关阵列中功率开关总数的二分之一，即26；控制器在第2轮调整中导通的功率开关数目的变化量为上一轮调整中导通的功率开关数目的变化量的二分之一，即25；以此类推，控制器在第7轮调整中导通的功率开关数目的变化量为1，二分法调整结束。在二分法调整期间的任意一轮调整中，若调整后导通的功率开关数目大于功率开关阵列中功率开关总数或小于零，则控制器保持该轮调整前的功率开关数目不变直到下一轮调整。After the dichotomy adjustment is turned on, the change in the number of power switches that the controller conducts in the first round of adjustment is one-half of the total number of power switches in the power switch array, that is, 2 6 ; The change in the number of power switches turned on is half of the change in the number of power switches turned on in the previous round of adjustment, that is, 2 5 ; and so on, the power switches turned on by the controller in the seventh round of adjustment The change in the number is 1, and the dichotomy adjustment ends. In any round of adjustment during the dichotomy adjustment period, if the number of power switches turned on after adjustment is greater than the total number of power switches in the power switch array or less than zero, the controller keeps the number of power switches before the adjustment in this round unchanged until the next round of adjustment. wheel adjustment.
如图4所示，将触发第一钟控比较器CP1、第二钟控比较器CP2和第三钟控比较器CP3翻转的阈值电压分别记为VOUT1、VOUT2和VOUT3，将电路的输出电压记为VOUT，将电路的额定输出电压记为VRATED，VOUT3即为高阈值电压，VOUT1即为低阈值电压，其中：As shown in FIG. 4, the threshold voltages that trigger the flipping of the first clocked comparator CP1, the second clocked comparator CP2 and the third clocked comparator CP3 are recorded as V OUT 1, V OUT 2 and V OUT 3, respectively, The output voltage of the circuit is recorded as V OUT , the rated output voltage of the circuit is recorded as V RATED , V OUT 3 is the high threshold voltage, and V OUT 1 is the low threshold voltage, where:
VRATED＝VOUT2V RATED = V OUT 2
式中，VREF为外部参考电压，R1为第一采样电阻R1，R2为第二采样电阻R2，R3为第三采样电阻R3，R4为第四采样电阻R4；In the formula, V REF is the external reference voltage, R1 is the first sampling resistor R1, R2 is the second sampling resistor R2, R3 is the third sampling resistor R3, and R4 is the fourth sampling resistor R4;
当电路工作在稳定状态时，在每个时钟周期，输出电压VOUT的大小在VOUT2附近上下波动，波动幅度为单个功率开关导通数目的增减所产生的电压幅度；When the circuit works in a stable state, in each clock cycle, the magnitude of the output voltage V OUT fluctuates around V OUT 2, and the fluctuation range is the voltage range generated by the increase or decrease of the number of conduction of a single power switch;
当负载跳变时，VOUT随之跳变，若VOUT1<VOUT<VOUT3，则说明负载跳变导致输出电压小幅波动，则VOUT在n个时钟周期内通过单个功率开关导通数目的增减使输出电压恢复至稳定状态；若VOUT由VOUT1<VOUT<VOUT3变化到VOUT<VOUT1或VOUT>VOUT3，则说明负载跳变导致输出电压大幅波动，即第一钟控比较器CP1的输出信号H由“1”变为“0”或第三钟控比较器CP3的输出信号L由“0”变为“1”，触发第一钟控比较器CP1或第三钟控比较器CP3向控制器发出信号，控制器即开启二分法调整，快速地在固定调整周期中将VOUT恢复至VOUT2附近。当VOUT<VOUT2，即第二钟控比较器CP2的输出信号M为“0”，第二钟控比较器CP2向控制器发出需要增加功率开关的导通数目的信号；当VOUT>VOUT2，即第二钟控比较器的输出信号M为“1”，第二钟控比较器CP2向控制器发出需要减少功率开关的导通数目的信号。When the load jumps, V OUT jumps along with it. If V OUT 1 < V OUT < V OUT 3, it means that the load jump causes the output voltage to fluctuate slightly, then V OUT is conducted through a single power switch within n clock cycles. The increase or decrease of the number of passes restores the output voltage to a stable state; if V OUT changes from V OUT 1 < V OUT < V OUT 3 to V OUT < V OUT 1 or V OUT > V OUT 3, it means that the load jump causes the output The voltage fluctuates greatly, that is, the output signal H of the first clocked comparator CP1 changes from "1" to "0" or the output signal L of the third clocked comparator CP3 changes from "0" to "1", triggering the first The clocked comparator CP1 or the third clocked comparator CP3 sends a signal to the controller, and the controller turns on the dichotomy adjustment to quickly restore V OUT to the vicinity of V OUT 2 in a fixed adjustment period. When V OUT < V OUT 2, that is, the output signal M of the second clocked comparator CP2 is “0”, the second clocked comparator CP2 sends a signal to the controller that the number of conduction of the power switch needs to be increased; when V OUT >V OUT 2, that is, the output signal M of the second clocked comparator is "1", and the second clocked comparator CP2 sends a signal to the controller that the number of conduction of the power switch needs to be reduced.
具体来说，该数字LDO电路在工作过程中，若负载变化，导致电路的输出电压VOUT低于二分法调整的低阈值电压，即则第三钟控比较器CP3输出信号L至控制器启动二分法调整，显然则在二分法第1轮调整中，当前PMOS功率开关的导通数目需要增加第1轮的二分值(功率开关改变量)，该二分值为功率开关总数的二分之一，即26，控制器中的加法器将这两组7-bit的二进制数相加后输出到PMOS功率开关阵列，使得其导通数目增加，因此PMOS功率开关阵列的输出电流增加，进而提高输出电压VOUT，之后，根据第二钟控比较器CP2比较更新后的输出电压VOUT和额定输出电压VRATED，若VOUT<VRATED，则PMOS功率开关的导通数目需要增加第2轮的二分值，反之，导通数目将减少第2轮的二分值，其中第2轮的二分值为第1轮的二分之一，即25，然后再根据更新后的VOUT进入第3轮的调整，在调整期间，若改变后的功率开关的导通数目超出范围(大于总数127或小于0)，则保持原来开关状态不变，进入下一轮调整，以此类推，第7轮的二分值为1，此时电路的功率开关的改变量已经近乎遍历了功率开关的总数量，因此，电路的输出电压VOUT与额定电压VRATED十分靠近，当第7轮调整结束，即二分法调整结束时，电路将恢复普通的调整模式，即每个调整周期只改变1个功率开关，而输出电压VOUT将在额定电压VRATED上下趋近，电路的输出电压VOUT恢复稳定；若负载变化，导致电路的输出电压VOUT超过二分法调整的高阈值电压，即则第一钟控比较器CP1输出信号H至控制器启动二分法调整，显然则在二分法第1轮调整中，当前PMOS功率开关的导通数目需要减少第1轮的二分值，即26，控制器中将这两组7-bit的二进制数相减后输出到PMOS功率开关阵列(减法可以通过对减数取补，再相加来实现)，使得其导通数目减少，因此PMOS功率开关阵列的输出电流减少，进而降低输出电压VOUT，之后的调整方式同上。在二分法调整期间，第一钟控比较器CP1、第三钟控比较器CP3的输出信号H、L被置于休眠状态，直到二分法调整结束后，才恢复正常。Specifically, during the operation of the digital LDO circuit, if the load changes, the output voltage V OUT of the circuit will be lower than the low threshold voltage adjusted by the dichotomy, that is, Then the third clocked comparator CP3 outputs the signal L to the controller to start the dichotomy adjustment, obviously Then in the first round of adjustment of the dichotomy method, the current number of PMOS power switches that are turned on needs to be increased by the first round of binary value (power switch change), which is half of the total number of power switches, that is, 2 6. The adder in the controller adds these two sets of 7-bit binary numbers and outputs it to the PMOS power switch array, so that the number of its conduction increases, so the output current of the PMOS power switch array increases, thereby increasing the output voltage V OUT , and then compare the updated output voltage V OUT with the rated output voltage V RATED according to the second clocked comparator CP2 , if V OUT <V RATED , the number of conductions of the PMOS power switch needs to be increased by two points in the second round value, on the contrary, the number of conduction will be reduced by the 2nd round value, where the 2nd round bisect value is half of the 1st round, that is 2 5 , and then enter the 3rd round according to the updated V OUT During the adjustment of the round, if the number of conduction of the changed power switch exceeds the range (greater than the total number of 127 or less than 0), the original switch state will remain unchanged, and enter the next round of adjustment, and so on, the seventh round The dichotomy value of 1 is 1. At this time, the change of the power switches of the circuit has almost traversed the total number of power switches. Therefore, the output voltage V OUT of the circuit is very close to the rated voltage V RATED . When the 7th round of adjustment ends, that is When the dichotomy adjustment is over, the circuit will return to the normal adjustment mode, that is, only one power switch will be changed per adjustment cycle, and the output voltage V OUT will approach the rated voltage V RATED , and the output voltage V OUT of the circuit will return to stability; If the load changes, causing the output voltage VOUT of the circuit to exceed the high threshold voltage of the dichotomy adjustment, i.e. Then the first clocked comparator CP1 outputs the signal H to the controller to start the dichotomy adjustment, obviously Then in the first round of adjustment of the dichotomy method, the current number of PMOS power switches that are turned on needs to be reduced by the binary value of the first round, that is, 2 6 . The controller subtracts these two sets of 7-bit binary numbers and outputs them to PMOS power switch array (subtraction can be achieved by complementing the subtrahend and then adding), so that the number of conductions is reduced, so the output current of the PMOS power switch array is reduced, thereby reducing the output voltage V OUT , the subsequent adjustment method is the same as above . During the dichotomy adjustment period, the output signals H and L of the first clocked comparator CP1 and the third clocked comparator CP3 are put into a dormant state, and return to normal after the dichotomy adjustment is completed.
设定本实施例中的输入电压VIN为0.6V，参考电压VREF为0.5V，额定输出电压为0.55V，采样时钟CLK为10MHz，片内电容为100pF，考虑到内部电路延时和负载充放电速度，控制器内部加入分频器，使得控制器的调整周期变为5×100ns。本实施例中数字LDO电路的负载瞬态响应特性曲线如图5所示，可以看到当该LDO电路的负载从轻载(2mA)跳变到重载(20mA)或从重载(20mA)跳变到轻载(2mA)时，电路开启二分法调整，输出电压VOUT恢复额定水平所需的时间均为3.3μs左右(7×5×100ns)，具有快速瞬态响应的特性。In this embodiment, the input voltage V IN is set to be 0.6V, the reference voltage V REF to be 0.5V, the rated output voltage to be 0.55V, the sampling clock CLK to be 10MHz, and the on-chip capacitance to be 100pF, considering the internal circuit delay and load For the charging and discharging speed, a frequency divider is added inside the controller, so that the adjustment period of the controller becomes 5×100ns. The load transient response characteristic curve of the digital LDO circuit in this embodiment is shown in Figure 5. It can be seen that when the load of the LDO circuit jumps from light load (2mA) to heavy load (20mA) or from heavy load (20mA) When jumping to light load (2mA), the circuit turns on the dichotomy adjustment, and the time required for the output voltage V OUT to recover to the rated level is about 3.3μs (7×5×100ns), which has the characteristics of fast transient response.
本发明中二分法调整的流程示意图见图6。如图6所示，二分法调整的工作原理如下：A schematic flowchart of the dichotomy adjustment in the present invention is shown in FIG. 6 . As shown in Figure 6, the dichotomy adjustment works as follows:
首先，设功率开关阵列包含的功率开关总数为N＝1+2+4+8+…+2n-1≈2n，电路工作在稳定状态时，当前导通的开关数目约为X，该值由一组n-bit的二进制数表示。First, suppose the total number of power switches included in the power switch array is N=1+2+4+8+...+2 n-1 ≈ 2 n , when the circuit works in a stable state, the number of switches that are currently turned on is about X, the Values are represented by a set of n-bit binary numbers.
当负载跳变，同时第一钟控比较器的输出信号H由“1”变为“0”或第三钟控比较器的输出信号L由“0”变为“1”，将开启二分法调整。此时，在第1轮调整周期中，设定需要改变的功率开关数目为总开关数目的二分之一，即将二分法因子i的初值设为1，则第一轮需要改变的功率开关数目该值也由一组n-bit的二进制数表示。When the load jumps and the output signal H of the first clocked comparator changes from "1" to "0" or the output signal L of the third clocked comparator changes from "0" to "1", the dichotomy will be turned on. Adjustment. At this time, in the first round of adjustment cycle, the number of power switches to be changed is set to be half of the total number of switches, that is, the initial value of the dichotomy factor i is set to 1, then the power switches to be changed in the first round number The value is also represented by a set of n-bit binary numbers.
然后，根据第二钟控比较器比较电路当前导通X个功率开关的输出电压VOUT(X)与额定输出电压VRATED的大小来判断需要增加K个导通的功率开关还是减少K个导通的功率开关。若第二钟控比较器的输出信号M为“0”，则导通的功率开关需要增加，即X＝X+K；若第二钟控比较器的输出信号M为“1”，则导通的功率开关需要减少，即X＝X-K。Then, according to the magnitude of the output voltage V OUT (X) and the rated output voltage V RATED that the second clocked comparator comparison circuit currently conducts the X power switches, it is determined whether it is necessary to increase the K power switches that are turned on or reduce the K power switches. On power switch. If the output signal M of the second clocked comparator is "0", the number of power switches to be turned on needs to be increased, that is, X=X+K; if the output signal M of the second clocked comparator is "1", the The number of power switches that are turned on needs to be reduced, that is, X=XK.
但X存在上下限，它不能超过功率开关总数N，并且不能为负数。因此，当X+K>N或X-K<0时，则使导通的功率开关保持该轮调整前的功率开关数目不变，直到下一轮调整。But X has upper and lower limits, it cannot exceed the total number of power switches N, and cannot be negative. Therefore, when X+K>N or X-K<0, the number of power switches that are turned on is kept unchanged until the next round of adjustment.
当X调整完毕后，电路的输出电压也会随之动态调整，之后进入第2轮调整。第2轮的功率开关改变量为上一轮的二分之一，因此，二分法因子i＝i+1，功率开关的改变量之后的调整方案和上一轮调整一致。When X is adjusted, the output voltage of the circuit will also be dynamically adjusted, and then enter the second round of adjustment. The change amount of the power switch in the second round is half of the previous round. Therefore, the dichotomy factor i=i+1, the change amount of the power switch The subsequent adjustment plan is the same as the previous round of adjustment.
最后，经过n轮调整，功率开关的改变量K＝1，即i＝log2N≈n，二分法调整结束。此时整个二分法调整周期中功率开关的变化量已经遍历了功率开关总数，输出电压VOUT也重新恢复到额定输出电压VRATED附近。Finally, after n rounds of adjustment, the change amount of the power switch is K=1, that is, i=log 2 N≈n, and the dichotomy adjustment ends. At this time, the variation of the power switches in the entire dichotomy adjustment cycle has traversed the total number of power switches, and the output voltage V OUT has also recovered to the vicinity of the rated output voltage V RATED .
在二分法调整中，二分法的启动机制将处于休眠状态，避免被重复触发，直到调整结束，启动机制才恢复正常。In the dichotomy adjustment, the start-up mechanism of the dichotomy will be in a dormant state to avoid being repeatedly triggered, and the start-up mechanism will not return to normal until the end of the adjustment.
Claims (9)
1. a kind of digital LDO circuit of fast transient response, it is characterised in that including clocked comparator array, controller, power Capacitor in switch arrays, sampling resistor network and piece, the positive input terminal of the clocked comparator array and sampling electricity The output end connection of network is hindered, the negative input end of the clocked comparator array is connect with external reference voltage, the clock The signal output end of control comparator array is connect with the signal input part of the controller, the clocked comparator array The input end of clock of clock enable end and the controller is connect with external sampling clock respectively, the signal of the controller Output end is connect with the input terminal of the array of power switches, the output end of the array of power switches respectively with it is described The input electrode of sampling resistor network is connected with the input electrode of capacitor in the piece and output voltage, the sampling resistor The output electrode connect and ground of capacitor in the output electrode of network and the piece, the output voltage are connected with load, The carrying ground, the controller are used to control the power switch number be connected in the array of power switches, into And the size of the output voltage is adjusted, when load jump leads to output voltage fluctuation, the controller is opened Dichotomy is adjusted the stable state of the fast quick-recovery of output voltage to the rated output voltage for tending to circuit.
2. a kind of digital LDO circuit of fast transient response according to claim 1, it is characterised in that the power is opened Closing array is one group of quantity with the PMOS transistor array in parallel of binary distributed, the signal output end of the controller with Each grid end of the PMOS transistor array connects, each source and the external input electricity of the PMOS transistor array Pressure connection, each drain terminal of the PMOS transistor array respectively with the input electrode of the sampling resistor network and described Piece in capacitor input electrode and output voltage connection.
3. a kind of digital LDO circuit of fast transient response according to claim 2, it is characterised in that the PMOS is brilliant Body pipe array includes n column PMOS transistor group, and according to binary distributed, the PMOS transistor group of jth column is by 2j-1It is a identical PMOS transistor parallel connection is constituted, wherein 1≤j≤n, j ∈ Z；The breadth length ratio W/L of each column PMOS transistor group is from small to large successively Are as follows: δ, 2 δ, 22·δ、23·δ、…、2n-1δ, wherein δ is the breadth length ratio of single PMOS transistor；The controller output one The power switch number be connected in the binary signal control of the group n-bit array of power switches.
4. a kind of digital LDO circuit of fast transient response according to claim 3, it is characterised in that the sampling electricity Resistance network includes concatenated first sampling resistor, the second sampling resistor, third sampling resistor and the 4th sampling resistor, and described the One end of one sampling resistor is electric with the input of capacitor in each drain terminal and the piece of the PMOS transistor array respectively Pole connection, the other end of first sampling resistor are connect with one end of second sampling resistor, and described second adopts The other end of sample resistance is connect with one end of the third sampling resistor, the other end of the third sampling resistor with it is described The 4th sampling resistor one end connection, the output electrode of capacitor in the other end of the 4th sampling resistor and the piece Connect and ground.
5. a kind of digital LDO circuit of fast transient response according to claim 4, it is characterised in that the clock ratio It include the first clocked comparator, the second clocked comparator and third clocked comparator compared with device array, first clock compares The positive input terminal of device is connect with the other end of first sampling resistor, the negative input end of first clocked comparator with The external reference voltage connection, the positive input terminal of second clocked comparator are another with second sampling resistor One end connection, the negative input end of second clocked comparator are connect with the external reference voltage, the third clock The positive input terminal of control comparator is connect with the other end of the third sampling resistor, and bearing for the third clocked comparator is defeated Enter end to connect with the external reference voltage, first clocked comparator, the second clocked comparator and third clock ratio It is connect respectively with the external sampling clock compared with the clock enable end of device, first clocked comparator, the second clock ratio It is connect respectively with the signal input part of the controller compared with device and the signal output end of third clocked comparator.
6. a kind of digital LDO circuit of fast transient response according to claim 5, it is characterised in that first clock Control comparator is used to judge whether the output voltage reaches the high threshold voltage for opening dichotomy adjustment, the third clock Control comparator is used to judge whether the output voltage reaches the low threshold voltage for opening dichotomy adjustment, second clock Control comparator is used to judge each adjustment week by comparing the size of the output voltage and the rated output voltage The interim conducting number for whether needing to increase and decrease power switch, and it is sent to signal form the signal input of the controller End, after opening dichotomy adjustment, the controller is according to the signal of second clocked comparator, at fixed n By n wheel adjustment in clock cycle, the output voltage is quickly adjusted to tending to the rated output voltage.
7. a kind of digital LDO circuit of fast transient response according to claim 6, it is characterised in that open dichotomy tune After whole, the variable quantity for the power switch number that the controller is connected in the 1st wheel adjustment is the array of power switches The half of middle power switch sum, i.e., 2n-1；The power switch number that the controller is connected in the 2nd wheel adjustment Variable quantity is the half of the variable quantity of power switch number be connected in last round of adjustment, i.e., 2n-2；And so on, it is described The variable quantity of power switch number that is connected in the n-th wheel adjustment of controller be 1, dichotomy adjustment terminates.
8. a kind of digital LDO circuit of fast transient response according to claim 7, it is characterised in that triggering is described The threshold voltage of first clocked comparator, the second clocked comparator and the overturning of third clocked comparator is denoted as V respectivelyOUT1、VOUT2 And VOUT3, the output voltage of circuit is denoted as VOUT, the rated output voltage of circuit is denoted as VRATED, VOUT3 be the height Threshold voltage, VOUT1 is the low threshold voltage, in which:
VRATED=VOUT2
In formula, VREFFor the external reference voltage, R1 is first sampling resistor, and R2 is the second sampling electricity Resistance, R3 are the third sampling resistor, and R4 is the 4th sampling resistor；
When circuit work is in stable state, in each clock cycle, output voltage VOUTSize in VOUTWave above and below near 2 Dynamic, fluctuating range is that voltage amplitude caused by the increase and decrease of number is connected in single power switch；
When load jump, VOUTIt jumps therewith, if VOUT1<VOUT<VOUT3, then illustrate that load jump leads to the small amplitude wave of output voltage It moves, then VOUTRestore output voltage to stablizing shape by the increase and decrease that number is connected in single power switch within n clock cycle State；If VOUTBy VOUT1<VOUT<VOUT3 change to VOUT<VOUT1 or VOUT>VOUT3, then illustrate that load jump causes output voltage big Amplitude wave is dynamic, triggers the first clocked comparator or third clocked comparator to the controller and issues signal, the controller Dichotomy adjustment is opened, V is worked asOUT<VOUT2, second clocked comparator needs to increase function to the controller sending The signal of the conducting number of rate switch；Work as VOUT>VOUT2, second clocked comparator is issued to the controller to be needed Reduce the signal of the conducting number of power switch.
9. a kind of digital LDO circuit of fast transient response according to claim 7, it is characterised in that adjusted in dichotomy In any one wheel adjustment of period, if the power switch number be connected after adjustment is greater than power in the array of power switches and opens It closes sum or less than zero, then the power switch invariable number before the controller keeps the wheel to adjust is until next round adjustment.
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