CN110319894B - Pulse signal detection circuit applied to metering instrument - Google Patents
- ️Tue Feb 13 2024
CN110319894B - Pulse signal detection circuit applied to metering instrument - Google Patents
Pulse signal detection circuit applied to metering instrument Download PDFInfo
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Publication number
- CN110319894B CN110319894B CN201910573018.3A CN201910573018A CN110319894B CN 110319894 B CN110319894 B CN 110319894B CN 201910573018 A CN201910573018 A CN 201910573018A CN 110319894 B CN110319894 B CN 110319894B Authority
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- resistor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
- G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
- G01F1/66—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by measuring frequency, phase shift or propagation time of electromagnetic or other waves, e.g. using ultrasonic flowmeters
- G01F1/661—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by measuring frequency, phase shift or propagation time of electromagnetic or other waves, e.g. using ultrasonic flowmeters using light
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
- G01F15/00—Details of, or accessories for, apparatus of groups G01F1/00 - G01F13/00 insofar as such details or appliances are not adapted to particular types of such apparatus
- G01F15/07—Integration to give total flow, e.g. using mechanically-operated integrating mechanism
- G01F15/075—Integration to give total flow, e.g. using mechanically-operated integrating mechanism using electrically-operated integrating means
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- Physics & Mathematics (AREA)
- Fluid Mechanics (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention relates to the field of metering instruments, in particular to a pulse signal detection circuit applied to a metering instrument, which comprises the following components: the input end of the double-schmitt type inverter is connected with the pulse signal and is used for converting the pulse signal into two inverted pulse level signals; the phase shifting circuit is connected with the double-schmitt type phase inverter and is used for avoiding that the edges of two inverted pulse level signals are at the same time; a push-pull output circuit connected with the phase shift circuit; and the processor is connected with the push-pull output circuit and is used for detecting the pulse signal according to the output of the push-pull output circuit. The invention has the following beneficial effects: the detection of the pulse signal is realized through the double schmitt type phase inverter, the phase shifting circuit, the push-pull output circuit and the processor which are connected in sequence.
Description
Technical Field
The invention relates to the field of metering instruments, in particular to a pulse signal detection circuit applied to a metering instrument.
Background
In the gas cumulative amount detection, the cumulative amount of gas in the meter is generally detected by detecting the number of LED blinking pulses in the meter.
The main principle of detecting pulses can be generalized to detect high level and detect low level. The detection of high level requires a high level voltage output with a high driving capability, and the detection of low level requires a low level voltage output with a high driving capability. The practical scheme is usually open drain output or push-pull output, and the open drain output mode can only ensure that the low level detection principle is available. The push-pull output mode can support high level detection and low level detection, but a switching tube is easy to conduct simultaneously, so that a power supply is short-circuited, and a circuit is damaged.
Disclosure of Invention
In order to solve the above problems, the present invention provides a pulse signal detection circuit applied to a metering device.
A pulse signal detection circuit for a metering device, comprising:
the input end of the double-schmitt type inverter is connected with the pulse signal and is used for converting the pulse signal into two inverted pulse level signals;
the phase shifting circuit is connected with the double-schmitt type phase inverter and is used for avoiding that the edges of two inverted pulse level signals are at the same time;
a push-pull output circuit connected with the phase shift circuit; and
and the processor is connected with the push-pull output circuit and is used for detecting the pulse signals according to the output of the push-pull output circuit.
Preferably, the first input end of the dual schmitt type inverter is connected with a pulse signal, the first output end of the dual schmitt type inverter is connected with the second input end and the phase shifting circuit, and the second output end of the dual schmitt type inverter is connected with the phase shifting circuit.
Preferably, the phase shift circuit includes: the dual-input-output circuit comprises a first RC circuit, a second RC circuit and a dual-AND-gate circuit, wherein a first input end of the dual-AND-gate circuit is connected with a first output end of the dual-Schmitt-type inverter, a second input end of the dual-AND-gate circuit is connected with an output end of the first RC circuit, an input end of the first RC circuit is connected with an output end of the second RC circuit, an input end of the second RC circuit is connected with a second output end of the dual-Schmitt-type inverter, a fourth input end of the dual-AND-gate circuit is connected with a second output end of the dual-Schmitt-type inverter, and both the first output end and the second output end of the dual-AND-gate circuit are connected with a push-pull output circuit.
Preferably, the first RC circuit includes: the double-schmitt-type inverter comprises a resistor R11 and a capacitor C6, wherein one end of the resistor R11 is connected with a first output end of the double-schmitt-type inverter, the other end of the resistor R11 is connected with a second input end of the double-AND-gate circuit and one end of the capacitor C6, and the other end of the capacitor C6 is connected with a common ground.
Preferably, the second RC circuit includes: the double-schmitt-type inverter comprises a resistor R12 and a capacitor C9, wherein one end of the resistor R12 is connected with the second output end of the double-schmitt-type inverter, the other end of the resistor R11 is connected with the third input end of the double-AND-gate circuit and one end of the capacitor C9, and the other end of the capacitor C9 is connected with the common ground.
Preferably, the push-pull output circuit includes: the resistor R1, R2, R3, R5, R7, R8, triode Q2, PMOS Q1 and NMOS Q3, one end of the resistor R3 is connected with the first output end of the double AND gate circuit, the other end of the resistor R3 is connected with one end of the resistor R5 and the base electrode of the triode Q2, the other end of the resistor R5 is connected with the common ground, the emitter electrode of the triode Q2 is connected with the common ground, the collector electrode of the triode Q2 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with one end of the resistor R1 and the grid electrode of the PMOS Q1, the other end of the resistor R1 is connected with the power input end, the source electrode of the PMOS Q1 is connected with the power input end, and the drain electrode of the PMOS Q1 is connected with the processor; one end of the resistor R7 is connected with the second output end of the double AND gate circuit, the other end of the resistor R7 is connected with one end of the resistor R8 and the grid electrode of the NMOS Q3, the other end of the resistor R8 is connected with the common ground, the source electrode of the NMOS Q3 is connected with the common ground, and the drain electrode of the NMOS Q3 is connected with the processor.
Preferably, the push-pull output circuit further includes: fuse F2, diode D1, D2 and electric capacity C1, the positive pole of diode D1, the negative pole of diode D2, the drain electrode of PMOS Q1 and the drain electrode of NMOS Q3 are connected to fuse F2's one end, the treater is connected to fuse F2's the other end, the common ground is connected to diode D2's positive pole, the one end of power input and electric capacity C1 is connected to diode D1's negative pole, the common ground is connected to electric capacity C1's the other end.
Preferably, the method further comprises: and the voltage-stabilizing power supply circuit is connected with the double-schmitt-type inverter.
The invention has the following beneficial effects:
1. the detection of the pulse signals is realized through the double Schmitt type phase inverter, the phase shifting circuit, the push-pull output circuit and the processor which are sequentially connected, and the accumulated gas quantity of the metering instrument is obtained according to the detection of the pulse signals;
2. the phase shifting circuit is used for avoiding the edges of two opposite-phase level signal changes from being in the same time, so that the phenomenon that a power supply is short-circuited and a circuit is damaged due to the fact that a switching tube is conducted simultaneously is avoided, and the push-pull output circuit is more reliable;
3. the diodes D1 and D2 are used, so that the clamping voltage range follows the power input voltage, and the characteristic of wide voltage can be matched better. For current limiting protection, the fuse F2 does not affect the circuit work under normal conditions, and the current limiting is triggered abnormally;
4. the voltage stabilizing power supply circuit is used for reducing the input wide voltage to a fixed lower voltage, and the voltage can enable a photoelectric conversion circuit, a double schmitt type inverter and a phase shifting circuit in a subsequent circuit to work normally.
Drawings
The invention will be described in further detail with reference to the drawings and the detailed description.
FIG. 1 is a schematic diagram showing connection of a pulse signal detection circuit applied to a metering device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram showing connection of a dual Schmitt type inverter in a pulse signal detection circuit for a meter according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an output signal of a dual Schmidt-type inverter in a pulse signal detection circuit for a meter according to an embodiment of the invention;
FIG. 4 is a schematic circuit diagram of a phase shifting circuit in a pulse signal detection circuit for a metering device according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a phase shift circuit output signal applied to a pulse signal detection circuit of a metering device according to an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a push-pull output circuit in a pulse signal detection circuit for a metering device according to an embodiment of the present invention;
FIG. 7 is a schematic circuit diagram of a push-pull output circuit in a pulse signal detection circuit for a metering device according to another embodiment of the present invention;
FIG. 8 is a schematic diagram showing connection of a regulated power supply circuit in a pulse signal detection circuit for a metering device according to an embodiment of the present invention;
fig. 9 is a schematic circuit diagram of a regulated power supply circuit applied to a pulse signal detection circuit of a metering device according to another embodiment of the present invention.
Detailed Description
The technical scheme of the present invention will be further described with reference to the accompanying drawings, but the present invention is not limited to these examples.
The basic idea of this embodiment is to output pulses using a push-pull output circuit, but to which a dual schmitt-type inverter and a phase shift circuit are connected at the input. The double schmitt type inverter is used for converting the pulse signal into two inverted pulse level signals; the phase shifting circuit is used for avoiding the edges of two opposite-phase level signal changes from being in the same time, so that the phenomenon that a power supply is short-circuited and a circuit is damaged due to the fact that a switching tube is conducted simultaneously is avoided, and the accumulated gas quantity of the metering instrument is obtained according to the detection of pulse signals.
Based on the above-mentioned idea, an embodiment of the present invention proposes a pulse signal detection circuit applied to a metering device, as shown in fig. 1, including: the input end of the double-schmitt type inverter is connected with the pulse signal and is used for converting the pulse signal into two inverted pulse level signals; the phase shifting circuit is connected with the double-schmitt type phase inverter and is used for avoiding that the edges of two inverted pulse level signals are at the same time; a push-pull output circuit connected with the phase shift circuit; and the processor is connected with the push-pull output circuit and is used for detecting the pulse signal according to the output of the push-pull output circuit.
As shown in fig. 2, a first input end of the dual schmitt type inverter is connected with a pulse signal, a first output end of the dual schmitt type inverter is connected with a second input end and a phase shifting circuit, and a second output end of the dual schmitt type inverter is connected with the phase shifting circuit.
The dual schmitt-type inverter uses a 74LVC2G14 of TI, a flip-flop containing two channels, and the flip-flop also has an inverting function. The two channels of the final dual schmitt type inverter output inverted two pulse level signals Y1, Y2, respectively, as shown in fig. 3. The pulse signal can be converted into a high-low digital level signal by the processing of the double schmitt type inverter.
As shown in fig. 4, the phase shift circuit includes: the dual-input-output circuit comprises a first RC circuit, a second RC circuit and a dual-AND-gate circuit, wherein a first input end of the dual-AND-gate circuit is connected with a first output end of the dual-Schmitt-type inverter, a second input end of the dual-AND-gate circuit is connected with an output end of the first RC circuit, an input end of the first RC circuit is connected with an output end of the second RC circuit, an input end of the second RC circuit is connected with a second output end of the dual-Schmitt-type inverter, a fourth input end of the dual-AND-gate circuit is connected with a second output end of the dual-Schmitt-type inverter, and both the first output end and the second output end of the dual-AND-gate circuit are connected with a push-pull output circuit.
Wherein the first RC circuit includes: the double-schmitt-type inverter comprises a resistor R11 and a capacitor C6, wherein one end of the resistor R11 is connected with a first output end of the double-schmitt-type inverter, the other end of the resistor R11 is connected with a second input end of the double-AND-gate circuit and one end of the capacitor C6, and the other end of the capacitor C6 is connected with a common ground.
Wherein the second RC circuit comprises: the double-schmitt-type inverter comprises a resistor R12 and a capacitor C9, wherein one end of the resistor R12 is connected with the second output end of the double-schmitt-type inverter, the other end of the resistor R11 is connected with the third input end of the double-AND-gate circuit and one end of the capacitor C9, and the other end of the capacitor C9 is connected with the common ground.
In practice, there is a time difference between the alternating on and off processes of the two MOS transistors, so there may be a very short period of time, and both the two MOS transistors are in an on state, resulting in a short circuit of the power supply. Therefore, a phase shift circuit needs to be introduced to slightly shift the timing of the two signal changes. As shown in fig. 5, A1 is a first input end pulse level signal, B1 is a second input end pulse level signal, Y1 is a first output end pulse level signal, A2 is a third input end pulse level signal, B2 is a fourth input end pulse level signal, Y2 is a second output end pulse level signal, two RC circuits enable edge time of the B1 and B2 pulse signals to be prolonged, a double and gate circuit can recognize voltages below 0.3VCC as low level, voltages above 0.7VCC as high level, and by utilizing the characteristics, edges of two paths of signals Y1 and Y2 output by the double and gate are completely staggered, so that simultaneous conduction of a MOS transistor of a later push-pull circuit is avoided. Wherein the staggering time depends on the RC value, and the RC value cannot be too large.
As shown in fig. 6, the push-pull output circuit includes: the resistor R1, R2, R3, R5, R7, R8, triode Q2, PMOS Q1 and NMOS Q3, one end of the resistor R3 is connected with the first output end of the double AND gate circuit, the other end of the resistor R3 is connected with one end of the resistor R5 and the base electrode of the triode Q2, the other end of the resistor R5 is connected with the common ground, the emitter electrode of the triode Q2 is connected with the common ground, the collector electrode of the triode Q2 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with one end of the resistor R1 and the grid electrode of the PMOS Q1, the other end of the resistor R1 is connected with the power input end, the source electrode of the PMOS Q1 is connected with the power input end, and the drain electrode of the PMOS Q1 is connected with the processor; one end of the resistor R7 is connected with the second output end of the double AND gate circuit, the other end of the resistor R7 is connected with one end of the resistor R8 and the grid electrode of the NMOS Q3, the other end of the resistor R8 is connected with the common ground, the source electrode of the NMOS Q3 is connected with the common ground, and the drain electrode of the NMOS Q3 is connected with the processor.
The signal Y1 controls the PMOS Q1, the signal Y2 controls the NMOS Q3, and the control logic is high-level on and low-level off. When the signal Y1 outputs a high level and the signal Y2 outputs a low level, the triode Q2 is turned on, the PMOS Q1 is turned on, the NMOS Q3 is turned off, and the power supply voltage is output in a pulse mode; when the signal Y1 outputs a low level and the signal Y2 outputs a high level, the triode Q2 is turned off, the PMOS Q1 is turned off, the NMOS Q3 is turned on, and the common ground voltage is pulsed. Since the signals Y1 and Y2 are subjected to the phase shift dislocation process, the PMOS Q1 and the NMOS Q3 cannot be turned on at the same time. Wherein, the PMOS Q1 is WPM3012, the limit GS withstand voltage is 20V, and the minimum starting voltage of GS is more than 3V. However, the actual working voltage range is 5V-24V, and the GS can be higher than the starting voltage when the lowest 5V supplies power and lower than the limit withstand voltage value of 20V when the highest 24V supplies power through the voltage division of the two resistors R1 and R2.
As shown in fig. 7, in an embodiment, the push-pull output circuit further includes: fuse F2, diode D1, D2 and electric capacity C1, the positive pole of diode D1, the negative pole of diode D2, the drain electrode of PMOS Q1 and the drain electrode of NMOS Q3 are connected to fuse F2's one end, the treater is connected to fuse F2's the other end, the common ground is connected to diode D2's positive pole, the one end of power input and electric capacity C1 is connected to diode D1's negative pole, the common ground is connected to electric capacity C1's the other end.
Two diodes D1 and D2 are added to the output end of the push-pull output circuit, and the voltage of the output signal end is limited between-0.7V and 24.7V, so that the interface has certain anti-surge interference capability when being connected with different external detection devices, and the internal circuit is protected. Meanwhile, as the push-pull output circuit is used, the driving capability of output pulses is strong, and in order to protect a switching tube in the push-pull circuit, the pulse output is added with a 500mA self-recovery fuse F2, so that the circuit is not damaged accidentally even if the external interface is in wrong wiring.
The processor in this embodiment includes an arithmetic logic unit, a register unit, a control unit, and the like, and has functions of processing instructions, executing operations, controlling time, processing data, and the like. The processor detects the pulse signal according to the output of the push-pull output circuit. The processor can judge the quantity of the scintillation pulse sent by the gas outlet quantity detection lamp through detecting and receiving the high-low level pulse signals, and the detection of the accumulated gas quantity of the metering instrument can be realized according to the quantity of the scintillation pulse.
In one embodiment, as shown in fig. 8, the present invention further includes: and the voltage-stabilizing power supply circuit is connected with the photoelectric conversion circuit and the double-schmitt type inverter. As shown in fig. 9, the regulated power supply circuit includes: regulated power supply chip U1, electric capacity C2, C3, C4, V of said regulated power supply chip IN The end is connected with the power input end, the GND end is connected with the public ground, V OUT The power supply output end is connected, one end of the capacitor C2 is connected with the power supply input end, the other end of the capacitor C2 is connected with the public ground, one end of the capacitor C3 is connected with the power supply output end, the other end of the capacitor C4 is connected with the public ground.
The regulated power supply chip U1 adopts the TLV76033 of TI, the input voltage range can support 5V-30V, the output voltage is 3.3V which is fixed, and the maximum output load can reach 100mA. The periphery only needs a few ceramic capacitors C2, C3 and C4, so that the power supply requirement can be met. The voltage-stabilizing power supply chip U1 reduces the input voltage VDD of 5V-24V to a fixed lower voltage VCC (below 5V), and the VCC voltage can enable a photoelectric conversion circuit, a double-Schmitt type inverter and the like in a subsequent circuit to work normally.
Those skilled in the art may make various modifications or additions to the described embodiments or substitutions thereof without departing from the spirit of the invention or exceeding the scope of the invention as defined in the accompanying claims.
Claims (8)
1. A pulse signal detection circuit applied to a metering device, comprising:
the input end of the double-schmitt type inverter is connected with the pulse signal and is used for converting the pulse signal into two inverted pulse level signals;
the phase shifting circuit is connected with the double-schmitt type phase inverter and is used for avoiding that the edges of two inverted pulse level signals are at the same time;
a push-pull output circuit connected with the phase shift circuit; and
and the processor is connected with the push-pull output circuit and is used for detecting the pulse signals according to the output of the push-pull output circuit.
2. The pulse signal detection circuit for a metering device according to claim 1, wherein the first input end of the double schmitt type inverter is connected with a pulse signal, the first output end of the double schmitt type inverter is connected with the second input end and the phase shifting circuit, and the second output end of the double schmitt type inverter is connected with the phase shifting circuit.
3. The pulse signal detection circuit for a metering device according to claim 2, wherein the phase shift circuit comprises: the dual-input-output circuit comprises a first RC circuit, a second RC circuit and a dual-AND-gate circuit, wherein a first input end of the dual-AND-gate circuit is connected with a first output end of the dual-Schmitt-type inverter, a second input end of the dual-AND-gate circuit is connected with an output end of the first RC circuit, an input end of the first RC circuit is connected with an output end of the second RC circuit, an input end of the second RC circuit is connected with a second output end of the dual-Schmitt-type inverter, a fourth input end of the dual-AND-gate circuit is connected with a second output end of the dual-Schmitt-type inverter, and both the first output end and the second output end of the dual-AND-gate circuit are connected with a push-pull output circuit.
4. A pulse signal detection circuit for a metering device according to claim 3, wherein the first RC circuit comprises: the double-schmitt-type inverter comprises a resistor R11 and a capacitor C6, wherein one end of the resistor R11 is connected with a first output end of the double-schmitt-type inverter, the other end of the resistor R11 is connected with a second input end of the double-AND-gate circuit and one end of the capacitor C6, and the other end of the capacitor C6 is connected with a common ground.
5. A pulse signal detection circuit for a metering device according to claim 3, wherein the second RC circuit comprises: the double-schmitt-type inverter comprises a resistor R12 and a capacitor C9, wherein one end of the resistor R12 is connected with the second output end of the double-schmitt-type inverter, the other end of the resistor R11 is connected with the third input end of the double-AND-gate circuit and one end of the capacitor C9, and the other end of the capacitor C9 is connected with the common ground.
6. A pulse signal detection circuit for use in a metering device according to claim 3, wherein the push-pull output circuit comprises: the resistor R1, R2, R3, R5, R7, R8, triode Q2, PMOS Q1 and NMOS Q3, one end of the resistor R3 is connected with the first output end of the double AND gate circuit, the other end of the resistor R3 is connected with one end of the resistor R5 and the base electrode of the triode Q2, the other end of the resistor R5 is connected with the common ground, the emitter electrode of the triode Q2 is connected with the common ground, the collector electrode of the triode Q2 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with one end of the resistor R1 and the grid electrode of the PMOS Q1, the other end of the resistor R1 is connected with the power input end, the source electrode of the PMOS Q1 is connected with the power input end, and the drain electrode of the PMOS Q1 is connected with the processor; one end of the resistor R7 is connected with the second output end of the double AND gate circuit, the other end of the resistor R7 is connected with one end of the resistor R8 and the grid electrode of the NMOS Q3, the other end of the resistor R8 is connected with the common ground, the source electrode of the NMOS Q3 is connected with the common ground, and the drain electrode of the NMOS Q3 is connected with the processor.
7. The pulse signal detection circuit for a metering device of claim 6, wherein the push-pull output circuit further comprises: fuse F2, diode D1, D2 and electric capacity C1, the positive pole of diode D1, the negative pole of diode D2, the drain electrode of PMOS Q1 and the drain electrode of NMOS Q3 are connected to fuse F2's one end, the treater is connected to fuse F2's the other end, the common ground is connected to diode D2's positive pole, the one end of power input and electric capacity C1 is connected to diode D1's negative pole, the common ground is connected to electric capacity C1's the other end.
8. The pulse signal detection circuit for a metering device according to any one of claims 1 to 7, further comprising: and the voltage-stabilizing power supply circuit is connected with the double-schmitt-type inverter.
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