CN110690927A - Digital-analog hybrid optical phase-locked loop system based on undersampling - Google Patents

一种基于欠采样的数模混合式光学锁相环系统，可应用于高速高灵敏度的零差相干解调激光通信系统中。通过将信号光和本振光经90度光学桥接器和平衡探测器转化为模拟电信号后，模拟数字转换器(ADC)对该电信号进行欠采样，以现场可编程逻辑门阵列(FPGA)为控制器来提取相位误差信号，相位误差信号经过数字环路滤波后驱动直接数字频率合成器(DDS)产生频率和相位都受控的误差信号，进而实现光学锁相。本发明的特点是采用欠采样的方式实现相位误差信号的提取，减小了对接收端电子学带宽及数字信号处理速度的要求。同时通过外调制的方式控制本振光，提高了环路控制带宽和锁相性能。本发明可以实现高速高灵敏度的零差相干解调。

An undersampling-based digital-analog hybrid optical phase-locked loop system can be applied to a high-speed and high-sensitivity homodyne coherent demodulation laser communication system. After converting the signal light and the local oscillator light into an analog electrical signal through a 90-degree optical bridge and a balanced detector, the analog-to-digital converter (ADC) undersamples the electrical signal to generate a Field Programmable Logic Gate Array (FPGA). To extract the phase error signal for the controller, the phase error signal is filtered by a digital loop and then drives a direct digital frequency synthesizer (DDS) to generate an error signal with controlled frequency and phase, thereby realizing optical phase locking. The invention is characterized in that the extraction of the phase error signal is realized by means of under-sampling, which reduces the requirements for the electronic bandwidth of the receiving end and the processing speed of the digital signal. At the same time, the local oscillator light is controlled by means of external modulation, which improves the loop control bandwidth and phase-locking performance. The present invention can realize high-speed and high-sensitivity homodyne coherent demodulation.

基于欠采样的数模混合式光学锁相环系统Digital-analog hybrid optical phase-locked loop system based on undersampling

技术领域technical field

本发明涉及高速零差相干解调的相干光通信领域，特别是一种基于欠采样的数模混合式光学锁相环系统，该系统装置可以放宽对接收电子学器件带宽的要求。The invention relates to the field of coherent optical communication of high-speed homodyne coherent demodulation, in particular to a digital-analog hybrid optical phase-locked loop system based on subsampling, which can relax the requirements for the bandwidth of receiving electronic devices.

背景技术Background technique

相干激光通信具有高速率、高灵敏度等优点，正在逐步取代传统的强度调制直接探测。对于高速光信号的零差相干接收而言，接收端需要一个光学锁相环对本振光和接收到的信号光进行相位误差信号的提取进而锁定。光学锁相环的实现主要有两个技术难点：首先是在高速率调制下，锁相误差信号的提取；其次是本振光的控制方式。Coherent laser communication has the advantages of high speed and high sensitivity, and is gradually replacing the traditional direct detection of intensity modulation. For the homodyne coherent reception of high-speed optical signals, an optical phase-locked loop is required at the receiving end to extract and lock the phase error signal of the local oscillator light and the received signal light. The realization of the optical phase-locked loop mainly has two technical difficulties: the first is the extraction of the phase-locked error signal under the high-speed modulation; the second is the control method of the local oscillator.

现有技术[1](孙建锋,许蒙蒙,张波,等.基于2X4 90°光学桥接器的自由空间相干光通信探测装置：CN105634591A.2016)提出用VCO对本振光进行边带调制以提高本振光的控制带宽。这种方式可以把光学锁相环的闭环带宽提高到600KHz附近，但是该类本振光控制方式较为复杂且光学效率较低。现有技术[2](徐健,黄丽艳,何国良,等.一种相干光接收装置中的载波相位估计方法:CN105763265A.2016)提出在数字域采用载波相位估计的方法进行信号解调，这种解调方式不需要对本振光进行精确的锁相控制，但是对DSP和ADC的处理速度要求较高。不利于接收装置的小型化、轻量化。Prior art [1] (Sun Jianfeng, Xu Mengmeng, Zhang Bo, et al. Free-space coherent optical communication detection device based on 2X4 90° optical bridge: CN105634591A.2016) It is proposed to use VCO to perform sideband modulation on the local oscillator light to improve the local oscillator Control bandwidth of light. This method can increase the closed-loop bandwidth of the optical phase-locked loop to around 600KHz, but this type of local oscillator optical control method is more complicated and has low optical efficiency. Prior art [2] (Xu Jian, Huang Liyan, He Guoliang, et al. A carrier phase estimation method in a coherent optical receiving device: CN105763265A.2016) proposes to use the carrier phase estimation method in the digital domain for signal demodulation, which is This demodulation method does not require precise phase-locking control of the local oscillator light, but requires high processing speed of DSP and ADC. It is not conducive to the miniaturization and weight reduction of the receiving device.

为了解决高速率下锁相误差信号的提取以及简化本振光的控制方式问题，我们开展了基于欠采样的数模混合式光学锁相环系统装置，这将对高速率、高灵敏度的零差相干解调具有非常重要的意义。In order to solve the problem of extracting the phase-locked error signal at high speed and simplifying the control method of the local oscillator, we have developed a digital-analog hybrid optical phase-locked loop system device based on undersampling, which will provide high-speed, high-sensitivity homodyne Coherent demodulation is very important.

发明内容SUMMARY OF THE INVENTION

本发明主要针对高速高灵敏度的零差相干解调激光通信系统，提出了一种基于欠采样的数模混合式光学锁相环系统。本系统可以快速实现光学锁相和信号解调。The invention mainly aims at the high-speed and high-sensitivity homodyne coherent demodulation laser communication system, and proposes a digital-mode hybrid optical phase-locked loop system based on undersampling. The system can quickly realize optical phase locking and signal demodulation.

本发明的技术解决方案如下：The technical solution of the present invention is as follows:

一种基于欠采样的数模混合式光学锁相环系统，其特点在于：该系统包括第一激光器、IQ调制器、第一驱动器、第二驱动器、第一分束器、IQ偏压控制器、可调衰减器、第二分束器、光学放大器、光功率计、90度光学桥接器、第一探测器、第二探测器、第三探测器、第四探测器、电学放大器、ADC、FPGA、第一DAC、激光器外调制单元、第二DAC、第二激光器、限幅放大器和误码仪，上述元部件的位置关系如下：A digital-analog hybrid optical phase-locked loop system based on subsampling, characterized in that the system includes a first laser, an IQ modulator, a first driver, a second driver, a first beam splitter, and an IQ bias controller , adjustable attenuator, second beam splitter, optical amplifier, optical power meter, 90-degree optical bridge, first detector, second detector, third detector, fourth detector, electrical amplifier, ADC, FPGA, the first DAC, the laser external modulation unit, the second DAC, the second laser, the limiting amplifier and the bit error detector, the positional relationship of the above components is as follows:

所述的第一激光器的输出端与所述的IQ调制器的1输入端相连，该IQ调制器的输出端与所述的第一分束器的输入端相连，该第一分束器将入射光分为两路：一路经所述的可调衰减器进入第二分束器，另一路进入所述的IQ偏压控制器的输入端，该IQ偏压控制器的1、2、3输出端分别与所述的IQ调制器的4、5、6输入端相连；The output end of the first laser is connected with the input end 1 of the IQ modulator, the output end of the IQ modulator is connected with the input end of the first beam splitter, and the first beam splitter will The incident light is divided into two paths: one path enters the second beam splitter through the adjustable attenuator, and the other path enters the input end of the IQ bias controller. 1, 2, and 3 of the IQ bias controller The output ends are respectively connected with the 4, 5, and 6 input ends of the IQ modulator;

所述的第二分束器将入射光分为两路：一路供所述的光功率计检测，另一路经所述的光学放大器放大后输入所述的90度光学桥接器的1输入端，该90度光学桥接器的1、2、3、4输出端的输出分别供所述的第一探测器、第二探测器、第三探测器、第四探测器探测，所述的第一探测器、第二探测器的输出端分别与所述的限幅放大器的1、2输入端相连，该限幅放大器的1、2输出端分别与所述的误码仪的 1、2输入端相连，该误码仪的1、2输出端分别经所述的第一驱动器、第二驱动器与所述的IQ调制器的2、3输入端相连，所述的第三探测器、第四探测器的输出端分别与所述的电学放大器的1、2输入端相连，该电学放大器的1、2输出端与所述的ADC的1、2输入端相连，该ADC的1、2输出端与所述的FPGA的1、2输入端相连，该FPGA的1输出端经所述的第一DAC输入所述的激光器外调制单元的1输入端，所述的FPGA的2输出端经所述的第二DAC与所述的第二激光器的控制端相连，该第二激光器的输出端与所述的激光器外调制单元的2输入端相连，所述的激光器外调制单元的输出端与所述的90度光学桥接器的2输入端相连。The second beam splitter divides the incident light into two paths: one path is used for detection by the optical power meter, and the other path is amplified by the optical amplifier and then input to the input end 1 of the 90-degree optical bridge, The outputs of the 1, 2, 3, and 4 output ends of the 90-degree optical bridge are respectively used for detection by the first detector, the second detector, the third detector, and the fourth detector, and the first detector , The output ends of the second detector are respectively connected with the input ends 1 and 2 of the limiting amplifier, and the output ends 1 and 2 of the limiting amplifier are respectively connected with the input ends 1 and 2 of the BER, respectively. The output ends 1 and 2 of the bit error detector are respectively connected to the input ends 2 and 3 of the IQ modulator through the first driver and the second driver. The output terminals are respectively connected with the input terminals 1 and 2 of the electrical amplifier, the output terminals 1 and 2 of the electrical amplifier are connected with the input terminals 1 and 2 of the ADC, and the output terminals 1 and 2 of the ADC are connected with the input terminals 1 and 2 of the ADC. The 1 and 2 input ends of the FPGA are connected, the 1 output end of the FPGA is input to the 1 input end of the laser external modulation unit through the described first DAC, and the 2 output end of the FPGA is passed through the described second. The DAC is connected to the control end of the second laser, the output end of the second laser is connected to the 2 input ends of the laser external modulation unit, and the output end of the laser external modulation unit is 90 degrees from the The 2 inputs of the optical bridge are connected.

本发明的工作过程是：The working process of the present invention is:

在信号光的发射端，所述的第一驱动器和第二驱动器将误码仪产生的两路高速电信号放大后经IQ调制器将该电信号加载到第一激光器输出的信号光上，第一分束器用于将调制后的信号光分成两路，其中一路输入到IQ偏压控制器中以反馈控制IQ调制器偏压点；另外一路输入到可调衰减器中，用于实时调节发射端的光功率。其中，第二分束器将经过可调衰减器输出的光分出两路，其中一路输入到光功率计中，用于实时监测光功率；另外一路信号光经过光学放大器放大后，入射到接收端。At the transmitting end of the signal light, the first driver and the second driver amplify the two high-speed electrical signals generated by the bit error detector and then load the electrical signals onto the signal light output by the first laser through the IQ modulator. A beam splitter is used to divide the modulated signal light into two paths, one of which is input to the IQ bias controller to feedback control the bias point of the IQ modulator; the other is input to the adjustable attenuator for real-time adjustment of the emission optical power at the end. Among them, the second beam splitter splits the light outputted by the adjustable attenuator into two channels, one of which is input to the optical power meter for real-time monitoring of the optical power; the other channel of signal light is amplified by the optical amplifier and incident to the receiving end.

在信号的接收端，所述的90度光学桥接器将经光学放大器放大后的信号光和本振光进行相位分集接收，第一探测器、第二探测器、第三探测器和第四探测器将 90度光学桥接器输出相位差为90度的四路干涉信号转换为对应的电信号。第三探测器和第四探测器输出的IQ两路信号经过电学放大器放大后，通过ADC转换为对应的数字信号。FPGA根据ADC输出的数字信号提取出相应的误差信号，该误差信号依次经过第一DAC和激光器外调制单元，用于将该误差信号转换为模拟信号并加载到第二激光器输出的本振光上，形成光学锁相环的闭环控制。At the receiving end of the signal, the 90-degree optical bridge performs phase diversity reception on the signal light and the local oscillator light amplified by the optical amplifier, and the first detector, the second detector, the third detector and the fourth detector The device converts the four-way interference signals with a phase difference of 90 degrees output by the 90-degree optical bridge into corresponding electrical signals. The IQ two-way signals output by the third detector and the fourth detector are amplified by an electrical amplifier and then converted into corresponding digital signals by an ADC. The FPGA extracts the corresponding error signal according to the digital signal output by the ADC. The error signal passes through the first DAC and the laser external modulation unit in turn, and is used to convert the error signal into an analog signal and load it onto the local oscillator light output by the second laser. , forming the closed-loop control of the optical phase-locked loop.

所述的FPGA主要完成四次方查找表、数字环路滤波器以及DDS的功能。其中，四次方查找表根据输入的IQ两路信号提取出相位误差信号；数字环路滤波器对提取出的相位误差信号进行PID算法处理；将经PID算法处理后的信号输入到DDS中，生成频率和相位均受控的信号。The FPGA mainly completes the functions of a quadratic look-up table, a digital loop filter and a DDS. Among them, the quadratic look-up table extracts the phase error signal according to the input IQ two-way signal; the digital loop filter performs PID algorithm processing on the extracted phase error signal; the signal processed by the PID algorithm is input into the DDS, Generates a frequency and phase controlled signal.

所述的第二DAC根据相位误差信号控制第二激光器，进行光学锁相环路的初始捕获。光学锁相环环路稳定工作后，第一探测器和第二探测器输出的两路信号经过限幅放大器放大，放大后的信号输入到误码仪上测试系统的通信灵敏度和误码率。The second DAC controls the second laser according to the phase error signal to perform initial capture of the optical phase-locked loop. After the optical phase-locked loop loop works stably, the two-way signals output by the first detector and the second detector are amplified by the limiting amplifier, and the amplified signals are input to the bit error tester to test the communication sensitivity and bit error rate of the system.

本发明的优点在于如下：The advantages of the present invention are as follows:

1、接收端采用零差相干探测的方式，可以达到近散粒噪声极限的通信灵敏速度。同时，通过欠采样相位误差信号解算的方式解决高速率相干接收时因电子学带宽受限而无法提取相位误差信号的难题。1. The receiving end adopts the method of homodyne coherent detection, which can achieve the communication sensitivity speed close to the shot noise limit. At the same time, the problem that the phase error signal cannot be extracted due to the limited electronic bandwidth during high-rate coherent reception is solved by solving the under-sampling phase error signal.

2、该装置通过单个FPGA实现四次方查找表、数字PID算法的环路滤波器和DDS 的功能，具备失锁后自动重新锁定的功能。减小了稳态下的锁相误差以及对激光器线宽的要求。2. The device realizes the functions of the quadratic look-up table, the loop filter of the digital PID algorithm and the DDS through a single FPGA, and has the function of automatically re-locking after losing lock. The phase-locking error in steady state and the requirement for laser linewidth are reduced.

3、该装置采用本振激光器外调制的方式，避免了直接调制本振光时带宽受限的问题，提高了锁相环路的控制带宽。简化了本振光的控制方式，有效的保证了锁相环的可靠性。3. The device adopts the external modulation method of the local oscillator laser, which avoids the problem of limited bandwidth when directly modulating the local oscillator light, and improves the control bandwidth of the phase-locked loop. The control mode of the local oscillator light is simplified, and the reliability of the phase-locked loop is effectively guaranteed.

4、该装置采用初始环路捕获的辅助环路。同时，在环路锁定后及时对误差信号进行卸载，提高了对信号光频率变化的容忍度。避免了由于信号光频率大范围漂移造成的锁相环路失锁。4. The device adopts the auxiliary loop captured by the initial loop. At the same time, the error signal is unloaded in time after the loop is locked, which improves the tolerance to the frequency variation of the signal light. The loss of phase-locked loop caused by the large-scale drift of the signal light frequency is avoided.

5、该装置的光学锁相电路设计简单，可兼容BPSK/QPSK等高阶调制的零差相干接收。5. The optical phase-locked circuit of the device has a simple design and is compatible with homodyne coherent reception of high-order modulation such as BPSK/QPSK.

附图说明Description of drawings

图1为本发明基于欠采样的数模混合式光学锁相环系统的结构框图。FIG. 1 is a structural block diagram of a digital-analog hybrid optical phase-locked loop system based on subsampling of the present invention.

图中：1—第一激光器、2—IQ调制器、3—第一驱动器、4—第二驱动器、5—第一分束器、6—IQ偏压控制器、7—可调衰减器、8—第二分束器、9—光学放大器、 10—光功率计、11—90度光学桥接器、12—第一探测器、13—第二探测器、14—第三探测器、15—第四探测器、16—电学放大器、17—ADC、18—FPGA、19—第一DAC、 20—激光器外调制单元、21—第二DAC、22—第二激光器、23—限幅放大器、24—误码仪、In the figure: 1—first laser, 2—IQ modulator, 3—first driver, 4—second driver, 5—first beam splitter, 6—IQ bias controller, 7—adjustable attenuator, 8—Second beam splitter, 9—Optical amplifier, 10—Optical power meter, 11—90 degree optical bridge, 12—First detector, 13—Second detector, 14—Third detector, 15— Fourth detector, 16—electrical amplifier, 17—ADC, 18—FPGA, 19—first DAC, 20—laser external modulation unit, 21—second DAC, 22—second laser, 23—limiting amplifier, 24 - bit error meter,

具体实施方式Detailed ways

下面结合实施案例和附图对本发明作进一步说明，但不应以此限制本发明的保护范围。The present invention will be further described below with reference to the examples and accompanying drawings, but the protection scope of the present invention should not be limited by this.

请参阅图1，图1是本发明基于欠采样的数模混合式光学锁相环系统的结构框图，实线部分为电信号的连接，虚线部分为光信号的相连。由图可见，本发明基于欠采样的数模混合式光学锁相环系统，包括第一激光器1、IQ调制器2、第一驱动器3、第二驱动器4、第一分束器5、IQ偏压控制器6、可调衰减器7、第二分束器8、光学放大器9、光功率计10、90度光学桥接器11、第一探测器12、第二探测器13、第三探测器14、第四探测器15、电学放大器16、ADC17、FPGA18、第一 DAC19、激光器外调制单元20、第二DAC21、第二激光器22、限幅放大器23和误码仪24，上述元部件的位置关系如下：Please refer to FIG. 1. FIG. 1 is a structural block diagram of a digital-analog hybrid optical phase-locked loop system based on undersampling of the present invention. The solid line part is the connection of electrical signals, and the dotted line part is the connection of optical signals. As can be seen from the figure, the present invention is based on an under-sampling digital-analog hybrid optical phase-locked loop system, including a first laser 1, an IQ modulator 2, a first driver 3, a second driver 4, a first beam splitter 5, an IQ offset Voltage controller 6, adjustable attenuator 7, second beam splitter 8, optical amplifier 9, optical power meter 10, 90-degree optical bridge 11, first detector 12, second detector 13, third detector 14. The fourth detector 15, the electrical amplifier 16, the ADC17, the FPGA18, the first DAC19, the laser external modulation unit 20, the second DAC21, the second laser 22, the limiting amplifier 23 and the BER 24, the positions of the above components The relationship is as follows:

所述的第一激光器1的输出端与所述的IQ调制器2的1输入端相连，该IQ调制器2的输出端与所述的第一分束器5的输入端相连，该第一分束器5将入射光分为两路：一路经所述的可调衰减器7进入第二分束器8，另一路进入所述的IQ 偏压控制器6的输入端，该IQ偏压控制器6的1、2、3输出端分别与所述的IQ调制器2的4、5、6输入端相连；The output end of the first laser 1 is connected to the input end 1 of the IQ modulator 2, the output end of the IQ modulator 2 is connected to the input end of the first beam splitter 5, and the first The beam splitter 5 divides the incident light into two paths: one path enters the second beam splitter 8 through the adjustable attenuator 7, and the other path enters the input end of the IQ bias controller 6, the IQ bias voltage The output ends 1, 2 and 3 of the controller 6 are respectively connected with the input ends 4, 5 and 6 of the IQ modulator 2;

所述的第二分束器8将入射光分为两路：一路输出光供所述的光功率计10检测，另一路输出光经所述的光学放大器9放大后输入所述的90度光学桥接器11的 1输入端，该90度光学桥接器11的1、2、3、4输出端分别供所述的第一探测器12、第二探测器13、第三探测器14、第四探测器15探测，所述的第一探测器12、第二探测器13的输出端分别与所述的限幅放大器23的1、2输入端相连，该限幅放大器23的1、2输出端分别与所述的误码仪24的1、2输入端相连，该误码仪24 的1、2输出端分别经所述的第一驱动器3、第二驱动器4与所述的IQ调制器2的 2、3输入端相连，所述的第三探测器14、第四探测器15的输出端分别与所述的电学放大器16的1、2输入端相连，该电学放大器16的1、2输出端与所述的ADC17 的1、2输入端相连，该ADC17的1、2输出端与所述的FPGA18的1、2输入端相连，该FPGA18的1输出端经所述的第一DAC19输入所述的激光器外调制单元20的1输入端，所述的FPGA18的2输出端经所述的第二DAC21与所述的第二激光器22的控制端相连，该第二激光器22的输出端与所述的激光器外调制单元20的2输入端相连，所述的激光器外调制单元20的输出端与所述的90度光学桥接器11的2输入端相连。The second beam splitter 8 divides the incident light into two paths: one output light is detected by the optical power meter 10, and the other output light is amplified by the optical amplifier 9 and then input to the 90-degree optical fiber. The 1 input end of the bridge 11, the 1, 2, 3, and 4 output ends of the 90-degree optical bridge 11 are respectively used for the first detector 12, the second detector 13, the third detector 14, the fourth detector The detector 15 detects, the output ends of the first detector 12 and the second detector 13 are respectively connected to the input ends 1 and 2 of the limiting amplifier 23, and the output ends 1 and 2 of the limiting amplifier 23 They are respectively connected with the input ends 1 and 2 of the bit error detector 24, and the output ends 1 and 2 of the bit error detector 24 are respectively connected to the IQ modulator 2 through the first driver 3, the second driver 4 and the IQ modulator 2. The 2 and 3 input terminals are connected, the output terminals of the third detector 14 and the fourth detector 15 are respectively connected with the 1 and 2 input terminals of the electrical amplifier 16, and the 1 and 2 output terminals of the electrical amplifier 16 are respectively connected. The terminal is connected to the input terminals 1 and 2 of the ADC17, the output terminals 1 and 2 of the ADC17 are connected to the input terminals 1 and 2 of the FPGA18, and the output terminal 1 of the FPGA18 is input through the first DAC19. The 1 input end of the laser external modulation unit 20, the 2 output end of the described FPGA 18 are connected with the control end of the second laser 22 through the second DAC21, and the output end of the second laser 22 is connected to the control end of the second laser 22. The two input ends of the external laser modulation unit 20 are connected to each other, and the output end of the external laser modulation unit 20 is connected to the two input ends of the 90-degree optical bridge 11 .

在信号光的发射端，所述的第一驱动器3和第二驱动器4将误码仪24产生的两路高速电信号放大后经IQ调制器2将该电信号加载到第一激光器1上。第一分束器5用于将调制后的信号光分成两路，其中一路输入到IQ偏压控制器6中以反馈控制IQ调制器2的偏压点；另外一路输入到可调衰减器7中，用于实时调节发射端的光功率。其中，第二分束器8将经过可调衰减器7输出的光分出两路，其中一路输入到光功率计10中，用于实时监测光功率；另外一路信号光经过光学放大器9放大后，入射到接收端。At the transmitting end of the signal light, the first driver 3 and the second driver 4 amplify the two high-speed electrical signals generated by the bit error detector 24 and load the electrical signals onto the first laser 1 through the IQ modulator 2 . The first beam splitter 5 is used to divide the modulated signal light into two paths, one of which is input to the IQ bias voltage controller 6 to feedback control the bias point of the IQ modulator 2; the other path is input to the adjustable attenuator 7 is used to adjust the optical power of the transmitter in real time. The second beam splitter 8 splits the light outputted by the adjustable attenuator 7 into two paths, one of which is input into the optical power meter 10 for real-time monitoring of the optical power; the other path of signal light is amplified by the optical amplifier 9 , incident on the receiving end.

在信号的接收端，所述的90度光学桥接器11将经光学放大器9放大后的信号光和本振光进行相位分集接收，第一探测器12、第二探测器13、第三探测器14和第四探测器15将90度光学桥接器11输出相位差为90度的四路干涉信号转换为对应的电信号。其中，第三探测器14和第四探测器15输出的IQ两路信号经过第一电学放大器16放大后，通过ADC17转换为对应的数字信号。FPGA18根据ADC输出的数字信号提取出相应的相位误差信号。第一DAC19将误差信号转化为模拟信号，通过激光器外调制单元20将FPGA产生的相位误差信号加载到第二激光器22产生调制光信号，形成光学锁相环的闭环控制。At the receiving end of the signal, the 90-degree optical bridge 11 performs phase diversity reception on the signal light and the local oscillator light amplified by the optical amplifier 9. The first detector 12, the second detector 13, the third detector 14 and the fourth detector 15 convert the four-way interference signals output by the 90-degree optical bridge 11 with a phase difference of 90 degrees into corresponding electrical signals. The IQ two-channel signals output by the third detector 14 and the fourth detector 15 are amplified by the first electrical amplifier 16 and then converted into corresponding digital signals by the ADC 17 . The FPGA18 extracts the corresponding phase error signal according to the digital signal output by the ADC. The first DAC 19 converts the error signal into an analog signal, and loads the phase error signal generated by the FPGA to the second laser 22 through the laser external modulation unit 20 to generate a modulated optical signal to form a closed-loop control of the optical phase-locked loop.

所述的FPGA11主要完成四次方查找表、数字环路滤波器以及DDS的功能。其中，四次方查找表根据输入的IQ两路信号提取出相位误差信号；数字环路滤波器对提取出的相位误差信号进行PID算法处理；将经PID算法处理后的信号输入到DDS 中，生成频率和相位均受控的信号。The FPGA11 mainly completes the functions of the quadratic look-up table, the digital loop filter and the DDS. Among them, the quadratic look-up table extracts the phase error signal according to the input IQ two-way signal; the digital loop filter performs PID algorithm processing on the extracted phase error signal; the signal processed by the PID algorithm is input into the DDS, Generates a frequency and phase controlled signal.

所述的第二DAC21根据相位误差信号控制第二激光器22，进行光学锁相环路的初始捕获。光学锁相环环路稳定工作后，第一探测器11和第二探测器12输出的两路信号经过限幅放大器23放大，放大后的信号输入到误码仪24上测试系统的通信灵敏度和误码率。The second DAC 21 controls the second laser 22 according to the phase error signal to perform initial capture of the optical phase-locked loop. After the optical phase-locked loop loop works stably, the two-way signals output by the first detector 11 and the second detector 12 are amplified by the limiting amplifier 23, and the amplified signals are input to the bit error tester 24 to test the communication sensitivity and bit error rate.

本发明一种基于欠采样的数模混合式光学锁相环系统工作时,具体操作步骤如下：When an undersampling-based digital-analog hybrid optical phase-locked loop system of the present invention works, the specific operation steps are as follows:

1)第三探测器(14)和第四探测器(15)将90度光学桥接器(11)输出IQ两路信号转换为对应的电信号V_I(t)和V_Q(t)：1) The third detector (14) and the fourth detector (15) convert the output IQ signals of the 90-degree optical bridge (11) into corresponding electrical signals V _I (t) and V _Q (t):

其中，R和R_L表示探测器的响应度和夸阻阻值；P_S和P_L表示信号光功率和本振光功率；

和

表示信号光相位噪声和本振光相位；θ(t)代表调制信号相位，对于QPSK调制θ(t)＝0,π/2,π,3π/2,对于BPSK调制θ(t)＝0,π。Among them, R and _RL represent the responsivity and resistance of the detector; P _S and _PL represent the optical power of the signal and the optical power of the local oscillator;

and

Represents the signal optical phase noise and the local oscillator optical phase; θ(t) represents the modulation signal phase, for QPSK modulation θ(t)=0, π/2, π, 3π/2, for BPSK modulation θ(t)=0, pi.

2)将第三探测器14、第四探测器15输出的IQ两路信号经过ADC(17)转换为相应的数字信号，两路信号进行同步采样，采样率为2GHz。采样的后电信号V_I(t)和 V_Q(t)：2) The IQ two-way signals output by the third detector 14 and the fourth detector 15 are converted into corresponding digital signals through ADC (17), and the two-way signals are sampled synchronously, and the sampling rate is 2GHz. Sampled post electrical signals V _I (t) and V _Q (t):

3)FPGA(18)首先采用四次方查找表从IQ两路数字信号中提取出相位误差信号 x[k]。四次方查找表对应的数学表达式为：3) FPGA (18) first extracts the phase error signal x[k] from the IQ two-channel digital signal by using a quadratic look-up table. The mathematical expression corresponding to the quadratic lookup table is:

将提取出的相位误差信号x[k]进行环路滤波处理，该环路滤波器由数字PID控制算法实现，对应的传递函数可以表达为：The extracted phase error signal x[k] is subjected to loop filter processing. The loop filter is realized by the digital PID control algorithm, and the corresponding transfer function can be expressed as:

经过环路滤波后的相位误差信号控制DDS产生频率和相位都受控的误差信号。The phase error signal after loop filtering controls the DDS to generate an error signal whose frequency and phase are controlled.

4)在第3步的四次方查找表提取相位误差信号的同时，同步解算信号光和本振光的频差，第二DAC(21)根据此频差信号直接控制本振激光器，频差不断的减小最终进入环路的捕获带中。完成锁相环路的初始捕获。4) While extracting the phase error signal from the fourth power look-up table in step 3, the frequency difference between the signal light and the local oscillator light is synchronously solved, and the second DAC (21) directly controls the local oscillator laser according to the frequency difference signal, and the frequency The ever-decreasing difference ends up in the capture band of the loop. Complete the initial acquisition of the phase-locked loop.

5)DDS输出的信号经过第一DAC(19)转换为模拟信号，激光器外调制单元(20) 根据该模拟信号对第二激光器(20)输出的本振光信号进行调制。5) The signal output by the DDS is converted into an analog signal by the first DAC (19), and the laser external modulation unit (20) modulates the local oscillator optical signal output by the second laser (20) according to the analog signal.

6)将激光器外调制单元(20)输出的光信号。输入到90度光学桥接器(11)中形成闭环。6) Externally modulate the optical signal output by the laser unit (20). The input into the 90 degree optical bridge (11) forms a closed loop.

7)锁相环路锁定后，将第一探测器(12)和第二探测器(13)输出的电信号经限幅放大器(23)放大后输入到误码仪(24)中。7) After the phase-locked loop is locked, the electrical signals output by the first detector (12) and the second detector (13) are amplified by the limiting amplifier (23) and then input into the bit error detector (24).

8)通过调节可调衰减器(7)改变输入信号光的功率，测试在不同输入信号光功率下对应的误码率。8) Change the power of the input signal light by adjusting the adjustable attenuator (7), and test the corresponding bit error rate under different input signal light powers.

1. The utility model provides a digital analog hybrid optics phase-locked loop system based on undersampling which characterized in that: the optical power amplifier comprises a first laser (1), an IQ modulator (2), a first driver (3), a second driver (4), a first beam splitter (5), an IQ bias controller (6), an adjustable attenuator (7), a second beam splitter (8), an optical amplifier (9), an optical power meter (10), a 90-degree optical bridge (11), a first detector (12), a second detector (13), a third detector (14), a fourth detector (15), an electrical amplifier (16), an ADC (17), an FPGA (18), a first DAC (19), an external laser modulation unit (20), a second DAC (21), a second laser (22), a limiting amplifier (23) and an error code meter (24), wherein the position relations of the components are as follows:

the output end of the first laser (1) is connected with the input end 1 of the IQ modulator (2), the output end of the IQ modulator (2) is connected with the input end of the first beam splitter (5), and the first beam splitter (5) divides incident light into two paths: one path enters a second beam splitter (8) through the adjustable attenuator (7), the other path enters the input end of the IQ bias controller (6), and the output ends 1, 2 and 3 of the IQ bias controller (6) are respectively connected with the input ends 4, 5 and 6 of the IQ modulator (2);

the second beam splitter (8) splits incident light into two paths: one path is used for detection of the optical power meter (10), the other path is amplified by the optical amplifier (9) and then input to the input end 1 of the 90-degree optical bridge (11), the output ends 1, 2, 3 and 4 of the 90-degree optical bridge (11) are respectively used for detection of the first detector (12), the second detector (13), the third detector (14) and the fourth detector (15), the output ends 1 and 2 of the first detector (12) and the second detector (13) are respectively connected with the input ends 1 and 2 of the limiting amplifier (23), the output ends 1 and 2 of the limiting amplifier (23) are respectively connected with the input ends 1 and 2 of the error code meter (24), and the output ends 1 and 2 of the error code meter (24) are respectively connected with the input end 2 of the IQ modulator (2) through the first driver (3) and the second driver (4), 3, the output ends of the third detector (14) and the fourth detector (15) are respectively connected with the input ends of the electrical amplifier (16)1 and the electrical amplifier 2, the 1, 2 output ends of the electrical amplifier (16) are connected with the 1, 2 input ends of the ADC (17), the 1 and 2 output ends of the ADC (17) are connected with the 1 and 2 input ends of the FPGA (18), the 1 output end of the FPGA (18) is input into the 1 input end of the laser external modulation unit (20) through the first DAC (19), the 2 output end of the FPGA (18) is connected with the control end of the second laser (22) through the second DAC (21), the output end of the second laser (22) is connected with the 2 input end of the laser external modulation unit (20), and the output end of the laser external modulation unit (20) is connected with the 2 input end of the 90-degree optical bridge (11).