CN111261609A - Semiconductor device and method of making the same - Google Patents
- ️Tue Jun 09 2020
技术领域technical field
本发明一般涉及半导体器件领域，且更具体地涉及一种半导体器件的封装结构及其制备方法。The present invention generally relates to the field of semiconductor devices, and more particularly, to a packaging structure of a semiconductor device and a method for manufacturing the same.
背景技术Background technique
在制作晶片的过程中，会先在半导体晶片中的半导体基底的表面形成集成电路元件(例如晶体管)。之后，在集成电路元件上形成内连线结构 (interconnect structure)。在半导体晶片的表面上形成导电元件，且这些导电元件电性耦接至集成电路元件。将半导体晶片切割成多个半导体芯片，也就是俗称的裸片(dies)。During wafer fabrication, integrated circuit elements (eg, transistors) are first formed on the surface of a semiconductor substrate in a semiconductor wafer. Thereafter, an interconnect structure is formed on the integrated circuit element. Conductive elements are formed on the surface of the semiconductor wafer and are electrically coupled to integrated circuit elements. The semiconductor wafer is diced into a plurality of semiconductor chips, commonly known as dies.
在半导体芯片的封装工艺中，半导体芯片时常使用倒装芯片接合与封装基板相连。焊料用以使半导体芯片中的导电元件连结至封装基底中的结合垫 (bond pads)。在接合两个半导体芯片(或是一个半导体芯片与一个封装基底) 时，可以将焊料预先形成在前述两个半导体芯片其中之一的导电元件/结合垫上、或者是同时形成在前述两个半导体芯片的导电元件/结合垫上。之后，进行一回焊(re-flow)工艺以使焊料连接半导体芯片。在回焊工艺中，焊料会出现爬锡(solder creeping)现象，造成锡量不足导致不沾锡(non-wetting)的问题或焊料量太多导致焊桥问题，从而影响产品的良率.In the packaging process of semiconductor chips, the semiconductor chips are often connected to the packaging substrate using flip-chip bonding. Solder is used to connect conductive elements in semiconductor chips to bond pads in package substrates. When bonding two semiconductor chips (or a semiconductor chip and a package substrate), solder may be pre-formed on the conductive elements/bond pads of one of the two semiconductor chips, or formed on both the semiconductor chips simultaneously on the conductive elements/bond pads. After that, a re-flow process is performed to connect the semiconductor chips with solder. In the reflow process, the solder will have a phenomenon of solder creeping, which will cause the problem of non-wetting due to insufficient amount of tin or the problem of solder bridge due to too much solder, thus affecting the yield of the product.
发明内容SUMMARY OF THE INVENTION
为了克服上述缺陷，本发明提供一种半导体器件及其形成方法。In order to overcome the above drawbacks, the present invention provides a semiconductor device and a method for forming the same.
本发明一方面提供一种半导体器件，包括：衬底，一表面上具有结合垫；导电体，凸出于所述结合垫且与所述结合垫连接；及所述导电体顶面设有焊料层以及环绕所述焊料层的第一阻挡层，所述焊料层凸出于所述第一阻挡层。One aspect of the present invention provides a semiconductor device, comprising: a substrate with a bonding pad on one surface; a conductor protruding from the bonding pad and connected to the bonding pad; and a solder provided on the top surface of the conductor layer and a first barrier layer surrounding the solder layer, the solder layer protruding from the first barrier layer.
根据本发明的一实施方式，所述焊料层的凸出高度大于等于所述第一阻挡层高度的10％。According to an embodiment of the present invention, the protruding height of the solder layer is greater than or equal to 10% of the height of the first barrier layer.
根据本发明的另一实施方式，所述导电体和所述结合垫通过凸块下金属化层连接。According to another embodiment of the present invention, the electrical conductors and the bonding pads are connected through an under-bump metallization layer.
根据本发明的另一实施方式，所述凸块下金属化层呈U型包覆所述导电体并露出所述导电体的顶面。According to another embodiment of the present invention, the under-bump metallization layer wraps the conductor in a U-shape and exposes the top surface of the conductor.
根据本发明的另一实施方式，所述凸块下金属化层与所述第一阻挡层接触连接。According to another embodiment of the present invention, the under-bump metallization layer is in contact with the first barrier layer.
根据本发明的另一实施方式，所述导电体和所述焊料层之间还包括第二阻挡层，所述第二阻挡层覆盖所述导电体顶面并与所述第一阻挡层接触连接。According to another embodiment of the present invention, a second barrier layer is further included between the electrical conductor and the solder layer, the second barrier layer covers the top surface of the electrical conductor and is in contact with the first barrier layer .
根据本发明的另一实施方式，所述导电体包括铜、钨、金中的一种或多种。According to another embodiment of the present invention, the electrical conductor includes one or more of copper, tungsten, and gold.
根据本发明的另一实施方式，所述第一阻挡层包括Ni。According to another embodiment of the present invention, the first barrier layer includes Ni.
根据本发明的另一实施方式，所述第二阻挡层包括Ti、Ta、TiW、Al、 Cr、NiCr中的一种或多种。According to another embodiment of the present invention, the second barrier layer includes one or more of Ti, Ta, TiW, Al, Cr, and NiCr.
本发明另一方面提供一种形成半导体器件的方法，包括：形成导电体于半导体器件的表面上的结合垫上且与所述结合垫连接；以及形成与所述导电体顶面连接的焊料层和环绕所述焊料层的第一阻挡层，所述焊料层凸出于所述第一阻挡层。Another aspect of the present invention provides a method of forming a semiconductor device, comprising: forming electrical conductors on bonding pads on a surface of the semiconductor device and connecting to the bonding pads; and forming a solder layer connected to a top surface of the electrical conductors and A first barrier layer surrounding the solder layer, the solder layer protruding from the first barrier layer.
根据本发明的一实施方式，所述焊料层的凸出高度大于等于所述第一阻挡层高度的10％。According to an embodiment of the present invention, the protruding height of the solder layer is greater than or equal to 10% of the height of the first barrier layer.
根据本发明的另一实施方式，所述方法还包括：将所述导电体与所述结合垫连接之前，在所述结合垫上形成U形凸块下金属化层；及在所述U形凸块下金属化层中形成所述导电体，并露出所述导电体顶面。According to another embodiment of the present invention, the method further includes: forming a U-bump under-bump metallization layer on the bonding pad before connecting the electrical conductor with the bonding pad; and forming a U-shaped bump metallization layer on the U-shaped bump The electrical conductor is formed in the under-block metallization layer, and the top surface of the electrical conductor is exposed.
根据本发明的另一实施方式，所述方法还包括：在所述导电体顶面形成第二阻挡层；在所述第二阻挡层上形成所述第一阻挡层；及在所述第一阻挡层中形成所述焊料层。According to another embodiment of the present invention, the method further includes: forming a second barrier layer on the top surface of the electrical conductor; forming the first barrier layer on the second barrier layer; and forming the first barrier layer on the first barrier layer The solder layer is formed in the barrier layer.
根据本发明的另一实施方式，所述凸块下金属化层与所述第一阻挡层接触连接。According to another embodiment of the present invention, the under-bump metallization layer is in contact with the first barrier layer.
根据本发明的另一实施方式，所述导电体包括铜。According to another embodiment of the present invention, the electrical conductor comprises copper.
根据本发明的另一实施方式，所述第一阻挡层包括Ni。According to another embodiment of the present invention, the first barrier layer includes Ni.
根据本发明的另一实施方式，所述第二阻挡层包括Ti、Ta。According to another embodiment of the present invention, the second barrier layer includes Ti and Ta.
本发明通过在焊料的外表面包覆环状阻挡层，减少了回焊工艺中由于焊料会出现爬锡造成锡量不足而导致的不沾锡的缺陷或焊料量太多导致焊桥缺陷，从而提高产品的良率。By covering the outer surface of the solder with a ring-shaped barrier layer, the invention reduces the defects of non-sticking due to insufficient tin amount due to the solder creeping up during the reflow process, or the solder bridge defects caused by too much solder, thereby reducing Improve product yield.
附图说明Description of drawings
通过参照附图详细描述其示例实施方式，本发明的上述和其它特征及优点将变得更加明显。The above and other features and advantages of the present invention will become more apparent from the detailed description of example embodiments thereof with reference to the accompanying drawings.
图1是本发明一实施例的半导体器件的示意图。FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.
图2是本发明另一实施例的半导体器件的示意图。FIG. 2 is a schematic diagram of a semiconductor device according to another embodiment of the present invention.
图3A-3G是本发明又一实施例的半导体器件的形成流程图。3A-3G are flowcharts of forming a semiconductor device according to yet another embodiment of the present invention.
图4是现有技术的半导体器件的示意图。FIG. 4 is a schematic diagram of a prior art semiconductor device.
其中，附图标记说明如下：Among them, the reference numerals are described as follows:
1：衬底1: Substrate
2：结合垫2: Binding pad
3：钝化层3: Passivation layer
31：聚合物层31: Polymer layer
4：第一间隔层4: The first spacer layer
5：导电金属层5: Conductive metal layer
51：UBM层51: UBM layer
6：导电体6: Conductor
7：第二阻挡层7: Second barrier layer
8：第二间隔层8: Second spacer layer
9：阻挡层9: Barrier layer
91：第一阻挡层91: First barrier layer
10：焊料层10: Solder layer
具体实施方式Detailed ways
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本发明将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中，为了清晰，夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. In the drawings, the thickness of regions and layers are exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
本文中术语“半导体器件”通常是指包含一或多个半导体材料的固态装置。术语“半导体器件”可指成品装置或指在成为成品装置之前的各个处理阶段处的组合件或其它结构。取决于其中使用术语“衬底”的上下文，所述术语可指晶片级衬底或指经单个化裸片级衬底。相关领域的技术人员将认识到，可以晶片级或以裸片级执行本文中所描述的方法的适合步骤。The term "semiconductor device" herein generally refers to a solid state device comprising one or more semiconductor materials. The term "semiconductor device" may refer to a finished device or to an assembly or other structure at various stages of processing prior to becoming a finished device. Depending on the context in which the term "substrate" is used, the term may refer to a wafer-level substrate or to a singulated die-level substrate. Those skilled in the relevant art will recognize that suitable steps of the methods described herein may be performed at the wafer level or at the die level.
本文中术语“连接”应做广义理解，例如，可以是直接相连，也可以间接相连。对于本领域的普通技术人员而言，可视具体情况理解上述术语在本发明中的具体含义。而术语“接触连接”是指直接相连。The term "connected" herein should be understood in a broad sense, for example, it may be directly connected or indirectly connected. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific conditions. And the term "contact connection" refers to direct connection.
本文中“上”、“下”等用语，仅为了便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系，而不应该认为是具有限制性的。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述可以同样地作相应的解释。Terms such as "upper", "lower" and the like herein are only used to facilitate describing the relationship of one element or component to another (or other) elements or components as shown in the figures, and should not be considered limiting. In addition to the orientation shown in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.
本文中“第一”、“第二”等类似用语，并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。Terms such as "first", "second" and the like herein do not denote any order, quantity, or importance, but are only used to distinguish different components.
如图1所示，本发明一实施例的半导体器件包括衬底1、结合垫2、导电体6、焊料层10和第一阻挡层91。As shown in FIG. 1 , a semiconductor device according to an embodiment of the present invention includes a substrate 1 , a bonding pad 2 , a conductor 6 , a solder layer 10 and a first barrier layer 91 .
衬底1例如可以是硅晶圆或含硅材料层，也可以是集成电路器件的顶层，诸如顶部金属层、钝化层等。正如本领域已知，集成电路(未示出)形成在衬底1上面和/或内部。出于清楚的目的，可以从附图中省略衬底1的各层和各个部件(包括晶体管、互连层、钝化后互连件、再分布层等)，这是因为它们对于理解本发明是不必要的。The substrate 1 can be, for example, a silicon wafer or a layer of silicon-containing material, or a top layer of an integrated circuit device, such as a top metal layer, a passivation layer, and the like. Integrated circuits (not shown) are formed on and/or within substrate 1 as known in the art. For the sake of clarity, various layers and various components of substrate 1 (including transistors, interconnect layers, post-passivation interconnects, redistribution layers, etc.) may be omitted from the drawings as they are useful for understanding the present invention is unnecessary.
结合垫2是金属焊盘(例如，铝焊盘)，结合垫2也可以包括其他合适的金属或导电材料。The bond pads 2 are metal pads (eg, aluminum pads), and the bond pads 2 may also include other suitable metals or conductive materials.
衬底1上还可以设置有钝化层3，钝化层3是图案化的，使得钝化层3 的一部分覆盖着金属焊盘的边缘部分露出其中心部分。A passivation layer 3 may also be provided on the substrate 1, and the passivation layer 3 is patterned so that a part of the passivation layer 3 covers the edge portion of the metal pad and exposes the central portion thereof.
导电体6凸出于结合垫2上且与结合垫2连接。导电体6(也被称为凸块) 可以直接与结合垫2接触连接，也可以通过凸块下金属层(UBM层)51与结合垫2连接。导电体6可以由铜、铜合金或其他合适的材料形成。导电体 6设置在U型UBM层51内，UBM层51的开口露出导电体6的顶面。UBM 层51电连接至结合垫2。UBM层51由钛(Ti)、氮化钛(TiN)、铜镍(CuNi)、铝(Al)等形成。The conductor 6 protrudes from the bonding pad 2 and is connected to the bonding pad 2 . The conductors 6 (also referred to as bumps) can be directly contacted and connected to the bonding pads 2 , or can be connected to the bonding pads 2 through an under-bump metal layer (UBM layer) 51 . Electrical conductors 6 may be formed of copper, copper alloys, or other suitable materials. The conductor 6 is arranged in the U-shaped UBM layer 51, and the opening of the UBM layer 51 exposes the top surface of the conductor 6. The UBM layer 51 is electrically connected to the bonding pads 2 . The UBM layer 51 is formed of titanium (Ti), titanium nitride (TiN), copper nickel (CuNi), aluminum (Al), or the like.
焊料层10与导电体6顶面连接。焊料层10可以直接与导电体6接触连接，也可以通过第二阻挡层7与导电体6连接。焊料层10可以连接至另一个电器件并且经过回流以将两个器件电接合在一起。第二阻挡层7用于防止焊料层10与导电体6之间的扩散。第二阻挡层7可以由钛、钽等形成。The solder layer 10 is connected to the top surface of the conductor 6 . The solder layer 10 may be directly contacted and connected to the conductor 6 , or may be connected to the conductor 6 through the second barrier layer 7 . Solder layer 10 may be connected to another electrical device and reflowed to electrically bond the two devices together. The second barrier layer 7 is used to prevent diffusion between the solder layer 10 and the conductor 6 . The second barrier layer 7 may be formed of titanium, tantalum, or the like.
焊料层10外表面环绕第一阻挡层91，焊料层10顶部从第一阻挡层91 上端露出部分焊料。在焊料层10的外表面环绕环状阻挡层91，可以减少回焊工艺中由于焊料会出现爬锡造成锡量不足而导致的不沾锡的缺陷或焊料量太多导致焊桥缺陷，从而提高产品的良率。优选，焊料层10凸出第一阻挡层 91的高度大于等于第一阻挡层91高度的10％。第一阻挡层91可以由Ni等形成。The outer surface of the solder layer 10 surrounds the first barrier layer 91 , and the top of the solder layer 10 exposes part of the solder from the upper end of the first barrier layer 91 . Surrounding the annular barrier layer 91 on the outer surface of the solder layer 10 can reduce the defect of non-sticking caused by insufficient tin amount due to the solder creeping up during the reflow process or the solder bridge defect caused by too much solder, thereby improving the Product yield. Preferably, the height of the solder layer 10 protruding from the first barrier layer 91 is greater than or equal to 10% of the height of the first barrier layer 91 . The first barrier layer 91 may be formed of Ni or the like.
本实施例的半导体器件除以上元件外，还可以包括其他任何适当的现有元件，例如但不限于，如图2所示，在钝化层3上还设置有聚合物层31。聚合物层31具有开口，聚合物层31被图案形成开口，露出金属焊盘的一部分，使导电体6凸出于聚合物层31。聚合物层31可以包括选自于聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)和/或类似的。In addition to the above components, the semiconductor device of this embodiment may also include any other suitable existing components, for example, but not limited to, as shown in FIG. 2 , a polymer layer 31 is further provided on the passivation layer 3 . The polymer layer 31 has an opening, and the polymer layer 31 is patterned to form an opening to expose a part of the metal pad, so that the conductor 6 protrudes from the polymer layer 31 . The polymer layer 31 may comprise selected from polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO) and/or the like.
图3A至图3G是本发明一实施例的形成半导体器件的流程图。本领域技术人员可以理解，图3A至图3G仅用于解释本发明，并不意在限定本发明。3A to 3G are flowcharts of forming a semiconductor device according to an embodiment of the present invention. Those skilled in the art can understand that FIGS. 3A to 3G are only used to explain the present invention, and are not intended to limit the present invention.
如图3A所示，结合垫2形成在衬底1上。钝化层3形成在衬底1的上方。覆盖衬底1，露出下面的结合垫2。第一间隔层4形成在钝化层3上，且露出结合垫2，也就是说第一间隔层4具有露出结合垫2的沟槽。在第一间隔层4上表面、沟槽内壁面及露出的结合垫2的上表面形成导电金属层5。可以通过电镀、化学镀等任何适合的方式形成导电金属层5。As shown in FIG. 3A , bonding pads 2 are formed on the substrate 1 . A passivation layer 3 is formed over the substrate 1 . The substrate 1 is covered, exposing the bond pads 2 below. The first spacer layer 4 is formed on the passivation layer 3 and exposes the bonding pads 2 , that is to say, the first spacer layer 4 has trenches exposing the bonding pads 2 . A conductive metal layer 5 is formed on the upper surface of the first spacer layer 4 , the inner wall surface of the trench and the upper surface of the exposed bonding pad 2 . The conductive metal layer 5 may be formed by any suitable method such as electroplating, electroless plating, or the like.
如图3B所示，在导电金属层5内形成导电体6，可以通过电镀、化学镀或溅射等任何适合的方式形成导电体6。随后在导电体6的上表面形成第二阻挡层7。第二阻挡层7可以由钛、钽等形成。然后，形成第二间隔层8，第二间隔层8露出第二阻挡层7，也就是说第二间隔层8具有露出第二阻挡层7 的沟槽。As shown in FIG. 3B , the conductor 6 is formed in the conductive metal layer 5 , and the conductor 6 may be formed by any suitable method such as electroplating, electroless plating or sputtering. A second barrier layer 7 is then formed on the upper surface of the conductor 6 . The second barrier layer 7 may be formed of titanium, tantalum, or the like. Then, the second spacer layer 8 is formed, and the second spacer layer 8 exposes the second barrier layer 7 , that is to say, the second spacer layer 8 has a trench through which the second barrier layer 7 is exposed.
如图3C所示，第二间隔层8的上表面、沟槽内壁面及第二阻挡层7的上表面形成阻挡层9。可以通过任何适当的方式形成阻挡层9。阻挡层9可以由Ni等形成。As shown in FIG. 3C , a barrier layer 9 is formed on the upper surface of the second spacer layer 8 , the inner wall surface of the trench and the upper surface of the second barrier layer 7 . The barrier layer 9 may be formed in any suitable manner. The barrier layer 9 may be formed of Ni or the like.
如图3D所示，除去形成在第二间隔层8上表面和第二阻挡层7上表面的部分阻挡层9，形成第一阻挡层91。As shown in FIG. 3D , part of the barrier layer 9 formed on the upper surface of the second spacer layer 8 and the upper surface of the second barrier layer 7 is removed to form a first barrier layer 91 .
如图3E所示，在第一阻挡层91内形成焊料层10。焊料层10的高度超出第一阻挡层91的高度，即焊料层10从第一阻挡层中露出，超出第一阻挡层91的高度大于第一阻挡层91高度的10％。焊料层10可以包含锡银、锡银铜、及其相似物等。As shown in FIG. 3E , the solder layer 10 is formed within the first barrier layer 91 . The height of the solder layer 10 exceeds the height of the first barrier layer 91 , that is, the solder layer 10 is exposed from the first barrier layer, and the height beyond the first barrier layer 91 is greater than 10% of the height of the first barrier layer 91 . The solder layer 10 may include tin-silver, tin-silver-copper, the like, and the like.
如图3F所示，除去第二间隔层8、形成在第一间隔层4上表面的部分导电金属层5和第一间隔层4。第二间隔层8和第一间隔层4可以是由光致抗蚀剂形成的光致抗蚀剂层，可以通过光刻蚀除去间隔层4和8。也可以是其他适当的材料形成间隔层4和8，根据间隔层4和8的材质选择适当的方式除去间隔层4和8。可以光刻蚀，或者其他任何适当的方式除去第一间隔层4 上表面的部分导电金属层5。经过回流焊后，结构如图3G所示。As shown in FIG. 3F , the second spacer layer 8 , part of the conductive metal layer 5 and the first spacer layer 4 formed on the upper surface of the first spacer layer 4 are removed. The second spacer layer 8 and the first spacer layer 4 may be photoresist layers formed of photoresist, and the spacer layers 4 and 8 may be removed by photolithography. The spacer layers 4 and 8 may also be formed of other appropriate materials, and the spacer layers 4 and 8 may be removed in an appropriate manner according to the materials of the spacer layers 4 and 8 . Part of the conductive metal layer 5 on the upper surface of the first spacer layer 4 may be removed by photo-etching or any other suitable manner. After reflow soldering, the structure is shown in Figure 3G.
本发明在焊料层的外表面环绕阻挡层，可以减少回焊工艺中由于焊料会出现爬锡造成锡量不足而导致的不沾锡的缺陷或焊料量太多导致焊桥缺陷，从而提高产品的良率。The invention surrounds the barrier layer on the outer surface of the solder layer, which can reduce the defect of non-sticking caused by insufficient tin amount due to the solder creeping up in the reflow process or the solder bridge defect caused by too much solder, thereby improving the product quality. Yield.
凸块下金属化层51与环形第一阻挡层91接触连接，实现对导电体的全包覆，防止焊料污染导电体。The under-bump metallization layer 51 is in contact with and connected to the annular first barrier layer 91 , so as to fully cover the conductor and prevent the solder from contaminating the conductor.
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。Of course, the present invention can also have other various embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding Changes and deformations should belong to the protection scope of the appended claims of the present invention.