CN111667874B - test system - Google Patents

A test system, comprising: the device comprises a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a temporary register. The registers operate as pipeline registers for the memory test circuitry and the output logic circuitry. In the first test mode, the memory test circuit transmits a first test signal to the memory, and the memory outputs the test signal to the temporary memory and then further transmits the test signal to the memory test circuit or the output logic circuit for testing.

测试系统test system

技术领域technical field

本发明涉及一种测试技术，且特别涉及一种测试系统。The present invention relates to a testing technology, and in particular, to a testing system.

背景技术Background technique

传统上，在测试内嵌式静态随机存取存储器(embedded static random accessmemory；eSRAM)时，会进行两种测试。一种是使用存储器测试电路对存储器进行测试；另一种是对电路进行电路功能的测试，以由一输入逻辑电路对存储器输出后的输出逻辑电路进行测试，又称扫描测试(scan test)。然而，为了进行上述的测试，以及输出逻辑电路功能的运行正常，常常需要设置多个暂存器(register)，以解决存储器在时序上的延迟可能造成的数据错误。这样的设置方式，往往提高测试电路的硬件成本。Traditionally, when testing embedded static random access memory (eSRAM), two types of tests are performed. One is to use the memory test circuit to test the memory; the other is to test the circuit function of the circuit, so that the output logic circuit after the output of the memory is tested by an input logic circuit, which is also called scan test. However, in order to carry out the above-mentioned test and the function of the output logic circuit to operate normally, it is often necessary to set up a plurality of registers (registers) to solve the data errors that may be caused by the delay in the timing of the memory. Such an arrangement often increases the hardware cost of the test circuit.

因此，如何设计一个新的测试系统，以解决上述的缺失，乃为此一业界亟待解决的问题。Therefore, how to design a new test system to solve the above deficiencies is an urgent problem to be solved in this industry.

发明内容SUMMARY OF THE INVENTION

发明内容旨在提供本公开内容的简化摘要，以使阅读者对本公开内容具备基本的理解。此发明内容并非本公开内容的完整概述，且其用意并非在指出本发明实施例的重要/关键元件或界定本发明的范围。SUMMARY The purpose of providing a simplified abstract of the disclosure is to provide the reader with a basic understanding of the disclosure. This summary is not an exhaustive overview of the disclosure, and it is not intended to identify key/critical elements of the embodiments of the invention or to delineate the scope of the invention.

本发明内容的一目的在于提供一种测试系统，借此改善现有技术的问题。An object of the present invention is to provide a testing system, thereby improving the problems of the prior art.

为达上述目的，本发明内容的一技术方案涉及一种测试系统，包含：存储器测试电路、存储器、输入逻辑电路、旁通电路、输出逻辑电路以及暂存器。存储器电性耦接于存储器测试电路。输入逻辑电路电性耦接于存储器。旁通电路选择性地与存储器测试电路或输入逻辑电路其中之一电性耦接。暂存器包含输入端以及输出端，输入端选择性地与存储器或旁通电路其中之一电性耦接，输出端电性耦接于存储器测试电路以及输出逻辑电路，暂存器运行为存储器测试电路以及输出逻辑电路的管线暂存器(pipeline register，流水线暂存器)。其中于第一测试模式时，由存储器测试电路传送第一测试信号至存储器，以由存储器输出存储器输出测试信号至暂存器进行暂存后进一步传送至存储器测试电路，以根据第一传送结果进行测试。In order to achieve the above object, a technical solution of the present invention relates to a test system, including: a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit, and a register. The memory is electrically coupled to the memory testing circuit. The input logic circuit is electrically coupled to the memory. The bypass circuit is selectively electrically coupled to one of the memory test circuit or the input logic circuit. The register includes an input end and an output end, the input end is selectively electrically coupled to one of the memory or the bypass circuit, the output end is electrically coupled to the memory test circuit and the output logic circuit, and the register operates as a memory Pipeline registers (pipeline registers) for test circuits and output logic circuits. In the first test mode, the memory test circuit transmits the first test signal to the memory, the memory outputs the test signal from the memory to the register for temporary storage, and then further transmits it to the memory test circuit for performing the test according to the first transmission result. test.

本发明的测试系统可通过暂存器的设置，提供输出逻辑电路、存储器测试电路以及旁通电路一个暂存的机制，可大幅减少硬件的成本。进一步地，通过暂存器所形成的共通路径，测试系统得以对存储器测试电路、输出逻辑电路以及旁通电路之间的所有可能路径均进行测试，更可达到提高测试涵盖率。The test system of the present invention can provide a temporary storage mechanism for the output logic circuit, the memory test circuit and the bypass circuit through the setting of the temporary memory, which can greatly reduce the cost of hardware. Further, through the common path formed by the register, the test system can test all possible paths between the memory test circuit, the output logic circuit and the bypass circuit, which can further improve the test coverage rate.

附图说明Description of drawings

为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂，附图的说明如下：In order to make the above-mentioned and other objects, features, advantages and embodiments of the present invention more clearly understood, the description of the accompanying drawings is as follows:

图1为本发明一实施例中，一种测试系统的方框图；1 is a block diagram of a testing system according to an embodiment of the present invention;

图2为本发明一实施例中，图1的测试系统运行于第一测试模式下的方框图；2 is a block diagram of the test system of FIG. 1 running in a first test mode in an embodiment of the present invention;

图3为本发明一实施例中，图1的测试系统运行于第二测试模式或第三测试模式下的方框图；以及3 is a block diagram of the test system of FIG. 1 operating in a second test mode or a third test mode according to an embodiment of the present invention; and

图4为本发明一实施例中，一种扫描链的示意图。FIG. 4 is a schematic diagram of a scan chain according to an embodiment of the present invention.

符号说明Symbol Description

1：测试系统 100：存储器测试电路1: Test System 100: Memory Test Circuit

102：存储器 104：输入逻辑电路102: Memory 104: Input logic circuit

105：比较器 106：旁通电路105: Comparator 106: Bypass circuit

108：输出逻辑电路 110：暂存器108: Output logic circuit 110: Scratchpad

112：多工器 114：多工器112: Multiplexer 114: Multiplexer

400：扫描链 402：移位暂存器400: Scan chain 402: Shift register

404：多工器 406：组合逻辑电路404: Multiplexer 406: Combinational Logic Circuit

ADD1、ADD2：位址信号 CLK：时钟信号ADD1, ADD2: address signal CLK: clock signal

CTL1、CTL2：控制信号 DATA：数据信号CTL1, CTL2: Control signal DATA: Data signal

DATA1、DATA2：数据信号 OOUT：存储器输出操作信号DATA1, DATA2: data signal OOUT: memory output operation signal

OUT：输出信号 P1：第一路径OUT: output signal P1: first path

P2：第二路径 P3：第三路径P2: Second path P3: Third path

P41、P42：第四路径 POUT：旁通输出测试信号P41, P42: Fourth path POUT: Bypass output test signal

SCAN：扫描信号 SE：选择信号SCAN: Scan signal SE: Select signal

SEL1、SEL2：选择信号 TOUT：存储器输出测试信号SEL1, SEL2: selection signal TOUT: memory output test signal

具体实施方式Detailed ways

请参照图1。图1为本发明一实施例中，一种测试系统1的方框图。测试系统1包含：存储器测试电路100、存储器102、输入逻辑电路104、旁通电路106、输出逻辑电路108、暂存器110、多工器112以及多工器114。Please refer to Figure 1. FIG. 1 is a block diagram of a testing system 1 according to an embodiment of the present invention. The test system 1 includes: a memory test circuit 100 , a memory 102 , an input logic circuit 104 , a bypass circuit 106 , an output logic circuit 108 , a register 110 , a multiplexer 112 and a multiplexer 114 .

通过多工器112，存储器测试电路100或输入逻辑电路104其中之一可选择性地电性耦接于存储器102。One of the memory test circuit 100 or the input logic circuit 104 can be selectively electrically coupled to the memory 102 through the multiplexer 112 .

于一实施例中，多工器112是根据选择信号SEL1进行选择。举例而言，在选择信号SEL1为第一电压准位时，多工器112使存储器测试电路100电性耦接于存储器102及旁通电路106。而在选择信号SEL1为第二电压准位时，多工器112使输入逻辑电路104电性耦接于存储器102及旁通电路106。In one embodiment, the multiplexer 112 is selected according to the selection signal SEL1. For example, when the selection signal SEL1 is at the first voltage level, the multiplexer 112 electrically couples the memory testing circuit 100 to the memory 102 and the bypass circuit 106 . When the selection signal SEL1 is at the second voltage level, the multiplexer 112 electrically couples the input logic circuit 104 to the memory 102 and the bypass circuit 106 .

于一实施例中，存储器102为例如，但不限于内嵌式静态随机存取存储器(embedded static random access memory；eSRAM)，配置以存储经由存储器测试电路100或是输入逻辑电路104输入的信号，并再输出。In one embodiment, the memory 102 is, for example, but not limited to, an embedded static random access memory (eSRAM), configured to store signals input through the memory test circuit 100 or the input logic circuit 104, and output again.

于一实施例中，存储器测试电路100为内建自我测试(Built-in Self Test；BIST)电路，并配置以产生包含例如但不限于数据信号DATA1、位址信号ADD1以及控制信号CTL1的一组信号，并通过多工器112传送到存储器102。In one embodiment, the memory test circuit 100 is a built-in self test (BIST) circuit, and is configured to generate a set of, for example but not limited to, a data signal DATA1, an address signal ADD1 and a control signal CTL1. The signal is transmitted to the memory 102 through the multiplexer 112 .

于一实施例中，输入逻辑电路104配置以产生包含例如但不限于数据信号DATA2、位址信号ADD2以及控制信号CTL2的一组信号，并通过多工器112传送到存储器102。In one embodiment, the input logic circuit 104 is configured to generate a set of signals including, for example, but not limited to, the data signal DATA2 , the address signal ADD2 and the control signal CTL2 , and transmit them to the memory 102 through the multiplexer 112 .

另一方面，通过多工器112，存储器测试电路100或输入逻辑电路104其中之一可选择性地电性耦接于旁通电路106。旁通电路106配置以将存储器测试电路100或输入逻辑电路104传送的信号传送至其他电路。于一实施例中，旁通电路106仅有传送信号的功能，不具有暂存的机制。On the other hand, one of the memory test circuit 100 or the input logic circuit 104 can be selectively electrically coupled to the bypass circuit 106 through the multiplexer 112 . Bypass circuit 106 is configured to pass signals passed by memory test circuit 100 or input logic circuit 104 to other circuits. In one embodiment, the bypass circuit 106 only has a function of transmitting signals, and does not have a temporary storage mechanism.

暂存器110具有输入端以及输出端。通过多工器114，存储器102或旁通电路106其中之一可选择性地电性耦接于暂存器110的输入端，以使暂存器110的输入端接收来自存储器102或旁通电路106所传送的信号进行暂存。The register 110 has an input terminal and an output terminal. Through the multiplexer 114, one of the memory 102 or the bypass circuit 106 can be selectively electrically coupled to the input end of the register 110, so that the input end of the register 110 receives the input from the memory 102 or the bypass circuit 106 The transmitted signal is temporarily stored.

暂存器110的输出端电性耦接于存储器测试电路100以及输出逻辑电路108，以将暂存的信号进一步传送到存储器测试电路100及输出逻辑电路108中。The output terminal of the register 110 is electrically coupled to the memory test circuit 100 and the output logic circuit 108 to further transmit the temporarily stored signal to the memory test circuit 100 and the output logic circuit 108 .

在运行模式中，暂存器110运行为输出逻辑电路108的管线暂存器(pipelineregister)。In the run mode, the register 110 operates as a pipeline register for the output logic circuit 108 .

更详细地说，在运行模式中，输入逻辑电路104可通过多工器112传送例如，但不限于包含数据信号DATA2、位址信号ADD2以及控制信号CTL2的输入操作信号至存储器102存储。存储器102进而据以输出存储器输出操作信号OOUT至暂存器110进行暂存后，进一步由暂存器110传送至输出逻辑电路108。由于暂存器110的存在，使得输出逻辑电路108所接收到的信号不受存储器102的延迟影响，避免时序不正确(timing violation)造成的数据错误。In more detail, in the running mode, the input logic circuit 104 may transmit input operation signals including, but not limited to, the data signal DATA2 , the address signal ADD2 and the control signal CTL2 to the memory 102 for storage through the multiplexer 112 . The memory 102 further outputs the memory output operation signal OOUT to the register 110 for temporary storage, and then further transmits the signal from the register 110 to the output logic circuit 108 . Due to the existence of the temporary memory 110, the signal received by the output logic circuit 108 is not affected by the delay of the memory 102, thereby avoiding data errors caused by timing violations.

请参照图2。图2为本发明一实施例中，图1的测试系统1运行于第一测试模式下的方框图。Please refer to Figure 2. FIG. 2 is a block diagram of the test system 1 of FIG. 1 running in a first test mode according to an embodiment of the present invention.

于第一测试模式时，经由多工器112根据选择信号SEL1的控制后，由存储器测试电路100传送包含例如但不限于数据信号DATA1、位址信号ADD1以及控制信号CTL1的第一测试信号至存储器102存储。接着，存储器102将输出存储器输出测试信号TOUT，经由多工器114根据选择信号SEL2的控制后，传送至暂存器110进行暂存，进一步再传送至存储器测试电路100或是输出逻辑电路108。In the first test mode, after the multiplexer 112 is controlled by the selection signal SEL1, the memory test circuit 100 transmits the first test signal including, but not limited to, the data signal DATA1, the address signal ADD1 and the control signal CTL1 to the memory 102 storage. Next, the memory 102 outputs the memory output test signal TOUT, which is transmitted to the register 110 for temporary storage through the multiplexer 114 according to the control of the selection signal SEL2, and further transmitted to the memory test circuit 100 or the output logic circuit 108.

因此，在第一测试模式中，暂存器110可运行为存储器测试电路100以及输出逻辑电路108的管线暂存器。Therefore, in the first test mode, the register 110 can operate as a pipeline register for the memory test circuit 100 and the output logic circuit 108 .

更详细地说，暂存器110的存在，可使得存储器测试电路100以及输出逻辑电路108所接收到的信号不受存储器102的延迟影响，避免时序不正确造成的数据错误。In more detail, the existence of the register 110 can prevent the signals received by the memory testing circuit 100 and the output logic circuit 108 from being affected by the delay of the memory 102, thereby avoiding data errors caused by incorrect timing.

于一实施例中，存储器测试电路100包含比较器105，配置以对第一测试信号与暂存器110传送至存储器测试电路100的第一传送结果进行比较，以测试存储器102。In one embodiment, the memory test circuit 100 includes a comparator 105 configured to test the memory 102 by comparing the first test signal with the first transmission result transmitted from the register 110 to the memory test circuit 100 .

在这样的情形下，除了可对存储器102测试外，存储器102至暂存器110的第一路径P1以及暂存器110至存储器测试电路100的第二路径P2亦可被测试。In this case, in addition to testing the memory 102 , the first path P1 from the memory 102 to the register 110 and the second path P2 from the register 110 to the memory testing circuit 100 can also be tested.

请参照图3。图3为本发明一实施例中，图1的测试系统1运行于第二测试模式或第三测试模式下的方框图。Please refer to Figure 3. FIG. 3 is a block diagram of the test system 1 of FIG. 1 operating in a second test mode or a third test mode in an embodiment of the present invention.

于第二测试模式时，经由多工器112根据选择信号SEL1的控制后，由存储器测试电路100传送包含例如但不限于数据信号DATA1、位址信号ADD1以及控制信号CTL1的第一测试信号，或由输入逻辑电路104传送包含例如但不限于数据信号DATA2、位址信号ADD2以及控制信号CTL2的第二测试信号至旁通电路106。In the second test mode, after the multiplexer 112 is controlled by the selection signal SEL1, the memory test circuit 100 transmits the first test signal including, but not limited to, the data signal DATA1, the address signal ADD1 and the control signal CTL1, or A second test signal including, but not limited to, a data signal DATA2 , an address signal ADD2 , and a control signal CTL2 is transmitted from the input logic circuit 104 to the bypass circuit 106 .

接着，旁通电路106输出旁通输出测试信号POUT，经由多工器114根据选择信号SEL2的控制后，传送至暂存器110进行暂存，扫描测试可以通过此暂存器110测试存储器测试电路100或输入逻辑电路104至旁通电路106再至暂存器110的第四路径P41或P42。Next, the bypass circuit 106 outputs the bypass output test signal POUT, which is transmitted to the register 110 for temporary storage through the multiplexer 114 according to the control of the selection signal SEL2. The scan test can be used to test the memory test circuit through the register 110. 100 or the input logic circuit 104 to the bypass circuit 106 and then to the fourth path P41 or P42 of the register 110 .

于一实施例中，扫描测试可通过暂存器110传送测试信号至存储器测试电路100进行比较，以测试存储器测试电路100自身的逻辑功能。In one embodiment, the scan test can transmit a test signal to the memory test circuit 100 through the register 110 for comparison, so as to test the logic function of the memory test circuit 100 itself.

在这样的情形下，除了可对存储器测试电路100自身的逻辑功能测试外，暂存器110至存储器测试电路100的第二路径P2亦可被测试。In this case, in addition to testing the logic function of the memory test circuit 100, the second path P2 from the register 110 to the memory test circuit 100 can also be tested.

扫描测试可以通过暂存器110将扫描测试信号传送至输出逻辑电路108，如此暂存器110至输出逻辑电路108的第三路径P3可被测试。The scan test can transmit the scan test signal to the output logic circuit 108 through the register 110, so that the third path P3 from the register 110 to the output logic circuit 108 can be tested.

需注意的是，若无暂存器110，在第二测试模式时，测试的路径就必须从存储器测试电路100经旁通电路106到存储器测试电路100、从存储器测试电路100经旁通电路106到输出逻辑电路108、从输入逻辑电路104经旁通电路106到存储器测试电路100或从输入逻辑电路104经旁通电路106到输出逻辑电路108。It should be noted that, if there is no register 110, in the second test mode, the test path must be from the memory test circuit 100 via the bypass circuit 106 to the memory test circuit 100, and from the memory test circuit 100 via the bypass circuit 106. To the output logic circuit 108 , from the input logic circuit 104 via the bypass circuit 106 to the memory test circuit 100 or from the input logic circuit 104 via the bypass circuit 106 to the output logic circuit 108 .

然而，如果有暂存器110，扫描测试的路径可被分为存储器测试电路100到暂存器110、输入逻辑电路104到暂存器110、暂存器110到存储器测试电路100、暂存器110到输出逻辑电路108。因此，在具有暂存器110的情形下，各别的路径较短，在电路设计上时序问题较容易被克服。However, if there is a scratchpad 110, the scan test path can be divided into memory test circuit 100 to scratchpad 110, input logic circuit 104 to scratchpad 110, scratchpad 110 to memory test circuit 100, scratchpad 110 to the output logic circuit 108 . Therefore, in the case of having the register 110, the respective paths are shorter, and the timing problem in circuit design is easier to overcome.

在另一实施例中，于第三测试模式时，是由存储器测试电路100传送包含例如但不限于数据信号DATA1、位址信号ADD1以及控制信号CTL1的第一测试信号，或由输入逻辑电路104传送包含例如但不限于数据信号DATA2、位址信号ADD2以及控制信号CTL2的第二测试信号至旁通电路106，以由旁通电路106输出旁通输出测试信号POUT至暂存器110进行暂存，以根据第三传送结果进行测试，使得第四路径P41以及P42可被测试。In another embodiment, in the third test mode, the memory test circuit 100 transmits the first test signal including, but not limited to, the data signal DATA1, the address signal ADD1 and the control signal CTL1, or the input logic circuit 104 Send a second test signal including, but not limited to, the data signal DATA2, the address signal ADD2 and the control signal CTL2 to the bypass circuit 106, so that the bypass circuit 106 outputs the bypass output test signal POUT to the register 110 for temporary storage , so as to test according to the third transmission result, so that the fourth paths P41 and P42 can be tested.

接着，暂存器110通过连接的扫描链(scan chain)输出第三测试信号TEST至存储器测试电路100或输出逻辑电路108，以根据第四传送结果进行测试，使得第二路径P2及第三路径P3可被测试。其中，第三测试信号TEST可与第二测试信号不同，且第三测试信号TEST可由测试系统1以外的一主机(图未示出)经由扫描链输入暂存器110。Next, the register 110 outputs the third test signal TEST to the memory test circuit 100 or the output logic circuit 108 through the connected scan chain, so as to perform the test according to the fourth transmission result, so that the second path P2 and the third path are P3 can be tested. The third test signal TEST may be different from the second test signal, and the third test signal TEST may be input to the register 110 by a host other than the test system 1 (not shown) via the scan chain.

请参照图4。图4为本发明一实施例中，一种扫描链400的示意图。Please refer to Figure 4. FIG. 4 is a schematic diagram of a scan chain 400 according to an embodiment of the present invention.

扫描链400包含多个移位暂存器(shift register)。以图4示出的移位暂存器402为例，其依照时钟信号CLK运行，搭配多工器404根据选择信号SE，在运行模式下选择数据信号DATA作为输入，以依虚线示出的路径传送数据信号DATA至组合逻辑电路406。或是在扫描模式下选择扫描信号SCAN作为输入，以依粗实线示出的路径传送扫描信号SCAN至下一级的移位暂存器，直至最后一级的移位暂存器产生输出信号OUT。The scan chain 400 includes a plurality of shift registers. Taking the shift register 402 shown in FIG. 4 as an example, it operates according to the clock signal CLK, and the multiplexer 404 selects the data signal DATA as the input in the operation mode according to the selection signal SE, and follows the path shown by the dotted line. The data signal DATA is sent to the combinational logic circuit 406 . Or select the scan signal SCAN as the input in the scan mode, and transmit the scan signal SCAN to the shift register of the next stage according to the path shown by the thick solid line, until the shift register of the last stage generates the output signal OUT.

于一实施例中，存储器测试电路100、输入逻辑电路104及输出逻辑电路108各自设置至少一内部暂存器。暂存器110可将第三测试信号TEST作为扫描信号SCAN，通过扫描链400的移位暂存器输出为输出信号OUT，传送至存储器测试电路100或输出逻辑电路108所包含的内部暂存器，进而使第二路径P2及第三路径P3可被测试是否正确。In one embodiment, the memory test circuit 100 , the input logic circuit 104 and the output logic circuit 108 are each provided with at least one internal register. The register 110 can use the third test signal TEST as the scan signal SCAN, output the third test signal TEST as the output signal OUT through the shift register of the scan chain 400, and transmit it to the memory test circuit 100 or the internal register included in the output logic circuit 108 , so that the second path P2 and the third path P3 can be tested for correctness.

在部分技术中，为了使信号的传输不会造成时序不正确，往往对于存储器测试电路100、输出逻辑电路108以及旁通电路106对应的三个路径必须设置三个暂存器，来分别提供管线暂存器的技术效果。并且，在这样的配置下，存储器测试电路100、输出逻辑电路108以及旁通电路106之间互相分离的路径中，会存在有无法被测试的路径，而使测试的精确度下降。In some technologies, in order to prevent the signal transmission from causing incorrect timing, three registers must be set for the three paths corresponding to the memory test circuit 100 , the output logic circuit 108 and the bypass circuit 106 to provide pipelines respectively. The technical effect of the scratchpad. In addition, in such a configuration, among the paths separated from each other among the memory test circuit 100 , the output logic circuit 108 and the bypass circuit 106 , there may be paths that cannot be tested, thereby reducing the accuracy of the test.

因此，本发明的测试系统1可通过暂存器110的设置，在运行模式下提供输出逻辑电路108作为管线暂存器，并且在测试模式下除可提供存储器测试电路100作为管线暂存器，亦可提供旁通电路106一个暂存的机制，可大幅减少硬件的成本。进一步地，通过暂存器110所形成的共通路径，测试系统1得以对存储器测试电路100、输出逻辑电路108以及旁通电路106之间的所有可能路径，包括前述的第一路径P1、第二路径P2、第三路径P3及第四路径P4均进行测试，更可达到提高测试涵盖率(test coverage)。Therefore, the test system 1 of the present invention can provide the output logic circuit 108 as a pipeline register in the running mode through the setting of the register 110, and in addition to provide the memory test circuit 100 as a pipeline register in the test mode, A temporary storage mechanism can also be provided for the bypass circuit 106, which can greatly reduce the cost of hardware. Further, through the common path formed by the register 110, the test system 1 can check all possible paths between the memory test circuit 100, the output logic circuit 108 and the bypass circuit 106, including the aforementioned first path P1, second path The path P2, the third path P3 and the fourth path P4 are all tested, which can further improve the test coverage.

虽然上文实施方式中公开了本发明的具体实施例，然其并非用以限定本发明，本发明所属技术领域中技术人员，在不悖离本发明的原理与精神的情形下，当可对其进行各种变动与修饰，因此本发明的保护范围当以附随权利要求所界定者为准。Although the above embodiments disclose specific embodiments of the present invention, they are not intended to limit the present invention. Those skilled in the art to which the present invention pertains can, without departing from the principles and spirit of the present invention, It undergoes various changes and modifications, so the protection scope of the present invention should be defined by the appended claims.