CN111899777A - Single-gate multi-write non-volatile memory and its operation method - Google Patents
- ️Fri Nov 06 2020
CN111899777A - Single-gate multi-write non-volatile memory and its operation method - Google Patents
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- CN111899777A CN111899777A CN201910367887.0A CN201910367887A CN111899777A CN 111899777 A CN111899777 A CN 111899777A CN 201910367887 A CN201910367887 A CN 201910367887A CN 111899777 A CN111899777 A CN 111899777A Authority
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Abstract
一种单闸极多次写入非挥发性内存及其操作方法，此非挥发性内存为单浮接闸极，其是在半导体基底上设置晶体管及电容结构，晶体管于导电闸极两侧的半导体基底内具有两个离子掺杂区作为源极和汲极，其中源极和汲极的宽度设计成不同，可利用汲极的边缘作为电容，藉以控制浮动闸极；本发明于写入时可以使用最少的控制电压种类及最少的组件，能够大幅缩短控制线路的长度，达到缩小整体面积的效果，从而减少非挥发性内存的生产成本。
A single-gate multiple-write non-volatile memory and an operation method thereof. The non-volatile memory is a single floating gate, and a transistor and a capacitor structure are arranged on a semiconductor substrate. The transistor has two ion-doped regions in the semiconductor substrate on both sides of the conductive gate as a source and a drain. The widths of the source and the drain are designed to be different, and the edge of the drain can be used as a capacitor to control the floating gate. The present invention can use the least control voltage type and the least components when writing, and can greatly shorten the length of the control circuit, achieving the effect of reducing the overall area, thereby reducing the production cost of the non-volatile memory.
Description
技术领域technical field
本发明涉及一种单闸极多次写入非挥发性内存(Non-Volatile Memory)，特别是关于一种利用汲极边缘当作电容来控制浮动闸极的单闸极多次写入非挥发性内存及其操作方法。The invention relates to a single-gate multi-write non-volatile memory (Non-Volatile Memory), in particular to a single-gate multi-write non-volatile memory using the edge of the drain as a capacitor to control the floating gate Sexual memory and how to operate it.
背景技术Background technique
互补式金属氧化半导体(Complementary Metal Oxide Semiconductor，CMOS)制程技术已成为特殊应用集成电路(application specific integrated circuit，ASIC)的常用制造方法。在计算机信息产品发达的今天，电子式可清除程序化只读存储器(Electrically Erasable Programmable Read Only Memory，EEPROM)由于具备有电性编写和抹除数据的非挥发性内存功能，且在电源关掉后数据不会消失，所以被广泛使用于电子产品上。Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common manufacturing method for application specific integrated circuits (ASICs). With the development of computer information products today, Electronically Erasable Programmable Read Only Memory (EEPROM) has the function of non-volatile memory for electrically writing and erasing data, and after the power is turned off Data will not disappear, so it is widely used in electronic products.
非挥发性内存为可程序化的，其用以储存电荷以改变内存的晶体管的闸极电压，或不储存电荷以留下原内存的晶体管的闸极电压。抹除操作则是将储存在非挥发性内存中的所有电荷移除，使得所有非挥发性内存回到原内存的晶体管的闸极电压。在现有的单闸极非挥发性内存的结构中，控制电压种类多、存储元件多，因此非挥发内存面积较大，造成成本的增加。Non-volatile memory is programmable to store charge to change the gate voltage of the transistors of the memory, or not store charge to leave the gate voltage of the transistors of the original memory. The erase operation is to remove all the charges stored in the non-volatile memory, so that all the non-volatile memory returns to the gate voltage of the transistors of the original memory. In the existing single-gate non-volatile memory structure, there are many types of control voltages and many storage elements, so the area of the non-volatile memory is large, which increases the cost.
有鉴于此，本发明遂针对上述现有技术的缺失，特别提出一种单闸极多次写入非挥发性内存及其操作方法，以大幅缩减单闸极非挥发性内存面积，及提升单闸极非挥发性内存的产品价值。In view of this, the present invention specifically proposes a single-gate multi-write non-volatile memory and an operation method thereof in order to reduce the area of the single-gate non-volatile memory greatly, and improve the single-gate non-volatile memory. Product value of gate non-volatile memory.
发明内容SUMMARY OF THE INVENTION
本发明的主要目的在于提供一种单闸极多次写入非挥发性内存及其操作方法，该非挥发性内存中的源极和汲极设计成不同宽度，以利用汲极的边缘作为电容来控制浮动闸极，于写入时可以最少的控制电压种类及最少的组件，达到缩小整体面积的效果。相较于一般可写入单闸极的非挥发性内存因为控制复杂造成成本提高，本发明因为操作简单组件最少，大幅减少控制线路，可大幅减少非挥发性内存的成本。The main purpose of the present invention is to provide a single-gate multi-write non-volatile memory and an operation method thereof. The source and drain of the non-volatile memory are designed to have different widths, so as to use the edge of the drain as a capacitor To control the floating gate, it can control the least voltage types and the least components during writing, so as to achieve the effect of reducing the overall area. Compared with the general non-volatile memory that can be written to a single gate, the cost is increased due to the complicated control. The present invention can greatly reduce the cost of the non-volatile memory because of the simple operation and the few components, greatly reducing the control circuit.
因此，为达上述目的，本发明所公开的一种单闸极多次写入非挥发性内存，此单闸极多次写入非挥发性内存包括P型半导体基底、晶体管和电容结构；其中，晶体管与电容结构设置于P型半导体基底，晶体管是由第一导电闸极堆栈在第一介电层表面，第一介电层位于P型半导体基底上，且有两个高度导电的离子掺杂区位于第一导电闸极与第一介电层两侧的P型半导体基底内来形成源极及汲极，且源极和汲极具有不同宽度；电容结构是利用汲极的边缘作为电容，藉以控制浮动闸极，且汲极与浮动闸极中间包含有轻掺杂区，轻掺杂区与离子掺杂区具有同型的离子，并形成非挥发性内存的单浮接闸极。Therefore, in order to achieve the above-mentioned purpose, a single-gate multi-write non-volatile memory disclosed in the present invention includes a P-type semiconductor substrate, a transistor and a capacitor structure; wherein , the transistor and capacitor structure are arranged on the P-type semiconductor substrate, the transistor is stacked on the surface of the first dielectric layer by the first conductive gate, the first dielectric layer is located on the P-type semiconductor substrate, and there are two highly conductive ion doped The impurity region is located in the P-type semiconductor substrate on both sides of the first conductive gate and the first dielectric layer to form a source electrode and a drain electrode, and the source electrode and the drain electrode have different widths; the capacitor structure uses the edge of the drain electrode as a capacitor , so as to control the floating gate, and a lightly doped region is included between the drain and the floating gate, and the lightly doped region and the ion-doped region have ions of the same type, and form a single floating gate of the non-volatile memory.
本发明中，半导体基底为P型半导体基板或是具有P型井的半导体基板，晶体管结构为N型晶体管，轻掺杂区与离子掺杂区为N型离子掺杂区。In the present invention, the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well, the transistor structure is an N-type transistor, and the lightly doped region and the ion-doped region are N-type ion-doped regions.
另外，本发明所公开的单闸极多次写入非挥发性内存的操作方法，可对于上述由P型半导体基底、晶体管与电容结构所构成的单闸极多次写入非挥发性内存，藉由于P型半导体基底、源极与汲极上分别施加基底电压Vsub、源极电压Vs、汲极电压Vd，进行写入或抹除过程。其中，于写入时，满足Vsub为接地(＝0)，Vd＝Vs＝高压(HV)；或Vd＝高压(HV)，且Vs＝中压(MV)或低压(LV)；或Vd＝中压(MV)，Vs＝低压(LV)或接地(0)。于抹除时，满足Vsub为接地(0)，Vd＝高压(HV)，Vs＝浮接；或Vd＝高压(HV)，Vs为接地(＝0)；或Vs＝高压(HV)，且Vd＝接地(0)；或Vs＝高压(HV)，且Vd＝浮接。In addition, the operation method of the single-gate multi-write non-volatile memory disclosed in the present invention can be used for the above-mentioned single-gate multi-write non-volatile memory composed of a P-type semiconductor substrate, a transistor and a capacitor structure, The writing or erasing process is performed by applying the substrate voltage V sub , the source voltage V s , and the drain voltage V d to the P-type semiconductor substrate, the source electrode and the drain electrode, respectively. Wherein, when writing, V sub is grounded (=0), V d =V s = high voltage (HV); or V d = high voltage (HV), and V s = medium voltage (MV) or low voltage (LV ); or V d = medium voltage (MV), V s = low voltage (LV) or ground (0). When erasing, V sub is ground (0), V d = high voltage (HV), V s = floating; or V d = high voltage (HV), V s is ground (= 0); or V s = High voltage (HV), and Vd = ground (0); or Vs = high voltage (HV), and Vd = floating.
以下藉由具体实施例配合所附的图式详加说明，当更容易了解本发明的目的、技术内容、特点及其所达成的功效。The following describes in detail with the accompanying drawings by means of specific embodiments, so as to more easily understand the purpose, technical content, characteristics and effects of the present invention.
附图说明Description of drawings
图1为本发明的一个实施例的单闸极多次写入非挥发性内存结构的剖视图。1 is a cross-sectional view of a single-gate write-multiple non-volatile memory structure according to an embodiment of the present invention.
图2为本发明的一个实施例中具有不同宽度的源极和汲极的一种布局结构。FIG. 2 is a layout structure of a source electrode and a drain electrode having different widths according to an embodiment of the present invention.
图3为本发明的一个实施例中具有不同宽度的源极和汲极的另一种布局结构。FIG. 3 is another layout structure of sources and drains with different widths according to an embodiment of the present invention.
图4为本发明的一个实施例的设有三个端点的结构示意图。FIG. 4 is a schematic diagram of a structure with three endpoints according to an embodiment of the present invention.
附图标记说明：100-单闸极多次写入非挥发性内存；110-NMOS晶体管；111-第一介电层；112-第一导电闸极；113-源极；114-汲极；115-通道；116-轻掺杂区；120-N型电容结构；130-P型半导体基底；Ld-长度；Ls-长度；Vd-汲极电压；Vs-源极电压；Vsub-基底电压；Wd-宽度；Ws-宽度。Reference numeral description: 100-single gate multiple write non-volatile memory; 110-NMOS transistor; 111-first dielectric layer; 112-first conductive gate; 113-source; 114-drain; 115-channel; 116-lightly doped region; 120-N-type capacitor structure; 130-P-type semiconductor substrate; Ld -length; Ls-length; Vd -drain voltage ; Vs -source voltage; V sub - substrate voltage; W d - width; W s - width.
具体实施方式Detailed ways
请参照图1，为本发明的一个实施例的单闸极多次写入非挥发性内存结构的剖视图。Please refer to FIG. 1 , which is a cross-sectional view of a single-gate write-multiple non-volatile memory structure according to an embodiment of the present invention.
单闸极多次写入非挥发性内存100包括P型半导体基板130，亦可为具有P型井的半导体基板，在此是以P型半导体基板130为例，NMOS晶体管(NMOSFET)110及N型电容结构120设于P型半导体基底130中；NMOS晶体管110包含第一介电层111位于P型半导体基底130表面上，第一导电闸极112迭设于第一介电层111上方，以及二离子掺杂区位于P型半导体基底130内，分别作为其源极113及汲极114，在源极113和汲极114间形成通道115，且源极113及汲极114具有不同宽度；N型电容结构120利用汲极114的边缘作为电容来控制一浮动闸极，并形成非挥发性内存100的一单浮接闸极(floating gate)。具体来说，汲极114边缘是在浮动闸极中间区域。其中，汲极114与浮动闸极中间包含有轻掺杂区116，离子掺杂区与轻掺杂区为N型离子掺杂区。The single-gate write-multiple non-volatile memory 100 includes a P-type semiconductor substrate 130, which can also be a semiconductor substrate with a P-type well. Here, the P-type semiconductor substrate 130 is used as an example. NMOS transistors (NMOSFETs) 110 and N The capacitor structure 120 is disposed in the P-type semiconductor substrate 130; the NMOS transistor 110 includes a first dielectric layer 111 on the surface of the P-type semiconductor substrate 130, a first conductive gate 112 is stacked on the first dielectric layer 111, and The two-ion doped region is located in the P-type semiconductor substrate 130, and serves as the source electrode 113 and the drain electrode 114, respectively. A channel 115 is formed between the source electrode 113 and the drain electrode 114, and the source electrode 113 and the drain electrode 114 have different widths; N The type capacitor structure 120 uses the edge of the drain 114 as a capacitor to control a floating gate and form a single floating gate of the non-volatile memory 100 . Specifically, the edge of the drain 114 is in the middle region of the floating gate. A lightly doped region 116 is included between the drain electrode 114 and the floating gate electrode, and the ion-doped region and the lightly-doped region are N-type ion-doped regions.
本发明中，所谓源极113和汲极114的宽度是指其沿着一横轴方向(即，由源极113往汲极114的平行方向)的边长，如图1所示，本实施例的汲极114的宽度Wd大于源极113的宽度Ws。另外，源极113和汲极114的长度也可为不同，如图2所示，本实施例的一个态样是将汲极114的离子掺杂区的长度Ld设计成大于源极113的离子掺杂区的长度Ls；另外，如图3所示，本实施例的另一个态样是将汲极114的离子掺杂区的长度Ld设计成大于源极113的离子掺杂区的长度Ls，且其两相对侧边呈现有夹角。In the present invention, the so-called width of the source electrode 113 and the drain electrode 114 refers to the side length along a horizontal axis direction (ie, the parallel direction from the source electrode 113 to the drain electrode 114 ). As shown in FIG. 1 , this embodiment In this example, the width W d of the drain electrode 114 is greater than the width W s of the source electrode 113 . In addition, the lengths of the source electrode 113 and the drain electrode 114 may also be different. As shown in FIG. 2 , in one aspect of this embodiment, the length L d of the ion-doped region of the drain electrode 114 is designed to be greater than that of the source electrode 113 . The length L s of the ion-doped region; in addition, as shown in FIG. 3 , another aspect of this embodiment is to design the length L d of the ion-doped region of the drain electrode 114 to be larger than the ion-doped region of the source electrode 113 The length L s of , and its two opposite sides present an included angle.
此单闸极多次写入非挥发性内存100设有三个端点，其示意图如图4所示，此三个端点分别为源极、汲极以及基底连接结构，并于P型半导体基底130、源极113及汲极114上分别施加基底电压Vsub、源极电压Vs及汲极电压Vd。此单闸极多次写入非挥发性内存100的操作电压过程的条件如下：The single-gate multi-write non-volatile memory 100 has three terminals, a schematic diagram of which is shown in FIG. 4 , the three terminals are the source, the drain, and the substrate connection structure, and are connected to the P-type semiconductor substrate 130 , The source electrode 113 and the drain electrode 114 are respectively applied with the substrate voltage V sub , the source voltage V s and the drain voltage V d . The conditions of the single-gate multi-write operation voltage process of the non-volatile memory 100 are as follows:
写入时：When writing:
a.Vsub＝接地(0)。aV sub = ground (0).
b.Vd＝Vs＝高压(HV)；或bV d = V s = high voltage (HV); or
Vd＝高压(HV)，且Vs＝中压(MV)或低压(LV)；或V d = high voltage (HV) and V s = medium voltage (MV) or low voltage (LV); or
Vd＝中压(MV)，且Vs＝低压(LV)或接地(0)。V d = medium voltage (MV), and V s = low voltage (LV) or ground (0).
抹除时：When erasing:
a.Vsub＝接地(0)。aV sub = ground (0).
b.Vd＝高压(HV)，且Vs＝接地(0)；或bV d = high voltage (HV), and V s = ground (0); or
Vd＝高压(HV)，且Vs＝浮接；或V d = high voltage (HV), and V s = floating; or
Vs＝高压(HV)，且Vd＝接地(0)；或V s = high voltage (HV), and V d = ground (0); or
Vs＝高压(HV)，且Vd＝浮接。V s = high voltage (HV), and V d = floating.
进一步地，具体说明上述偏压条件中所提出的「高压」、「中压」及「低压」的范围，其中，「高压」是指汲极对源极的崩溃电压-晶体管的临界电压Vt；「中压」是指汲极对源极的崩溃电压×1/2；且「低压」是指汲极对源极的崩溃电压×1/4。Further, the ranges of "high voltage", "medium voltage" and "low voltage" proposed in the above-mentioned bias conditions are specifically described, wherein "high voltage" refers to the breakdown voltage of the drain to the source - the threshold voltage V t of the transistor ; "Medium voltage" refers to the breakdown voltage of drain to source × 1/2; and "low voltage" refers to the breakdown voltage of drain to source × 1/4.
上述图1的结构是在P型硅晶圆上制造而得，由标准隔离模块制程来完成基本的隔离结构之后，一个NMOS晶体管的通道是藉由离子布植来形成，在成长第一导电闸极的介电层之后，接着，沉积形成多晶硅，且以微影蚀刻进行图案化将多晶硅形成单浮接闸极；然后，进行离子布植，以形成NMOS晶体管的汲极和源极等电极。在金属化之后，便完成许多单闸极多次写入非挥发性内存结构的制作。The structure shown in Figure 1 above is fabricated on a P-type silicon wafer. After the basic isolation structure is completed by a standard isolation module process, a channel of an NMOS transistor is formed by ion implantation. After growing the first conductive gate After the electrode dielectric layer is formed, polysilicon is then deposited and patterned by lithography etching to form a single floating gate; then, ion implantation is performed to form electrodes such as the drain and source of the NMOS transistor. After metallization, the fabrication of many single-gate multi-write non-volatile memory structures is completed.
综上所述，根据本发明所揭露的单闸极多次写入非挥发性内存及其操作方法，相较于一般可写入单闸极的非挥发性内存，其控制复杂、成本较高，本发明于写入时可以最少的控制电压及最少的组件，可使得非挥发性内存的面积得以大幅减少，并可缩短控制线路的长度，从而达到大幅降低生产成本的目的。To sum up, according to the single-gate multi-write non-volatile memory and the operation method thereof disclosed in the present invention, compared with the general non-volatile memory that can be written to a single gate, its control is complicated and the cost is higher Therefore, the present invention can minimize the control voltage and components during writing, so that the area of the non-volatile memory can be greatly reduced, and the length of the control circuit can be shortened, so as to achieve the purpose of greatly reducing the production cost.
以上所述是藉由实施例说明本发明的特点，其目的在使熟习该技术者能了解本发明的内容并据以实施，而非限定本发明的专利范围，故，凡其他未脱离本发明所揭示的精神所完成的等效修饰或修改，仍应包含本案的保护范围内。The above is to illustrate the characteristics of the present invention by means of the embodiments, and its purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, rather than limit the scope of the patent of the present invention. Therefore, all others do not depart from the present invention. Equivalent modification or modification completed by the disclosed spirit shall still be included in the protection scope of this case.
Claims (2)
1.一种单闸极多次写入非挥发性内存，其特征在于，包括：1. a kind of single-gate write non-volatile memory multiple times, is characterized in that, comprises: 一P型半导体基底；a P-type semiconductor substrate; 一晶体管，该晶体管设置于该P型半导体基底，该晶体管包括一第一介电层、一第一导电闸极与多个离子掺杂区，该第一介电层位于该P型半导体基底表面，该第一导电闸极迭设于该第一介电层上，该多个离子掺杂区设于该半导体基底内并位于该第一导电闸极的两侧，分别形成源极及汲极，该源极和该汲极的宽度不同；以及A transistor is disposed on the P-type semiconductor substrate, the transistor includes a first dielectric layer, a first conductive gate and a plurality of ion-doped regions, and the first dielectric layer is located on the surface of the P-type semiconductor substrate , the first conductive gate is stacked on the first dielectric layer, and the plurality of ion-doped regions are arranged in the semiconductor substrate and located on both sides of the first conductive gate to form a source electrode and a drain electrode respectively , the source and the drain have different widths; and 一电容结构，该电容结构设置于该P型半导体基底，该电容结构利用该汲极的边缘作为电容来控制一浮动闸极，且该汲极与该浮动闸极中间包含一轻掺杂区，该轻掺杂区与该多个离子掺杂区具有同型的离子，并形成该非挥发性内存的一单浮接闸极。a capacitor structure, the capacitor structure is disposed on the P-type semiconductor substrate, the capacitor structure uses the edge of the drain as a capacitor to control a floating gate, and a lightly doped region is included between the drain and the floating gate, The lightly doped region and the plurality of ion-doped regions have ions of the same type, and form a single floating gate of the non-volatile memory. 2.一种单闸极多次写入非挥发性内存的操作方法，该非挥发性内存包括一P型半导体基底、一晶体管与一电容结构，该晶体管设置于该P型半导体基底，该晶体管包括一第一介电层、一第一导电闸极与多个离子掺杂区，该第一介电层位于该P型半导体基底表面，该第一导电闸极迭设于该第一介电层上，该多个离子掺杂区设于该半导体基底内并位于该第一导电闸极的两侧，分别形成源极及汲极，且该源极和该汲极的宽度不同，该电容结构利用该汲极的边缘作为电容来控制一浮动闸极，且该汲极与该浮动闸极中间包含一轻掺杂区，该轻掺杂区与该多个离子掺杂区具有同型的离子，并形成该非挥发性内存的一单浮接闸极，其特征在于，该操作方法包括以下步骤：2. A method of operating a single-gate multi-write non-volatile memory, the non-volatile memory comprising a P-type semiconductor substrate, a transistor and a capacitor structure, the transistor is disposed on the P-type semiconductor substrate, the transistor It includes a first dielectric layer, a first conductive gate and a plurality of ion doping regions, the first dielectric layer is located on the surface of the P-type semiconductor substrate, and the first conductive gate is stacked on the first dielectric On the layer, the plurality of ion-doped regions are arranged in the semiconductor substrate and located on both sides of the first conductive gate, respectively forming a source electrode and a drain electrode, and the width of the source electrode and the drain electrode are different, and the capacitance The structure uses the edge of the drain as a capacitor to control a floating gate, and a lightly doped region is included between the drain and the floating gate, and the lightly doped region and the plurality of ion-doped regions have ions of the same type , and form a single floating gate of the non-volatile memory, characterized in that the operation method includes the following steps: 于该P型半导体基底、该源极与该汲极上分别施加一基底电压Vsub、一源极电压Vs及一汲极电压Vd，并满足下列条件：A substrate voltage V sub , a source voltage V s and a drain voltage V d are respectively applied to the P-type semiconductor substrate, the source electrode and the drain electrode, and the following conditions are met: 写入时：When writing: a.Vsub＝接地(0)；及aV sub = ground (0); and b.Vd＝Vs＝高压(HV)；或bV d = V s = high voltage (HV); or Vd＝高压(HV)，且Vs＝中压(MV)或低压(LV)；或V d = high voltage (HV) and V s = medium voltage (MV) or low voltage (LV); or Vd＝中压(MV)，且Vs＝低压(LV)或接地(0)。V d = medium voltage (MV), and V s = low voltage (LV) or ground (0). 抹除时：When erasing: a.Vsub＝接地(0)；及aV sub = ground (0); and b.Vd＝高压(HV)，且Vs＝接地(0)；或bV d = high voltage (HV), and V s = ground (0); or Vd＝高压(HV)，且Vs＝浮接；或V d = high voltage (HV), and V s = floating; or Vs＝高压(HV)，且Vd＝接地(0)；或V s = high voltage (HV), and V d = ground (0); or Vs＝高压(HV)，且Vd＝浮接。V s = high voltage (HV), and V d = floating.
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