CN112073065B - Millimeter wave sub-sampling DDS (direct digital synthesizer) mixing decimal frequency division phase-locked loop structure - Google Patents

本发明公开了一种毫米波亚采样DDS混频小数分频锁相环结构，包括：缓冲器、第一亚采样鉴相器PD1、第二亚采样鉴相器PD2、DDS、DAC、乘法器、电压电流转换电路、低通滤波器、第一反相器链F1、第二反相器链F2、分频器和压控振荡器。本发明在采样输出过后再进行混频，需要的DDS输出频率大大降低，降低了功耗的同时，可以达到很好的线性度和很低的功耗。本发明的特点是DDS输出信号频率高分辨率特性不受锁相环影响，锁相环使频率合成器可以以最小频率步进在较宽频率范围内跳变，DDS则提供在较窄频率范围可以以很小频率步进跳变的能力。因此其宽带变频速度取决于锁相环环路锁定时间，环路锁定后的窄带变频速度则取决于DDS的变频时间。

The invention discloses a millimeter-wave sub-sampling DDS mixing fractional frequency-division phase-locked loop structure, comprising: a buffer, a first sub-sampling phase detector PD1, a second sub-sampling phase detector PD2, a DDS, a DAC, and a multiplier , a voltage-current conversion circuit, a low-pass filter, a first inverter chain F1, a second inverter chain F2, a frequency divider and a voltage-controlled oscillator. The present invention carries out frequency mixing after sampling output, and the required DDS output frequency is greatly reduced, while reducing power consumption, good linearity and very low power consumption can be achieved. The feature of the present invention is that the frequency high-resolution characteristic of the DDS output signal is not affected by the phase-locked loop. The ability to step-hop at very small frequencies. Therefore, its broadband frequency conversion speed depends on the phase-locked loop loop locking time, and the narrow-band frequency conversion speed after the loop is locked depends on the DDS frequency conversion time.

一种毫米波亚采样DDS混频小数分频锁相环结构A millimeter-wave sub-sampling DDS mixing fractional frequency division phase-locked loop structure

技术领域technical field

本发明属于模数混合集成电路技术领域，具体涉及一种毫米波亚采样DDS混频小数分频锁相环结构。The invention belongs to the technical field of analog-digital hybrid integrated circuits, and in particular relates to a millimeter-wave sub-sampling DDS frequency mixing fractional frequency division phase-locked loop structure.

背景技术Background technique

锁相环(PLL，Phase Locked Loop)就是锁定相位的反馈环路，它是一种典型的反馈控制电路。它利用外部输入的参考信号控制环路内部振荡信号的频率和相位。实现输出信号频率对输入信号频率的自动跟踪，一般用于闭环跟踪电路。随着5G的发展，业界对锁相环的频率和相位噪声要求越来越高。较差的杂散和相位噪声会导致相邻通道信号的频谱混叠，降低信噪比。传统的鉴频鉴相电荷泵锁相环中的杂散主要来自于电荷泵充放电电流的失配。A phase locked loop (PLL, Phase Locked Loop) is a phase locked feedback loop, which is a typical feedback control circuit. It uses an externally input reference signal to control the frequency and phase of the internal oscillation signal of the loop. Realize automatic tracking of output signal frequency to input signal frequency, generally used in closed-loop tracking circuit. With the development of 5G, the industry has higher and higher requirements for the frequency and phase noise of the phase-locked loop. Poor spurious and phase noise can cause spectral aliasing of adjacent channel signals, reducing the signal-to-noise ratio. The spurs in the traditional phase-frequency and phase-detection charge-pump phase-locked loop mainly come from the mismatch of the charging and discharging current of the charge pump.

请参见图1，图1是现有技术提供的一种典型的锁相环的电路结构示意图，图1的锁相环主要模块包括鉴相器(PD，Phase Detector)、环路的低通滤波器和压控振荡器(VCO，Voltage-Controlled Oscillator)。鉴相器具有两个输入信号，分别是参考信号以及压控振荡器的输出信号。鉴相器把参考信号和输出信号的相位差信号转换成电压信号，并将电压信号送到低通滤波器里，低通滤波器滤除掉高频杂波后剩下的就是压控振荡器的控制信号。因此，锁相环的输出信号经过分频后不断地与参考信号进行对比，然后改变压控振荡器的振荡频率，直到两个信号的频率相同，锁相环就进入了锁定状态。并且在锁定状态，由于外部的干扰等等造成的压控振荡器输出发生变化也会及时反馈到压控振荡器的控制电压上及时改正，最终得到一个稳定的输出信号，相位噪声就是锁相环进入了锁定状态后相位的抖动，是锁相环很重要的一个性能指标。Please refer to Fig. 1, Fig. 1 is a schematic diagram of the circuit structure of a typical PLL provided by the prior art, the main modules of the PLL in Fig. 1 include a phase detector (PD, Phase Detector), a low-pass filter of the loop and Voltage-Controlled Oscillator (VCO, Voltage-Controlled Oscillator). The phase detector has two input signals, namely the reference signal and the output signal of the voltage controlled oscillator. The phase detector converts the phase difference signal between the reference signal and the output signal into a voltage signal, and sends the voltage signal to the low-pass filter. After the low-pass filter filters out high-frequency clutter, the voltage-controlled oscillator is left control signal. Therefore, the output signal of the phase-locked loop is continuously compared with the reference signal after frequency division, and then the oscillation frequency of the voltage-controlled oscillator is changed until the frequency of the two signals is the same, and the phase-locked loop enters the locked state. And in the locked state, changes in the output of the voltage-controlled oscillator due to external interference, etc. will also be fed back to the control voltage of the voltage-controlled oscillator in time for correction, and finally a stable output signal is obtained. Phase noise is the phase-locked loop The phase jitter after entering the locked state is a very important performance index of the phase-locked loop.

DDS(Direct Digital Synthesis，直接数字式频率合成器)具有高分辨率、高速捷变频、相位变化连续等诸多优点。但其合成信号频率较低，宽带无杂散动态范围指标不佳，而以锁相环电路为核心的间接频率合成技术具有合成信号频率高、信号相位噪声为鉴相信号相位噪声和VCO信号相位噪声的合成的特点，但在频率分辨率、变频速度等指标上劣于DDS。更重要的是，单独使用间接频率合成方案往往无法兼顾高频率分辨率，低相位噪声和杂散，捷变频等重要性能指标。而DDS+PLL方案将直接数字频率合成与间接频率合成相结合，往往能够达到单独使用DDS或锁相环技术均难以企及的效果。DDS (Direct Digital Synthesis, direct digital frequency synthesizer) has many advantages such as high resolution, high-speed frequency agility, and continuous phase change. However, the synthesized signal frequency is low, and the broadband spurious-free dynamic range index is not good, while the indirect frequency synthesis technology with the phase-locked loop circuit as the core has the advantages of high synthesized signal frequency, signal phase noise is the phase noise of the phase detection signal and the phase noise of the VCO signal Noise synthesis characteristics, but inferior to DDS in terms of frequency resolution, frequency conversion speed and other indicators. More importantly, the indirect frequency synthesis scheme alone often cannot take into account important performance indicators such as high frequency resolution, low phase noise and spurs, and frequency agility. The DDS+PLL scheme combines direct digital frequency synthesis and indirect frequency synthesis, and can often achieve effects that are difficult to achieve by using DDS or phase-locked loop technology alone.

传统的锁相环中，为了进行小数分频。有TDC(时间数字转换器，Time to DigitalConvertor)结构、delta-sigma结构等。TDC结构利用相位累加的效果，使得采样时钟可以实现相位累加，达到小数采样的效果，但是此种结构的最小分辨精度受到工艺的影响，相位累加的过程中容易引入相位误差。Delta-sigma结构利用分频器在一定的周期内生成不同整数分频比的输出达到平均输出是小数分频的效果，此种方案的输出频率线性度不好频率精度低。传统的混频器方案在VCO的输出处进行混频，需要的DDS输出频率非常高，功耗大。In the traditional phase-locked loop, in order to carry out fractional frequency division. There are TDC (time to digital converter, Time to Digital Convertor) structure, delta-sigma structure and so on. The TDC structure uses the effect of phase accumulation, so that the sampling clock can achieve phase accumulation and achieve the effect of fractional sampling. However, the minimum resolution accuracy of this structure is affected by the process, and phase errors are easily introduced during the phase accumulation process. The Delta-sigma structure uses a frequency divider to generate outputs with different integer frequency division ratios within a certain period to achieve the effect that the average output is a fractional frequency division. The output frequency linearity of this scheme is not good and the frequency accuracy is low. The traditional mixer solution performs mixing at the output of the VCO, which requires a very high output frequency of the DDS and consumes a lot of power.

发明内容Contents of the invention

为了解决现有技术中存在的上述问题，本发明提供了一种毫米波亚采样DDS混频小数分频锁相环结构。本发明要解决的技术问题通过以下技术方案实现：In order to solve the above-mentioned problems in the prior art, the present invention provides a millimeter-wave sub-sampling DDS mixing fractional frequency-division phase-locked loop structure. The technical problem to be solved in the present invention is realized through the following technical solutions:

一种毫米波亚采样DDS混频小数分频锁相环结构，包括：缓冲器、第一亚采样鉴相器PD1、第二亚采样鉴相器PD2、DDS、DAC、乘法器、电压电流转换电路、低通滤波器、第一反相器链F1、第二反相器链F2、分频器和压控振荡器，其中，A millimeter-wave sub-sampling DDS mixing fractional frequency-division phase-locked loop structure, including: buffer, first sub-sampling phase detector PD1, second sub-sampling phase detector PD2, DDS, DAC, multiplier, voltage-current conversion circuit, low pass filter, first inverter chain F1, second inverter chain F2, frequency divider and voltage controlled oscillator, wherein,

所述缓冲器的第一输出端、第二输出端分别连接所述DDS的第一输入端和第二输入端，所述缓冲器的第一输出端、第二输出端还分别连接所述第一亚采样鉴相器PD1的第一输入端和第二输入端，且所述缓冲器的第一输出端、第二输出端还分别连接所述第二亚采样鉴相器PD2的第一输入端和第二输入端；The first output end and the second output end of the buffer are respectively connected to the first input end and the second input end of the DDS, and the first output end and the second output end of the buffer are respectively connected to the first The first input end and the second input end of a sub-sampling phase detector PD1, and the first output end and the second output end of the buffer are respectively connected to the first input of the second sub-sampling phase detector PD2 terminal and the second input terminal;

所述DDS的第一输出端、第二输出端分别连接所述DAC的第一输入端和第二输入端，所述DAC的第一输出端、第二输出端、第三输出端和第四输出端均连接所述乘法器，所述第一亚采样鉴相器PD1的第一输出端和第二输出端、所述第二亚采样鉴相器PD2的第一输出端和第二输出端均连接所述乘法器；The first output terminal and the second output terminal of the DDS are respectively connected to the first input terminal and the second input terminal of the DAC, and the first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the DAC The output terminals are all connected to the multiplier, the first output terminal and the second output terminal of the first subsampling phase detector PD1, the first output terminal and the second output terminal of the second subsampling phase detector PD2 are connected to the multiplier;

所述乘法器的第一输出端和第二输出端连接所述电压电流转换电路，所述电压电流转换电路的输出端通过所述低通滤波器连接至所述压控振荡器，所述压控振荡器的第一输出端通过所述第一反相器链F1连接至所述分频器的第一输入端，所述压控振荡器的第二输出端通过第二反相器链F2连接至所述分频器的第二输入端，所述分频器的第一输出端和第二输出端均连接至所述第一亚采样鉴相器PD1的控制端，所述分频器的第三输出端和第四输出端均连接至所述第二亚采样鉴相器PD2的控制端。The first output terminal and the second output terminal of the multiplier are connected to the voltage-current conversion circuit, the output terminal of the voltage-current conversion circuit is connected to the voltage-controlled oscillator through the low-pass filter, and the voltage-current conversion circuit is connected to the voltage-controlled oscillator. The first output terminal of the controlled oscillator is connected to the first input terminal of the frequency divider through the first inverter chain F1, and the second output terminal of the voltage controlled oscillator is connected through the second inverter chain F2 Connected to the second input end of the frequency divider, the first output end and the second output end of the frequency divider are connected to the control end of the first sub-sampling phase detector PD1, the frequency divider Both the third output terminal and the fourth output terminal of are connected to the control terminal of the second sub-sampling phase detector PD2.

在本发明的一个实施例中，所述第一亚采样鉴相器PD1包括晶体管M1、晶体管M2、晶体管M3、晶体管M4、晶体管M5、晶体管M6、电容C3和电容C4，其中，In an embodiment of the present invention, the first sub-sampling phase detector PD1 includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a capacitor C3, and a capacitor C4, wherein,

所述缓冲器的第一输出端连接所述晶体管M1的源极、所述晶体管M4的源极，所述缓冲器的第二输出端连接所述晶体管M3的源极和所述晶体管M5的源极，所述晶体管M1的漏极连接所述晶体管M3的漏极、所述晶体管M2的源极，所述晶体管M5的漏极连接所述晶体管M4的漏极、所述晶体管M6的源极，所述晶体管M2的漏极连接所述电容C3的第一端和所述乘法器，所述电容C3的第二端连接接地端，所述晶体管M2的源极还连接所述晶体管M2的漏极，所述晶体管M3的栅极和所述晶体管M4的栅极连接接地端，所述晶体管M6的漏极连接所述电容C4的第一端和所述乘法器，所述电容C4的第二端连接接地端，所述晶体管M6的源极还连接所述晶体管M6的漏极，所述晶体管M1的栅极和所述晶体管M5的栅极连接所述分频器的第一输出端，所述晶体管M2的栅极和所述晶体管M6的栅极连接所述分频器的第二输出端。The first output end of the buffer is connected to the source of the transistor M1 and the source of the transistor M4, and the second output end of the buffer is connected to the source of the transistor M3 and the source of the transistor M5 The drain of the transistor M1 is connected to the drain of the transistor M3 and the source of the transistor M2, the drain of the transistor M5 is connected to the drain of the transistor M4 and the source of the transistor M6, The drain of the transistor M2 is connected to the first terminal of the capacitor C3 and the multiplier, the second terminal of the capacitor C3 is connected to the ground terminal, and the source of the transistor M2 is also connected to the drain of the transistor M2 , the gate of the transistor M3 and the gate of the transistor M4 are connected to the ground terminal, the drain of the transistor M6 is connected to the first terminal of the capacitor C4 and the multiplier, and the second terminal of the capacitor C4 connected to the ground terminal, the source of the transistor M6 is also connected to the drain of the transistor M6, the gate of the transistor M1 and the gate of the transistor M5 are connected to the first output terminal of the frequency divider, the The gate of the transistor M2 and the gate of the transistor M6 are connected to the second output end of the frequency divider.

在本发明的一个实施例中，所述晶体管M2和所述晶体管M6的尺寸为所述晶体管M1和所述晶体管M5的一半，所述晶体管M3和所述晶体管M4的尺寸与所述晶体管M1和所述晶体管M5的尺寸相同。In one embodiment of the present invention, the size of the transistor M2 and the transistor M6 is half that of the transistor M1 and the transistor M5, and the size of the transistor M3 and the transistor M4 is the same as that of the transistor M1 and the transistor M5. The transistors M5 have the same size.

在本发明的一个实施例中，所述第二亚采样鉴相器PD2包括晶体管M7、晶体管M8、晶体管M9、晶体管M10、晶体管M11、晶体管M12、电容C5和电容C6，其中，In an embodiment of the present invention, the second sub-sampling phase detector PD2 includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a capacitor C5, and a capacitor C6, wherein,

所述缓冲器的第一输出端连接所述晶体管M7的源极、所述晶体管M10的源极，所述缓冲器的第二输出端连接所述晶体管M9的源极和所述晶体管M11的源极，所述晶体管M7的漏极连接所述晶体管M9的漏极、所述晶体管M8的源极，所述晶体管M11的漏极连接所述晶体管M10的漏极、所述晶体管M12的源极，所述晶体管M8的漏极连接所述电容C5的第一端和所述乘法器，所述电容C5的第二端连接接地端，所述晶体管M8的源极还连接所述晶体管M8的漏极，所述晶体管M9的栅极和所述晶体管M10的栅极连接接地端，所述晶体管M12的漏极连接所述电容C6的第一端和所述乘法器，所述电容C6的第二端连接接地端，所述晶体管M12的源极还连接所述晶体管M12的漏极，所述晶体管M7的栅极和所述晶体管M11的栅极连接所述分频器的第三输出端，所述晶体管M8的栅极和所述晶体管M12的栅极连接所述分频器的第四输出端。The first output end of the buffer is connected to the source of the transistor M7 and the source of the transistor M10, and the second output end of the buffer is connected to the source of the transistor M9 and the source of the transistor M11 The drain of the transistor M7 is connected to the drain of the transistor M9 and the source of the transistor M8, the drain of the transistor M11 is connected to the drain of the transistor M10 and the source of the transistor M12, The drain of the transistor M8 is connected to the first terminal of the capacitor C5 and the multiplier, the second terminal of the capacitor C5 is connected to the ground terminal, and the source of the transistor M8 is also connected to the drain of the transistor M8 , the gate of the transistor M9 and the gate of the transistor M10 are connected to the ground terminal, the drain of the transistor M12 is connected to the first terminal of the capacitor C6 and the multiplier, and the second terminal of the capacitor C6 connected to the ground terminal, the source of the transistor M12 is also connected to the drain of the transistor M12, the gate of the transistor M7 and the gate of the transistor M11 are connected to the third output terminal of the frequency divider, the The gate of the transistor M8 and the gate of the transistor M12 are connected to the fourth output terminal of the frequency divider.

在本发明的一个实施例中，所述晶体管M8和所述晶体管M12的尺寸为所述晶体管M7和所述晶体管M11的一半，所述晶体管M9和所述晶体管M10的尺寸与所述晶体管M7和所述晶体管M11的尺寸相同。In one embodiment of the present invention, the size of the transistor M8 and the transistor M12 is half that of the transistor M7 and the transistor M11, and the size of the transistor M9 and the transistor M10 is the same as that of the transistor M7 and the transistor M11. The sizes of the transistors M11 are the same.

在本发明的一个实施例中，所述乘法器包括晶体管M13、晶体管M14、晶体管M15、晶体管M16、晶体管M17、晶体管M18、晶体管M19、晶体管M20、晶体管M21、晶体管M22、晶体管M23、晶体管M24、电容C7、电容C8、电阻R2和电阻R3，其中，In one embodiment of the present invention, the multiplier includes a transistor M13, a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a transistor M20, a transistor M21, a transistor M22, a transistor M23, a transistor M24, capacitor C7, capacitor C8, resistor R2 and resistor R3, wherein,

所述晶体管M13的栅极、所述晶体管M17的栅极连接所述DAC的第一输出端，所述晶体管M14的栅极、所述晶体管M16的栅极连接所述DAC的第二输出端，所述晶体管M15的栅极和所述晶体管M18的栅极连接所述第一亚采样鉴相器PD1，所述晶体管M13的源极连接所述晶体管M14的源极、所述晶体管M15的漏极，所述晶体管M13的漏极连接所述电容C7的第一端、所述电阻R2的第一端，所述晶体管M14的漏极连接所述电容C8的第一端、所述电阻R3的第一端，所述晶体管M15的源极连接接地端，所述晶体管M16的源极连接所述晶体管M17的源极、所述晶体管M18的漏极，所述晶体管M16的漏极连接所述电容C7的第一端、所述电阻R2的第一端，所述晶体管M17的漏极连接所述电容C8的第一端、所述电阻R3的第一端，所述晶体管M18的源极接地；The gate of the transistor M13 and the gate of the transistor M17 are connected to the first output terminal of the DAC, the gate of the transistor M14 and the gate of the transistor M16 are connected to the second output terminal of the DAC, The gate of the transistor M15 and the gate of the transistor M18 are connected to the first sub-sampling phase detector PD1, the source of the transistor M13 is connected to the source of the transistor M14, and the drain of the transistor M15 , the drain of the transistor M13 is connected to the first terminal of the capacitor C7 and the first terminal of the resistor R2, the drain of the transistor M14 is connected to the first terminal of the capacitor C8 and the first terminal of the resistor R3 At one end, the source of the transistor M15 is connected to the ground terminal, the source of the transistor M16 is connected to the source of the transistor M17, the drain of the transistor M18, and the drain of the transistor M16 is connected to the capacitor C7 The first terminal of the resistor R2, the drain of the transistor M17 is connected to the first terminal of the capacitor C8 and the first terminal of the resistor R3, and the source of the transistor M18 is grounded;

所述晶体管M19的栅极、所述晶体管M23的栅极连接所述DAC的第三输出端，所述晶体管M20的栅极、所述晶体管M22的栅极连接所述DAC的第四输出端，所述晶体管M21的栅极和所述晶体管M24的栅极连接所述第二亚采样鉴相器PD2，所述晶体管M19的源极连接所述晶体管M20的源极、所述晶体管M21的漏极，所述晶体管M19的漏极连接所述电容C7的第一端、所述电阻R2的第一端，所述晶体管M20的漏极连接所述电容C8的第一端、所述电阻R3的第一端，所述晶体管M21的源极连接接地端，所述晶体管M22的源极连接所述晶体管M23的源极、所述晶体管M24的漏极，所述晶体管M22的漏极连接所述电容C7的第一端、所述电阻R2的第一端，所述晶体管M23的漏极连接所述电容C8的第一端、所述电阻R3的第一端，所述晶体管M24的源极接地；The gate of the transistor M19 and the gate of the transistor M23 are connected to the third output terminal of the DAC, the gate of the transistor M20 and the gate of the transistor M22 are connected to the fourth output terminal of the DAC, The gate of the transistor M21 and the gate of the transistor M24 are connected to the second sub-sampling phase detector PD2, and the source of the transistor M19 is connected to the source of the transistor M20 and the drain of the transistor M21 , the drain of the transistor M19 is connected to the first terminal of the capacitor C7 and the first terminal of the resistor R2, the drain of the transistor M20 is connected to the first terminal of the capacitor C8 and the first terminal of the resistor R3 At one end, the source of the transistor M21 is connected to the ground terminal, the source of the transistor M22 is connected to the source of the transistor M23, the drain of the transistor M24, and the drain of the transistor M22 is connected to the capacitor C7 The first terminal of the resistor R2, the drain of the transistor M23 is connected to the first terminal of the capacitor C8 and the first terminal of the resistor R3, and the source of the transistor M24 is grounded;

所述电容C7的第二端和所述电容C8的第二端连接接地端，所述电阻R2的第二端和所述电阻R3的第二端连接电源端，所述电容C7的第一端和所述电阻R2的第一端还连接所述电压电流转换电路的第一输入端，所述电容C8的第一端和所述电阻R3的第一端还连接所述电压电流转换电路的第二输入端。The second terminal of the capacitor C7 and the second terminal of the capacitor C8 are connected to the ground terminal, the second terminal of the resistor R2 and the second terminal of the resistor R3 are connected to the power supply terminal, and the first terminal of the capacitor C7 The first end of the resistor R2 is also connected to the first input end of the voltage-current conversion circuit, and the first end of the capacitor C8 and the first end of the resistor R3 are also connected to the first input end of the voltage-current conversion circuit. Two input terminals.

在本发明的一个实施例中，所述电压电流转换电路包括晶体管M25、晶体管M26、晶体管M27、晶体管M28、晶体管M29、晶体管M30、晶体管M31、晶体管M32和晶体管M33，其中，In one embodiment of the present invention, the voltage-current conversion circuit includes a transistor M25, a transistor M26, a transistor M27, a transistor M28, a transistor M29, a transistor M30, a transistor M31, a transistor M32, and a transistor M33, wherein,

所述乘法器的第一输出端连接所述晶体管M25的栅极，所述乘法器的第二输出端连接所述晶体管M26的栅极，所述晶体管M25的源极连接所述晶体管M26的源极和所述晶体管M27的漏极，所述晶体管M25的漏极连接所述晶体管M28的漏极、所述晶体管M28的栅极、所述晶体管M31的栅极，所述晶体管M26的漏极连接所述晶体管M29的漏极、所述晶体管M29的栅极、所述晶体管M30的栅极，所述晶体管M27的栅极连接偏置电压端，所述晶体管M27的源极连接接地端，所述晶体管M30的漏极连接所述晶体管M32的漏极、所述晶体管M32的栅极、所述晶体管M33的栅极，所述晶体管M31的漏极连接所述晶体管M33的漏极和所述低通滤波器，所述晶体管M32的源极和所述晶体管M33的源极连接接地端，所述晶体管M28、所述晶体管M29、所述晶体管M30、所述晶体管M31连接电源端。The first output end of the multiplier is connected to the gate of the transistor M25, the second output end of the multiplier is connected to the gate of the transistor M26, and the source of the transistor M25 is connected to the source of the transistor M26. pole and the drain of the transistor M27, the drain of the transistor M25 is connected to the drain of the transistor M28, the gate of the transistor M28, and the gate of the transistor M31, and the drain of the transistor M26 is connected to The drain of the transistor M29, the gate of the transistor M29, the gate of the transistor M30, the gate of the transistor M27 is connected to the bias voltage terminal, the source of the transistor M27 is connected to the ground terminal, the The drain of the transistor M30 is connected to the drain of the transistor M32, the gate of the transistor M32, and the gate of the transistor M33, and the drain of the transistor M31 is connected to the drain of the transistor M33 and the low-pass In the filter, the source of the transistor M32 and the source of the transistor M33 are connected to a ground terminal, and the transistor M28, the transistor M29, the transistor M30, and the transistor M31 are connected to a power supply terminal.

在本发明的一个实施例中，所述低通滤波器包括电阻R1、电容C1和电容C2，其中，In one embodiment of the present invention, the low-pass filter includes a resistor R1, a capacitor C1, and a capacitor C2, wherein,

所述电阻R1的第一端、所述电容C2的第一端连接所述电压电流转换电路的输出端和所述压控振荡器的输入端，所述电阻R1的第二端连接所述电容C1的第一端，所述电容C1的第二端和所述电容C2的第二端连接接地端。The first end of the resistor R1 and the first end of the capacitor C2 are connected to the output end of the voltage-current conversion circuit and the input end of the voltage-controlled oscillator, and the second end of the resistor R1 is connected to the capacitor The first end of C1, the second end of the capacitor C1 and the second end of the capacitor C2 are connected to the ground.

在本发明的一个实施例中，所述压控振荡器包括晶体管M33、晶体管M34、晶体管M35、晶体管M36、电感L、可调电容C_A1、可调电容C_A2、电容阵列，其中，In an embodiment of the present invention, the voltage-controlled oscillator includes a transistor M33, a transistor M34, a transistor M35, a transistor M36, an inductor L, an adjustable capacitor C _A1 , an adjustable capacitor C _A2 , and a capacitor array, wherein,

所述电压电流转换电路的输出端连接所述可调电容C_A1的第一端、所述可调电容C_A2的第一端，所述可调电容C_A1的第二端连接所述晶体管M33的漏极、所述电感L的第一端、所述晶体管M34的栅极、所述电容阵列的第一端、所述晶体管M35的漏极、所述晶体管M36的栅极、所述第一反相器链F1，所述可调电容C_A2的第二端连接所述晶体管M34的漏极、所述电感L的第二端、所述晶体管M33的栅极、所述电容阵列的第二端、所述晶体管M36的漏极、所述晶体管M35的栅极、所述第二反相器链F2，所述晶体管M33的源极和所述晶体管M34的源极通过恒流源连接电源端，所述晶体管M35的源极和所述晶体管M36的源极连接接地端。The output end of the voltage-current conversion circuit is connected to the first end of the adjustable capacitor C _A1 and the first end of the adjustable capacitor C _A2 , and the second end of the adjustable capacitor C _A1 is connected to the transistor M33 The drain of the inductor L, the first terminal of the inductor L, the gate of the transistor M34, the first terminal of the capacitor array, the drain of the transistor M35, the gate of the transistor M36, the first Inverter chain F1, the second end of the adjustable capacitor C _A2 is connected to the drain of the transistor M34, the second end of the inductor L, the gate of the transistor M33, the second end of the capacitor array Terminal, the drain of the transistor M36, the gate of the transistor M35, the second inverter chain F2, the source of the transistor M33 and the source of the transistor M34 are connected to the power supply terminal through a constant current source , the source of the transistor M35 and the source of the transistor M36 are connected to the ground terminal.

本发明的有益效果：Beneficial effects of the present invention:

本发明在采样输出过后再进行混频，需要的DDS输出频率大大降低，降低了功耗的同时，可以达到很好的线性度和很低的功耗。本发明的特点是DDS输出信号频率高分辨率特性不受锁相环影响，锁相环使频率合成器可以以最小频率步进在较宽频率范围内跳变，DDS则提供在较窄频率范围可以以很小频率步进跳变的能力。因此其宽带变频速度取决于锁相环环路锁定时间，环路锁定后的窄带变频速度则取决于DDS的变频时间。本发明的实现难点在于环内混频器输出信号的滤波处理，所以为了达到更好的滤波效果，本发明利用了IQ调制的方式，使得乘法器输出的频率分量中的高频分量被大大滤除。The present invention carries out frequency mixing after sampling output, and the required DDS output frequency is greatly reduced, while reducing power consumption, good linearity and very low power consumption can be achieved. The feature of the present invention is that the frequency high-resolution characteristic of the DDS output signal is not affected by the phase-locked loop. The ability to step-hop at very small frequencies. Therefore, its broadband frequency conversion speed depends on the locking time of the phase-locked loop loop, and the narrow-band frequency conversion speed after the loop is locked depends on the frequency conversion time of DDS. The difficulty in the realization of the present invention lies in the filtering process of the output signal of the mixer in the loop, so in order to achieve a better filtering effect, the present invention utilizes the IQ modulation method, so that the high frequency components in the frequency components output by the multiplier are greatly filtered remove.

以下将结合附图及实施例对本发明做进一步详细说明。The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

附图说明Description of drawings

图1是现有技术提供的一种典型的锁相环的电路结构示意图；Fig. 1 is a schematic circuit structure diagram of a typical phase-locked loop provided by the prior art;

图2是本发明实施例提供的一种毫米波亚采样DDS混频小数分频锁相环结构的电路结构示意图；Fig. 2 is a schematic circuit structure diagram of a millimeter-wave sub-sampling DDS mixing fractional frequency division phase-locked loop structure provided by an embodiment of the present invention;

图3是本发明实施例提供的一种第一亚采样鉴相器的电路结构示意图；3 is a schematic diagram of a circuit structure of a first sub-sampling phase detector provided by an embodiment of the present invention;

图4是本发明实施例提供的一种第二亚采样鉴相器的电路结构示意图；Fig. 4 is a schematic circuit structure diagram of a second sub-sampling phase detector provided by an embodiment of the present invention;

图5为本发明实施例提供的一种DAC电路原理图；FIG. 5 is a schematic diagram of a DAC circuit provided by an embodiment of the present invention;

图6是本发明实施例提供的一种乘法器的电路结构示意图；FIG. 6 is a schematic diagram of a circuit structure of a multiplier provided by an embodiment of the present invention;

图7是本发明实施例提供的一种电压电流转换电路的电路结构示意图；Fig. 7 is a schematic circuit structure diagram of a voltage-current conversion circuit provided by an embodiment of the present invention;

图8是本发明实施例提供的一种低通滤波器的电路结构示意图；FIG. 8 is a schematic diagram of a circuit structure of a low-pass filter provided by an embodiment of the present invention;

图9是本发明实施例提供的一种压控振荡器的电路结构示意图。FIG. 9 is a schematic diagram of a circuit structure of a voltage-controlled oscillator provided by an embodiment of the present invention.

具体实施方式Detailed ways

下面结合具体实施例对本发明做进一步详细的描述，但本发明的实施方式不限于此。The present invention will be described in further detail below in conjunction with specific examples, but the embodiments of the present invention are not limited thereto.

实施例一Embodiment one

请参见图2，图2是本发明实施例提供的一种毫米波亚采样DDS混频小数分频锁相环结构的电路结构示意图。本实施例提供一种毫米波亚采样DDS混频小数分频锁相环结构，该锁相环结构包括：缓冲器(即buffer)、第一亚采样鉴相器PD1、第二亚采样鉴相器PD2、DDS(直接数字式频率合成器)、DAC(数字模拟转换器)、乘法器(即MIX)、电压电流转换电路(即V/I)、低通滤波器、第一反相器链F1、第二反相器链F2、分频器(即/N)和压控振荡器(即VCO)，其中，Please refer to FIG. 2 . FIG. 2 is a schematic diagram of a circuit structure of a millimeter-wave sub-sampling DDS mixing fractional frequency-division phase-locked loop structure provided by an embodiment of the present invention. This embodiment provides a millimeter-wave sub-sampling DDS fractional frequency-division phase-locked loop structure. The phase-locked loop structure includes: a buffer (ie buffer), a first sub-sampling phase detector PD1, a second sub-sampling phase detector PD2, DDS (direct digital frequency synthesizer), DAC (digital-to-analog converter), multiplier (ie MIX), voltage-current conversion circuit (ie V/I), low-pass filter, first inverter chain F1, second inverter chain F2, frequency divider (ie /N) and voltage controlled oscillator (ie VCO), wherein,

缓冲器的第一输出端、第二输出端分别连接DDS的第一输入端和第二输入端，缓冲器的第一输出端、第二输出端还分别连接第一亚采样鉴相器PD1的第一输入端和第二输入端，且缓冲器的第一输出端、第二输出端还分别连接第二亚采样鉴相器PD2的第一输入端和第二输入端；DDS的第一输出端、第二输出端分别连接DAC的第一输入端和第二输入端，DAC的第一输出端、第二输出端、第三输出端和第四输出端均连接乘法器，第一亚采样鉴相器PD1的第一输出端和第二输出端、第二亚采样鉴相器PD2的第一输出端和第二输出端均连接乘法器；乘法器的第一输出端和第二输出端连接电压电流转换电路，电压电流转换电路的输出端通过低通滤波器连接至压控振荡器，压控振荡器的第一输出端通过第一反相器链F1连接至分频器的第一输入端，压控振荡器的第二输出端通过第二反相器链F2连接至分频器的第二输入端，分频器的第一输出端和第二输出端均连接至第一亚采样鉴相器PD1的控制端，分频器的第三输出端和第四输出端均连接至第二亚采样鉴相器PD2的控制端。The first output end and the second output end of the buffer are respectively connected to the first input end and the second input end of the DDS, and the first output end and the second output end of the buffer are respectively connected to the first sub-sampling phase detector PD1 The first input terminal and the second input terminal, and the first output terminal and the second output terminal of the buffer are also respectively connected to the first input terminal and the second input terminal of the second sub-sampling phase detector PD2; the first output of the DDS end, the second output end are respectively connected to the first input end and the second input end of DAC, and the first output end, the second output end, the third output end and the fourth output end of DAC are all connected to the multiplier, and the first sub-sampling The first output end and the second output end of the phase detector PD1, the first output end and the second output end of the second sub-sampling phase detector PD2 are all connected to the multiplier; the first output end and the second output end of the multiplier The voltage-current conversion circuit is connected, the output terminal of the voltage-current conversion circuit is connected to the voltage-controlled oscillator through a low-pass filter, and the first output terminal of the voltage-controlled oscillator is connected to the first frequency divider through the first inverter chain F1 The input terminal, the second output terminal of the voltage controlled oscillator is connected to the second input terminal of the frequency divider through the second inverter chain F2, and the first output terminal and the second output terminal of the frequency divider are connected to the first sub- The control terminal of the sampling phase detector PD1, the third output terminal and the fourth output terminal of the frequency divider are all connected to the control terminal of the second sub-sampling phase detector PD2.

通过本实施例所提出的新型锁相环结构可知，压控振荡器的输出信号经分频后输出IQ两路差分采样的时钟信号，然后对参考信号进行采样，输出两路IQ差分差频输出信号，两路IQ差频信号与DDS产生的IQ差分信号进行混频，最终通过电荷泵(即电压电流转换电路)和低通滤波器对压控振荡器进行控制，形成锁相环环路。例如，当压控振荡器输出频率为18GHz时，128分频过后差生两路频率为140.625MHz的IQ信号，对150MHz的参考信号进行采样，输出9.375MHz的差频信号。DDS/DAC通过150MHz的参考信号产生一个频率为9.375MHz的信号与采样输出信号进行混频，最终通过电荷泵和低通滤波器控制压控振荡器。所以，整个锁相环利用150MHz的参考时钟输出了18GHz的输出信号，达到了小数分频的效果。Through the new phase-locked loop structure proposed in this embodiment, it can be seen that the output signal of the voltage-controlled oscillator outputs the clock signal of IQ two-way differential sampling after frequency division, and then samples the reference signal to output two-way IQ differential difference frequency output Signal, two IQ differential frequency signals are mixed with the IQ differential signal generated by DDS, and finally the voltage-controlled oscillator is controlled by a charge pump (ie, voltage-current conversion circuit) and a low-pass filter to form a phase-locked loop. For example, when the output frequency of the VCO is 18GHz, two IQ signals with a frequency of 140.625MHz are differentially generated after 128 frequency division, the reference signal of 150MHz is sampled, and a difference frequency signal of 9.375MHz is output. DDS/DAC generates a signal with a frequency of 9.375MHz through a 150MHz reference signal to mix with the sampling output signal, and finally controls the voltage-controlled oscillator through a charge pump and a low-pass filter. Therefore, the entire phase-locked loop uses a reference clock of 150MHz to output an output signal of 18GHz, which achieves the effect of fractional frequency division.

在一个具体实施例中，请参见图3，图3是本发明实施例提供的一种第一亚采样鉴相器的电路结构示意图，通过图3可知，第一亚采样鉴相器PD1包括晶体管M1、晶体管M2、晶体管M3、晶体管M4、晶体管M5、晶体管M6、电容C3和电容C4，其中，缓冲器的第一输出端连接晶体管M1的源极、晶体管M4的源极，缓冲器的第二输出端连接晶体管M3的源极和晶体管M5的源极，晶体管M1的漏极连接晶体管M3的漏极、晶体管M2的源极，晶体管M5的漏极连接晶体管M4的漏极、晶体管M6的源极，晶体管M2的漏极连接电容C3的第一端和乘法器，电容C3的第二端连接接地端，晶体管M2的源极还连接晶体管M2的漏极，晶体管M3的栅极和晶体管M4的栅极连接接地端，晶体管M6的漏极连接电容C4的第一端和乘法器，电容C4的第二端连接接地端，晶体管M6的源极还连接晶体管M6的漏极，晶体管M1的栅极和所述晶体管M5的栅极连接分频器的第一输出端，晶体管M2的栅极和晶体管M6的栅极连接分频器的第二输出端。In a specific embodiment, please refer to FIG. 3. FIG. 3 is a schematic diagram of a circuit structure of a first sub-sampling phase detector provided by an embodiment of the present invention. It can be seen from FIG. 3 that the first sub-sampling phase detector PD1 includes a transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, capacitor C3, and capacitor C4, wherein the first output terminal of the buffer is connected to the source of the transistor M1 and the source of the transistor M4, and the second output of the buffer is The output terminal is connected to the source of the transistor M3 and the source of the transistor M5, the drain of the transistor M1 is connected to the drain of the transistor M3, the source of the transistor M2, and the drain of the transistor M5 is connected to the drain of the transistor M4 and the source of the transistor M6 , the drain of the transistor M2 is connected to the first terminal of the capacitor C3 and the multiplier, the second terminal of the capacitor C3 is connected to the ground terminal, the source of the transistor M2 is also connected to the drain of the transistor M2, the gate of the transistor M3 and the gate of the transistor M4 The pole is connected to the ground terminal, the drain of the transistor M6 is connected to the first terminal of the capacitor C4 and the multiplier, the second terminal of the capacitor C4 is connected to the ground terminal, the source of the transistor M6 is also connected to the drain of the transistor M6, and the gate of the transistor M1 is connected to the multiplier. The gate of the transistor M5 is connected to the first output terminal of the frequency divider, and the gates of the transistor M2 and the transistor M6 are connected to the second output terminal of the frequency divider.

进一步地，晶体管M1、晶体管M2、晶体管M3、晶体管M4、晶体管M5、晶体管M6均为NMOS。Further, the transistor M1 , the transistor M2 , the transistor M3 , the transistor M4 , the transistor M5 and the transistor M6 are all NMOS.

进一步地，晶体管M2和晶体管M6的尺寸为晶体管M1和晶体管M5的一半，晶体管M3和晶体管M4的尺寸与晶体管M1和晶体管M5的尺寸相同。Further, the size of the transistor M2 and the transistor M6 is half of that of the transistor M1 and the transistor M5, and the size of the transistor M3 and the transistor M4 is the same as that of the transistor M1 and the transistor M5.

在本实施例中，CLK_NI和CLK_PI是一对差分信号，当CLK_NI为低时，第一亚采样鉴相器PD1进入采样阶段。当CLK_NI为高时，第一亚采样鉴相器PD1进入保持阶段。第一亚采样鉴相器PD1中的所有晶体管都是N型的。晶体管M1和晶体管M5是一对开关管，分别连接VIN_PI和VIN_NI端口。由于开关管从导通向关断状态切换时，反型层电荷会通过源漏流出，这叫“沟道电荷注入”。为防止电荷直接注入到采样电容上进一步改变采样电容上的电压值，本实施例引入了晶体管M2和晶体管M6作沟道电荷的收集。晶体管M2和晶体管M6的尺寸是晶体管M1和晶体管M5的一半，控制信号与晶体管M1和晶体管M5互补，晶体管M2和晶体管M6的源极与漏极均短接。这样，当晶体管M1和晶体管M5关断时，晶体管M2和晶体管M6导通，晶体管M2和晶体管M6中形成的反型层可以容纳流出的沟道电荷。晶体管M2和晶体管M6还可以抑制时钟馈通。当晶体管M1和晶体管M5截止时，VIN_NI和VIN_PI可能通过源漏电容耦合到采样电容上去，引起采样值不稳定，因此引入晶体管M3、晶体管M4，晶体管M3和晶体管M4的栅极保持接地，晶体管M3和晶体管M4的尺寸与晶体管M1和晶体管M5的尺寸完全一样，因此源漏电容也与开关管一样。因此，当第一亚采样鉴相器PD1进入保持阶段，两差分信号通过相同大小的源漏电容耦合到晶体管M2和晶体管M6的源极，使得晶体管M1、晶体管M3的漏极的等效电容接近于0，影响相互抵消。In this embodiment, CLK_NI and CLK_PI are a pair of differential signals. When CLK_NI is low, the first sub-sampling phase detector PD1 enters the sampling phase. When CLK_NI is high, the first sub-sampling phase detector PD1 enters the hold phase. All transistors in the first sub-sampling phase detector PD1 are of N-type. The transistor M1 and the transistor M5 are a pair of switch tubes, which are respectively connected to the VIN_PI and VIN_NI ports. When the switch tube is switched from on to off, the inversion layer charges will flow out through the source and drain, which is called "channel charge injection". In order to prevent charges from being directly injected into the sampling capacitor to further change the voltage value on the sampling capacitor, this embodiment introduces a transistor M2 and a transistor M6 for channel charge collection. The size of the transistor M2 and the transistor M6 is half of that of the transistor M1 and the transistor M5, the control signal is complementary to the transistor M1 and the transistor M5, and the source and the drain of the transistor M2 and the transistor M6 are both short-circuited. In this way, when the transistor M1 and the transistor M5 are turned off, the transistor M2 and the transistor M6 are turned on, and the inversion layer formed in the transistor M2 and the transistor M6 can accommodate the channel charges flowing out. Transistors M2 and M6 also suppress clock feedthrough. When the transistor M1 and the transistor M5 are turned off, VIN_NI and VIN_PI may be coupled to the sampling capacitor through the source-drain capacitance, causing the sampling value to be unstable, so the transistor M3 and the transistor M4 are introduced, and the gates of the transistor M3 and the transistor M4 are kept grounded, and the transistor M3 The size of the transistor M4 is exactly the same as that of the transistor M1 and the transistor M5, so the source-drain capacitance is also the same as that of the switch tube. Therefore, when the first sub-sampling phase detector PD1 enters the holding phase, the two differential signals are coupled to the sources of the transistor M2 and the transistor M6 through the source-drain capacitance of the same size, so that the equivalent capacitance of the drains of the transistor M1 and the transistor M3 is close to At 0, the effects cancel each other out.

在一个具体实施例中，请参见图4，图4是本发明实施例提供的一种第二亚采样鉴相器的电路结构示意图，通过图4可知，第二亚采样鉴相器PD2包括晶体管M7、晶体管M8、晶体管M9、晶体管M10、晶体管M11、晶体管M12、电容C5和电容C6，其中，缓冲器的第一输出端连接晶体管M7的源极、晶体管M10的源极，缓冲器的第二输出端连接晶体管M9的源极和晶体管M11的源极，晶体管M7的漏极连接晶体管M9的漏极、晶体管M8的源极，晶体管M11的漏极连接晶体管M10的漏极、晶体管M12的源极，晶体管M8的漏极连接电容C5的第一端和乘法器，电容C5的第二端连接接地端，晶体管M8的源极还连接晶体管M8的漏极，晶体管M9的栅极和晶体管M10的栅极连接接地端，晶体管M12的漏极连接电容C6的第一端和乘法器，电容C6的第二端连接接地端，晶体管M12的源极还连接晶体管M12的漏极，晶体管M7的栅极和晶体管M11的栅极连接分频器的第三输出端，晶体管M8的栅极和晶体管M12的栅极连接分频器的第四输出端。In a specific embodiment, please refer to FIG. 4. FIG. 4 is a schematic circuit structure diagram of a second sub-sampling phase detector provided by an embodiment of the present invention. It can be seen from FIG. 4 that the second sub-sampling phase detector PD2 includes a transistor M7, transistor M8, transistor M9, transistor M10, transistor M11, transistor M12, capacitor C5 and capacitor C6, wherein the first output terminal of the buffer is connected to the source of the transistor M7, the source of the transistor M10, and the second output of the buffer The output end is connected to the source of the transistor M9 and the source of the transistor M11, the drain of the transistor M7 is connected to the drain of the transistor M9 and the source of the transistor M8, and the drain of the transistor M11 is connected to the drain of the transistor M10 and the source of the transistor M12 , the drain of the transistor M8 is connected to the first terminal of the capacitor C5 and the multiplier, the second terminal of the capacitor C5 is connected to the ground terminal, the source of the transistor M8 is also connected to the drain of the transistor M8, the gate of the transistor M9 and the gate of the transistor M10 The pole is connected to the ground terminal, the drain of the transistor M12 is connected to the first terminal of the capacitor C6 and the multiplier, the second terminal of the capacitor C6 is connected to the ground terminal, the source of the transistor M12 is also connected to the drain of the transistor M12, and the gate of the transistor M7 is connected to the multiplier. The gate of the transistor M11 is connected to the third output terminal of the frequency divider, and the gates of the transistor M8 and the transistor M12 are connected to the fourth output terminal of the frequency divider.

进一步地，晶体管M7、晶体管M8、晶体管M9、晶体管M10、晶体管M11、晶体管M12均为NMOS。Further, the transistor M7, the transistor M8, the transistor M9, the transistor M10, the transistor M11, and the transistor M12 are all NMOS.

进一步地，晶体管M8和晶体管M12的尺寸为晶体管M7和晶体管M11的一半，晶体管M9和晶体管M10的尺寸与晶体管M7和晶体管M11的尺寸相同。Further, the size of the transistor M8 and the transistor M12 is half of that of the transistor M7 and the transistor M11, and the size of the transistor M9 and the transistor M10 is the same as that of the transistor M7 and the transistor M11.

在本实施例中，CLK_NQ和CLK_PQ是一对差分信号，当CLK_NQ为低时，第二亚采样鉴相器PD2进入采样阶段。当CLK_NQ为高时，第二亚采样鉴相器PD2进入保持阶段。第二亚采样鉴相器PD2中的所有晶体管都是N型的。晶体管M7和晶体管M11是一对开关管，分别连接VIN_PQ和VIN_NQ端口。由于开关管从导通向关断状态切换时，反型层电荷会通过源漏流出，这叫“沟道电荷注入”。为防止电荷直接注入到采样电容上进一步改变采样电容上的电压值，本实施例引入了晶体管M8和晶体管M12作沟道电荷的收集。晶体管M8和晶体管M12的尺寸是晶体管M7和晶体管M11的一半，控制信号与晶体管M7和晶体管M11互补，晶体管M8和晶体管M12的源极与漏极均短接。这样，当晶体管M7和晶体管M11关断时，晶体管M8和晶体管M12导通，晶体管M8和晶体管M12中形成的反型层可以容纳流出的沟道电荷。晶体管M8和晶体管M12还可以抑制时钟馈通。当晶体管M7和晶体管M11截止时，VIN_NQ和VIN_PQ可能通过源漏电容耦合到采样电容上去，引起采样值不稳定，因此引入晶体管M9、晶体管M10，晶体管M9和晶体管M10的栅极保持接地，晶体管M9和晶体管M10的尺寸与晶体管M7和晶体管M11的尺寸完全一样，因此源漏电容也与开关管一样。因此，当第二亚采样鉴相器PD2进入保持阶段，两差分信号通过相同大小的源漏电容耦合到晶体管M8和晶体管M12的源极，使得晶体管M7、晶体管M9的漏极的等效电容接近于0，影响相互抵消。In this embodiment, CLK_NQ and CLK_PQ are a pair of differential signals. When CLK_NQ is low, the second sub-sampling phase detector PD2 enters the sampling phase. When CLK_NQ is high, the second sub-sampling phase detector PD2 enters the hold phase. All transistors in the second sub-sampling phase detector PD2 are of N-type. The transistor M7 and the transistor M11 are a pair of switch tubes, which are respectively connected to the VIN_PQ and VIN_NQ ports. When the switch tube is switched from on to off, the inversion layer charges will flow out through the source and drain, which is called "channel charge injection". In order to prevent charges from being directly injected into the sampling capacitor to further change the voltage value on the sampling capacitor, this embodiment introduces a transistor M8 and a transistor M12 to collect channel charges. The size of the transistor M8 and the transistor M12 is half of that of the transistor M7 and the transistor M11, the control signal is complementary to the transistor M7 and the transistor M11, and the source and the drain of the transistor M8 and the transistor M12 are both short-circuited. In this way, when the transistor M7 and the transistor M11 are turned off, the transistor M8 and the transistor M12 are turned on, and the inversion layer formed in the transistor M8 and the transistor M12 can accommodate the channel charges flowing out. Transistor M8 and transistor M12 also suppress clock feedthrough. When the transistor M7 and the transistor M11 are turned off, VIN_NQ and VIN_PQ may be coupled to the sampling capacitor through the source-drain capacitance, causing the sampling value to be unstable, so the transistor M9 and the transistor M10 are introduced, and the gates of the transistor M9 and the transistor M10 are kept grounded, and the transistor M9 The size of the transistor M10 is exactly the same as that of the transistor M7 and the transistor M11, so the source-drain capacitance is also the same as that of the switch tube. Therefore, when the second sub-sampling phase detector PD2 enters the holding phase, the two differential signals are coupled to the sources of the transistor M8 and the transistor M12 through the source-drain capacitance of the same size, so that the equivalent capacitance of the drains of the transistor M7 and the transistor M9 is close to At 0, the effects cancel each other out.

请参见图5，图5为本发明实施例提供的一种DAC电路原理图，图5为10bit SARDAC，DDS产生IQ差分数字控制信号DDS_NI[0:9]、DDS_NQ[0:9]、DDS_PI[0:9]和DDS_PQ[0:9]，控制DAC中的电容整列的参考电压值接地或者Vref(基准电压)，使得DAC输出两路IQ差分正弦波信号，相对于电流型DAC，SAR DAC具有更好的功耗性能。Please refer to FIG. 5. FIG. 5 is a schematic diagram of a DAC circuit provided by an embodiment of the present invention. FIG. 5 is a 10bit SARDAC, and DDS generates IQ differential digital control signals DDS_NI[0:9], DDS_NQ[0:9], DDS_PI[ 0:9] and DDS_PQ[0:9], control the reference voltage value of the capacitor in the DAC to be grounded or Vref (reference voltage), so that the DAC outputs two IQ differential sine wave signals. Compared with the current type DAC, the SAR DAC has Better power performance.

在一个具体实施例中，请参见图6，图6是本发明实施例提供的一种乘法器的电路结构示意图，通过图6可知，乘法器包括晶体管M13、晶体管M14、晶体管M15、晶体管M16、晶体管M17、晶体管M18、晶体管M19、晶体管M20、晶体管M21、晶体管M22、晶体管M23、晶体管M24、电容C7、电容C8、电阻R2和电阻R3，其中，晶体管M13的栅极、晶体管M17的栅极连接DAC的第一输出端，晶体管M14的栅极、晶体管M16的栅极连接DAC的第二输出端，晶体管M15的栅极和晶体管M18的栅极连接第一亚采样鉴相器PD1的电容C3的第一端和电容C4的第一端，晶体管M13的源极连接晶体管M14的源极、晶体管M15的漏极，晶体管M13的漏极连接电容C7的第一端、电阻R2的第一端，晶体管M14的漏极连接电容C8的第一端、电阻R3的第一端，晶体管M15的源极连接接地端，晶体管M16的源极连接晶体管M17的源极、晶体管M18的漏极，晶体管M16的漏极连接电容C7的第一端、电阻R2的第一端，晶体管M17的漏极连接电容C8的第一端、电阻R3的第一端，晶体管M18的源极接地；晶体管M19的栅极、晶体管M23的栅极连接DAC的第三输出端，晶体管M20的栅极、晶体管M22的栅极连接DAC的第四输出端，晶体管M21的栅极和晶体管M24的栅极连接第二亚采样鉴相器PD2的电容C5的第一端和电容C6的第一端，晶体管M19的源极连接晶体管M20的源极、晶体管M21的漏极，晶体管M19的漏极连接电容C7的第一端、电阻R2的第一端，晶体管M20的漏极连接电容C8的第一端、电阻R3的第一端，晶体管M21的源极连接接地端，晶体管M22的源极连接晶体管M23的源极、晶体管M24的漏极，晶体管M22的漏极连接电容C7的第一端、电阻R2的第一端，晶体管M23的漏极连接电容C8的第一端、电阻R3的第一端，晶体管M24的源极接地；电容C7的第二端和电容C8的第二端连接接地端，电阻R2的第二端和电阻R3的第二端连接电源端，电容C7的第一端和电阻R2的第一端还连接电压电流转换电路的第一输入端，电容C8的第一端和电阻R3的第一端还连接电压电流转换电路的第二输入端。In a specific embodiment, please refer to FIG. 6. FIG. 6 is a schematic circuit structure diagram of a multiplier provided by an embodiment of the present invention. It can be seen from FIG. 6 that the multiplier includes a transistor M13, a transistor M14, a transistor M15, a transistor M16, Transistor M17, transistor M18, transistor M19, transistor M20, transistor M21, transistor M22, transistor M23, transistor M24, capacitor C7, capacitor C8, resistor R2 and resistor R3, wherein the gate of transistor M13 and the gate of transistor M17 are connected The first output end of the DAC, the gate of the transistor M14, the gate of the transistor M16 are connected to the second output end of the DAC, the gate of the transistor M15 and the gate of the transistor M18 are connected to the capacitor C3 of the first sub-sampling phase detector PD1 The first end and the first end of the capacitor C4, the source of the transistor M13 is connected to the source of the transistor M14, the drain of the transistor M15, the drain of the transistor M13 is connected to the first end of the capacitor C7, the first end of the resistor R2, the transistor The drain of M14 is connected to the first terminal of the capacitor C8 and the first terminal of the resistor R3, the source of the transistor M15 is connected to the ground terminal, the source of the transistor M16 is connected to the source of the transistor M17, the drain of the transistor M18, and the drain of the transistor M16 The pole is connected to the first end of the capacitor C7 and the first end of the resistor R2, the drain of the transistor M17 is connected to the first end of the capacitor C8 and the first end of the resistor R3, the source of the transistor M18 is grounded; the gate of the transistor M19, the transistor The gate of M23 is connected to the third output terminal of the DAC, the gate of the transistor M20 and the gate of the transistor M22 are connected to the fourth output terminal of the DAC, and the gates of the transistor M21 and the gate of the transistor M24 are connected to the second sub-sampling phase detector The first end of the capacitor C5 and the first end of the capacitor C6 of PD2, the source of the transistor M19 is connected to the source of the transistor M20, the drain of the transistor M21, the drain of the transistor M19 is connected to the first end of the capacitor C7, the resistor R2 The first terminal, the drain of the transistor M20 is connected to the first terminal of the capacitor C8 and the first terminal of the resistor R3, the source of the transistor M21 is connected to the ground terminal, the source of the transistor M22 is connected to the source of the transistor M23, and the drain of the transistor M24 , the drain of the transistor M22 is connected to the first terminal of the capacitor C7 and the first terminal of the resistor R2, the drain of the transistor M23 is connected to the first terminal of the capacitor C8 and the first terminal of the resistor R3, and the source of the transistor M24 is grounded; the capacitor C7 The second terminal of the capacitor C8 and the second terminal of the capacitor C8 are connected to the ground terminal, the second terminal of the resistor R2 and the second terminal of the resistor R3 are connected to the power supply terminal, and the first terminal of the capacitor C7 and the first terminal of the resistor R2 are also connected to the voltage-current conversion The first input terminal of the circuit, the first terminal of the capacitor C8 and the first terminal of the resistor R3 are also connected to the second input terminal of the voltage-current conversion circuit.

进一步地，晶体管M13、晶体管M14、晶体管M15、晶体管M16、晶体管M17、晶体管M18、晶体管M19、晶体管M20、晶体管M21、晶体管M22、晶体管M23、晶体管M24均为NMOS。Further, the transistor M13, the transistor M14, the transistor M15, the transistor M16, the transistor M17, the transistor M18, the transistor M19, the transistor M20, the transistor M21, the transistor M22, the transistor M23, and the transistor M24 are all NMOS.

在本实施例中，DDS生成的IQ差分对信号与采样电路输出的差频IQ信号进行相乘，输出DDS的IQ差分信号与采样电路输出的差频IQ信号的频率差信号。由于采用了IQ结构，使得乘法器的输出信号的频率分量仅包含DDS生成的IQ差分信号与采样电路输出的差频IQ信号的频率差信号，抑制了其他谐波分量。为了得到更好的谐波抑制能力，分频器的输出和参考频率的频率差应该适当增大。为了得到更加纯净的差频信号，乘法器的输出电阻R2、R3与C7、C8组成低通滤波器，进一步滤除高频杂波噪声。In this embodiment, the IQ difference pair signal generated by the DDS is multiplied by the difference frequency IQ signal output by the sampling circuit, and the frequency difference signal of the IQ difference signal of the DDS and the difference frequency IQ signal output by the sampling circuit is output. Due to the IQ structure, the frequency component of the output signal of the multiplier only includes the frequency difference signal between the IQ difference signal generated by the DDS and the difference frequency IQ signal output by the sampling circuit, and other harmonic components are suppressed. In order to obtain better harmonic suppression capability, the frequency difference between the output of the frequency divider and the reference frequency should be appropriately increased. In order to obtain a more pure difference frequency signal, the output resistors R2, R3 of the multiplier and C7, C8 form a low-pass filter to further filter out high-frequency clutter noise.

在一个具体实施例中，请参见图7，图7是本发明实施例提供的一种电压电流转换电路的电路结构示意图，通过图7可知，电压电流转换电路包括晶体管M25、晶体管M26、晶体管M27、晶体管M28、晶体管M29、晶体管M30、晶体管M31、晶体管M32和晶体管M33，其中，乘法器的第一输出端连接晶体管M25的栅极，即电容C7的第一端和电阻R2的第一端连接晶体管M25的栅极，乘法器的第二输出端连接晶体管M26的栅极，即电容C8的第一端和电阻R3的第一端连接晶体管M26的栅极，晶体管M25的源极连接晶体管M26的源极和晶体管M27的漏极，晶体管M25的漏极连接晶体管M28的漏极、晶体管M28的栅极、晶体管M31的栅极，晶体管M26的漏极连接晶体管M29的漏极、晶体管M29的栅极、晶体管M30的栅极，晶体管M27的栅极连接偏置电压端V_BIAS，晶体管M27的源极连接接地端，晶体管M30的漏极连接晶体管M32的漏极、晶体管M32的栅极、晶体管M33的栅极，晶体管M31的漏极连接晶体管M33的漏极和低通滤波器，晶体管M32的源极和晶体管M33的源极连接接地端，晶体管M28、晶体管M29、晶体管M30、晶体管M31连接电源端。In a specific embodiment, please refer to FIG. 7. FIG. 7 is a schematic circuit structure diagram of a voltage-current conversion circuit provided by an embodiment of the present invention. It can be seen from FIG. 7 that the voltage-current conversion circuit includes a transistor M25, a transistor M26, and a transistor M27 , transistor M28, transistor M29, transistor M30, transistor M31, transistor M32 and transistor M33, wherein the first output end of the multiplier is connected to the gate of the transistor M25, that is, the first end of the capacitor C7 is connected to the first end of the resistor R2 The gate of the transistor M25, the second output terminal of the multiplier is connected to the gate of the transistor M26, that is, the first terminal of the capacitor C8 and the first terminal of the resistor R3 are connected to the gate of the transistor M26, and the source of the transistor M25 is connected to the gate of the transistor M26 Source and the drain of transistor M27, the drain of transistor M25 is connected to the drain of transistor M28, the gate of transistor M28, the gate of transistor M31, the drain of transistor M26 is connected to the drain of transistor M29, the gate of transistor M29 , the gate of the transistor M30, the gate of the transistor M27 is connected to the bias voltage terminal V _BIAS , the source of the transistor M27 is connected to the ground terminal, the drain of the transistor M30 is connected to the drain of the transistor M32, the gate of the transistor M32, the gate of the transistor M33 The gate and the drain of the transistor M31 are connected to the drain of the transistor M33 and the low-pass filter, the source of the transistor M32 and the source of the transistor M33 are connected to the ground, and the transistors M28, M29, M30 and M31 are connected to the power supply.

进一步地，晶体管M25、晶体管M26、晶体管M27、晶体管M32和晶体管M33为NMOS，晶体管M28、晶体管M29、晶体管M30、晶体管M31为PMOS。Further, the transistor M25 , the transistor M26 , the transistor M27 , the transistor M32 and the transistor M33 are NMOS, and the transistor M28 , the transistor M29 , the transistor M30 and the transistor M31 are PMOS.

在一个具体实施例中，请参见图8，图8是本发明实施例提供的一种低通滤波器的电路结构示意图，低通滤波器包括电阻R1、电容C1和电容C2，其中，电阻R1的第一端、电容C2的第一端连接电压电流转换电路的输出端和压控振荡器的输入端，即电阻R1的第一端、电容C2的第一端连接晶体管M31、晶体管M33的漏极，电阻R1的第一端、电容C2的第一端还连接压控振荡器的输入端，电阻R1的第二端连接电容C1的第一端，电容C1的第二端和电容C2的第二端连接接地端。In a specific embodiment, please refer to FIG. 8. FIG. 8 is a schematic diagram of a circuit structure of a low-pass filter provided by an embodiment of the present invention. The low-pass filter includes a resistor R1, a capacitor C1, and a capacitor C2, wherein the resistor R1 The first end of the first end of the capacitor C2 is connected to the output end of the voltage-current conversion circuit and the input end of the voltage-controlled oscillator, that is, the first end of the resistor R1 and the first end of the capacitor C2 are connected to the drain of the transistor M31 and the transistor M33 The first end of the resistor R1 and the first end of the capacitor C2 are also connected to the input end of the voltage-controlled oscillator, the second end of the resistor R1 is connected to the first end of the capacitor C1, the second end of the capacitor C1 and the first end of the capacitor C2 The two terminals are connected to the ground terminal.

在本实施例中，由折叠运算放大器作为电压电流转换电路，为了达到更高的增益、降低相位噪声，鉴相器(即第一亚采样鉴相器PD1、第二亚采样鉴相器PD2)引入了预放大部分，先将输入信号进行放大在通过电压电流转换电路转换为电流信号。为了达到更好的输出摆幅，仅用一个PMOS和一个NMOS(即晶体管M31、晶体管M33)组成电压电流转换电路的输出。亚采样锁相环的电压电流转换电路上拉和下拉电流是由采样电压的幅度决定的，因此也一定相等，不存在鉴频鉴相锁相环里存在的电流不匹配问题。In this embodiment, the folded operational amplifier is used as the voltage-to-current conversion circuit. In order to achieve higher gain and reduce phase noise, the phase detector (ie, the first sub-sampling phase detector PD1 and the second sub-sampling phase detector PD2) The pre-amplification part is introduced, and the input signal is first amplified and then converted into a current signal through a voltage-current conversion circuit. In order to achieve a better output swing, only one PMOS and one NMOS (ie transistor M31 and transistor M33 ) are used to form the output of the voltage-current conversion circuit. The pull-up and pull-down currents of the voltage-current conversion circuit of the sub-sampling phase-locked loop are determined by the amplitude of the sampling voltage, so they must be equal, and there is no current mismatch problem in the frequency-detection phase-locked loop.

采样得到的信号包含着输出信号的相位信息，经过电压电流转换电路处理后对电容进行充电。电压电流转换电路的负载相当于一个低通滤波器。为了滤除杂散，引入了一个低通滤波器，由于低通滤波器的引入，使系统引入了一个极点，容易导致锁相环的相位裕度不足从而导致系统不稳定。所以为了增加锁相环的相位裕度，引入了电阻R1，从而引入一个零点。为了避免输出电压产生跳跃，再引入了一个电容C2来滤除电压跳变时产生的干扰。The sampled signal contains the phase information of the output signal, and the capacitor is charged after being processed by the voltage-current conversion circuit. The load of the voltage-to-current conversion circuit is equivalent to a low-pass filter. In order to filter the stray, a low-pass filter is introduced. Due to the introduction of the low-pass filter, the system introduces a pole, which easily leads to insufficient phase margin of the phase-locked loop and thus leads to system instability. Therefore, in order to increase the phase margin of the phase-locked loop, a resistor R1 is introduced, thereby introducing a zero point. In order to prevent the output voltage from jumping, a capacitor C2 is introduced to filter out the interference generated when the voltage jumps.

在一个具体实施例中，请参见图9，图9是本发明实施例提供的一种压控振荡器的电路结构示意图，压控振荡器包括晶体管M33、晶体管M34、晶体管M35、晶体管M36、电感L、可调电容C_A1、可调电容C_A2、电容阵列，其中，电压电流转换电路的输出端连接可调电容C_A1的第一端、可调电容C_A2的第一端，即可调电容C_A1的第一端、可调电容C_A2的第一端连接晶体管M31的漏极、晶体管M33的漏极、电阻R1的第一端、电容C2的第一端，可调电容C_A1的第二端连接晶体管M33的漏极、电感L的第一端、晶体管M34的栅极、电容阵列的第一端、晶体管M35的漏极、晶体管M36的栅极、第一反相器链F1，可调电容C_A2的第二端连接晶体管M34的漏极、电感L的第二端、晶体管M33的栅极、电容阵列的第二端、晶体管M36的漏极、晶体管M35的栅极、第二反相器链F2，晶体管M33的源极和晶体管M34的源极通过恒流源连接电源端，晶体管M35的源极和晶体管M36的源极连接接地端。In a specific embodiment, please refer to FIG. 9. FIG. 9 is a schematic diagram of a circuit structure of a voltage-controlled oscillator provided by an embodiment of the present invention. The voltage-controlled oscillator includes a transistor M33, a transistor M34, a transistor M35, a transistor M36, an inductor L, adjustable capacitor C _A1 , adjustable capacitor C _A2 , and capacitor array, wherein the output end of the voltage-current conversion circuit is connected to the first end of the adjustable capacitor C _A1 and the first end of the adjustable capacitor C _A2 , that is, adjustable The first end of the capacitor C _A1 and the first end of the adjustable capacitor C _A2 are connected to the drain of the transistor M31, the drain of the transistor M33, the first end of the resistor R1, the first end of the capacitor C2, and the adjustable capacitor C _A1 The second end is connected to the drain of the transistor M33, the first end of the inductor L, the gate of the transistor M34, the first end of the capacitor array, the drain of the transistor M35, the gate of the transistor M36, and the first inverter chain F1, The second end of the adjustable capacitor C _A2 is connected to the drain of the transistor M34, the second end of the inductor L, the gate of the transistor M33, the second end of the capacitor array, the drain of the transistor M36, the gate of the transistor M35, the second The inverter chain F2, the source of the transistor M33 and the source of the transistor M34 are connected to the power terminal through the constant current source, and the source of the transistor M35 and the source of the transistor M36 are connected to the ground terminal.

进一步地，晶体管M33、晶体管M34为PMOS，晶体管M35、晶体管M36为NMOS。Further, the transistor M33 and the transistor M34 are PMOS, and the transistor M35 and the transistor M36 are NMOS.

在本实施例中，压控振荡器采用的是NMOS和PMOS互补的LC振荡器，这种结构能提供更低的相位噪声。LC振荡器通过改变电容的容值可以得到很高的振荡频率范围。根据振荡频率的公式：

LC振荡器通过调整电压V_tune可以改变可调电容C_A1和可调电容C_A2的容值，从而改变LC振荡器的输出频率。为了得到足够宽的输出频率范围，LC振荡器使用了四个不同大小的电容模块组成的电容阵列，四个不同大小的电容模块即C_DIG[0:3]，其中四个电容模块电容值大小的比值为1：2：4：8，每个电容模块由两个电容和处于这两个电容之间的开关组成，四个电容模块的四个开关分别为T₀、T₁、T₂、T₃，因此通过控制开关T₀-T₃接入与否进行控制LC振荡器的振荡频率，T₀、T₁、T₂、T₃为高时，电容接入环路，LC振荡器的电容值增大，振荡频率下降；T₀、T₁、T₂、T₃为低时，电容与环路断开，电路的电容值变大，频率升高。四个不同的电容模块的组合可以产生叠加，从而产生了2⁴个频段。In this embodiment, the voltage-controlled oscillator is an LC oscillator that is complementary to NMOS and PMOS, and this structure can provide lower phase noise. The LC oscillator can obtain a very high oscillation frequency range by changing the capacitance of the capacitor. According to the formula of oscillation frequency:

The LC oscillator can change the capacitance of the adjustable capacitor C _A1 and the adjustable capacitor C _A2 by adjusting the voltage V _tune , thereby changing the output frequency of the LC oscillator. In order to obtain a wide enough output frequency range, the LC oscillator uses a capacitor array composed of four capacitor modules of different sizes. The four capacitor modules of different sizes are C _DIG [0:3], and the capacitance values of the four capacitor modules are The ratio is 1:2:4:8. Each capacitor module is composed of two capacitors and a switch between the two capacitors. The four switches of the four capacitor modules are T ₀ , T ₁ , T ₂ , T ₃ , so the oscillation frequency of the LC oscillator is controlled by controlling whether the switches T ₀ -T ₃ are connected or not. When T ₀ , T ₁ , T ₂ , and T ₃ are high, the capacitor is connected to the loop, and the LC oscillator When the capacitance value increases, the oscillation frequency decreases; when T ₀ , T ₁ , T ₂ , and T ₃ are low, the capacitance is disconnected from the loop, the capacitance value of the circuit becomes larger, and the frequency increases. The combination of four different capacitive modules can be superimposed, resulting in 2 ⁴ frequency bands.

本发明为了能在高达十几GHz的频率下稳定正常工作，为了达到小数分频的效果，本发明利用反馈回的信号对参考信号进行采样输出差频信号，再将采样的信号与DDS生成的低频信号进行混频，最终达到小数分频的效果，这种小数分频结构相比于传统的delta-sigma结构或者TDC结构有分频精度高、线性度好和功耗低等优点。In order for the present invention to work stably and normally at a frequency up to more than ten GHz, in order to achieve the effect of fractional frequency division, the present invention uses the feedback signal to sample the reference signal to output the difference frequency signal, and then compares the sampled signal with the DDS generated The low-frequency signal is mixed to achieve the effect of fractional frequency division. Compared with the traditional delta-sigma structure or TDC structure, this fractional frequency division structure has the advantages of high frequency division accuracy, good linearity and low power consumption.

本发明的锁相环结构相比于过去在VCO输出上进行混频的方案，本发明的DDS/DAC输出的频率低，所需的参考频率低，并且使用的SAR型DAC能节省大部分DAC的功耗。The phase-locked loop structure of the present invention is compared with the scheme that carries out frequency mixing on the VCO output in the past, the frequency of the DDS/DAC output of the present invention is low, the reference frequency required is low, and the SAR type DAC used can save most of the DAC power consumption.

本发明的采样电路与DAC电路采用IQ输出，大大的减少了混频器的杂散，使得锁相环整体有更低的杂散性能。The sampling circuit and the DAC circuit of the present invention adopt IQ output, which greatly reduces the stray of the mixer, so that the whole phase-locked loop has lower stray performance.

在本发明的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。此外，本领域的技术人员可以将本说明书中描述的不同实施例或示例进行接合和组合。In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example Or features are included in at least one embodiment or example of the invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.