CN112289365B - Semiconductor memory device - Google Patents

The invention provides a semiconductor memory device, which comprises a data memory array for storing application data, a check bit memory array for storing check bit data, a data read-write and correction part, a check bit read-write part and a concomitant generation and decoding part. The data read-write and correction part reads the data memory array and outputs first application read data. The check bit read/write section reads the check bit memory array and outputs check bit read data. In the reading period of the application data, the syndrome generating and decoding part generates syndrome writing data according to the first application reading data, and compares and decodes the syndrome writing data with the check bit reading data to generate check comparison data. In the same reading period, the data reading-writing and correcting part corrects the application data according to the verification comparison data, and writes the corrected application data back to the data memory array and outputs corresponding output data.

半导体存储器装置semiconductor memory device

技术领域Technical field

本发明涉及一种存储器装置，尤其涉及一种可进行错误检查和校正的半导体存储器装置。The present invention relates to a memory device, and in particular to a semiconductor memory device capable of error checking and correction.

背景技术Background technique

动态随机存取存储器(Dynamic Random Access Memory，DRAM)具有结构简单、单位体积容量较高而成本较低的优点，可应用于各种电子装置。在数据传输和/或数据存储的过程中，数据的可靠度是一个重要的课题。一般来说，目前的动态随机存取存储器常使用错误检查和校正(Error Checking and Correcting，ECC)技术来提高数据的可靠度。欲写入至动态随机存取存储器的数据会先进行ECC编码程序，以产生对应的错误检查和校正码，并且一并将数据以及错误检查和校正码进行存储。在读取数据时，即可将读取出来的数据与错误检查和校正码进行比较与解码，以校正数据中的错误比特，并输出经校正后的比特。Dynamic Random Access Memory (DRAM) has the advantages of simple structure, high capacity per unit volume and low cost, and can be applied to various electronic devices. Data reliability is an important issue during data transmission and/or data storage. Generally speaking, current dynamic random access memories often use Error Checking and Correcting (ECC) technology to improve data reliability. Data to be written to the dynamic random access memory will first undergo an ECC encoding process to generate corresponding error checking and correction codes, and the data and error checking and correction codes will be stored together. When reading data, the read data can be compared and decoded with the error checking and correction code to correct the erroneous bits in the data and output the corrected bits.

为了满足芯片小型化的需求，一般的DRAM会采用单错误校正(Single ErrorCorrecting)技术。此技术仅可对一个数据单位中的一个错误比特进行校正，而无法处理两个以上的错误比特的情况。然而，在将数据存储至DRAM时，可能会因高温、刷新操作等导致的软错误(Soft error)而间歇性地随机产生错误比特。若在一个数据单位中存在一个错误比特且未即时地将经校正的数据写回存储器，一旦累积了两个以上的错误比特时，错误检查和校正功能就会失效，从而降低数据的可靠度。In order to meet the demand for chip miniaturization, general DRAM will use Single Error Correction (Single ErrorCorrecting) technology. This technology can only correct one erroneous bit in one data unit, but cannot handle the situation of more than two erroneous bits. However, when data is stored in DRAM, erroneous bits may be randomly generated intermittently due to soft errors caused by high temperature, refresh operations, etc. If there is an erroneous bit in a data unit and the corrected data is not written back to the memory immediately, once more than two erroneous bits accumulate, the error checking and correction functions will fail, thus reducing the reliability of the data.

发明内容Contents of the invention

本发明提供一种半导体存储器装置，可在数据的读取周期中，对间歇性产生的错误比特进行即时校正。The present invention provides a semiconductor memory device that can perform real-time correction of intermittently generated erroneous bits during a data reading cycle.

本发明的半导体存储器装置包括数据存储器阵列、校验位存储器阵列、数据读写与校正部、校验位读写部以及伴随式产生与解码部。数据存储器阵列用以存储应用数据。校验位存储器阵列用以存储对应于应用数据的校验位数据。数据读写与校正部耦接数据存储器阵列，用以对数据存储器阵列进行应用数据的读取，并输出对应的第一应用读取数据。校验位读写部耦接校验位存储器阵列，用以对校验位存储器阵列进行校验位数据的读取，并输出对应的校验位读取数据。伴随式产生与解码部耦接数据读写与校正部以及校验位读写部，在应用数据的读取周期内，伴随式产生与解码部依据第一应用读取数据产生伴随式写入数据，并且将伴随式写入数据与校验位读取数据进行比较与解码以产生校验比较数据。在同一个读取周期内，数据读写与校正部根据校验比较数据对应用数据进行校正，并将校正后的应用数据写回数据存储器阵列以及输出对应的输出数据。The semiconductor memory device of the present invention includes a data memory array, a parity bit memory array, a data reading and writing and correction unit, a parity bit reading and writing unit, and a syndrome generation and decoding unit. The data memory array is used to store application data. The parity bit memory array is used to store parity bit data corresponding to the application data. The data reading, writing and correcting unit is coupled to the data memory array and used to read application data from the data memory array and output corresponding first application read data. The check bit reading and writing unit is coupled to the check bit memory array, and is used to read check bit data from the check bit memory array, and output corresponding check bit read data. The syndrome generation and decoding unit is coupled to the data reading, writing and correction unit and the check bit reading and writing unit. During the reading cycle of application data, the syndrome generation and decoding unit generates syndrome writing data according to the first application read data. , and compare and decode the syndrome write data and the check bit read data to generate check comparison data. In the same read cycle, the data reading, writing and correction unit corrects the application data according to the verification comparison data, writes the corrected application data back to the data memory array and outputs corresponding output data.

在本发明的一实施例中，上述的数据读写与校正部包括多个读取放大器、多个数据校正器以及多个写入放大器。多个读取放大器从数据存储器阵列读取并放大应用数据，以产生对应的第一应用读取数据与第二应用读取数据。各个数据校正器耦接对应的读取放大器。多个数据校正器锁存第二应用读取数据，根据校验比较数据校正第二应用读取数据中的错误比特以产生输出数据，并且输出对应的校正数据。各个写入放大器耦接对应的读取放大器以及数据校正器。多个写入放大器根据校正数据以及校验比较数据将校正后的应用数据写入至数据存储器阵列。In an embodiment of the present invention, the above-mentioned data reading, writing and correcting unit includes a plurality of read amplifiers, a plurality of data correctors and a plurality of write amplifiers. A plurality of read amplifiers read and amplify application data from the data memory array to generate corresponding first application read data and second application read data. Each data corrector is coupled to a corresponding read amplifier. A plurality of data correctors latches the second application read data, corrects erroneous bits in the second application read data according to the check comparison data to generate output data, and outputs corresponding correction data. Each write amplifier is coupled to a corresponding read amplifier and data corrector. A plurality of write amplifiers write the corrected application data to the data memory array according to the correction data and the verification comparison data.

基于上述，当在数据的读取周期中发生了一比特的错误比特时，本发明的半导体存储器装置能够在同一个读取周期中检查出错误比特的所在位置并即时地进行校正，并且将校正后的正确数据写回存储器阵列中。藉此，可避免累积两个比特以上的错误比特的情况，从而提高数据的可靠度。Based on the above, when an erroneous bit of one bit occurs during the data reading cycle, the semiconductor memory device of the present invention can detect the location of the erroneous bit in the same reading cycle and perform corrections immediately, and correct the error. The correct data is then written back to the memory array. In this way, the accumulation of more than two erroneous bits can be avoided, thereby improving the reliability of the data.

为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, embodiments are given below and described in detail with reference to the accompanying drawings.

附图说明Description of drawings

图1是依照本发明一实施例的一种半导体存储器装置的电路示意图。FIG. 1 is a schematic circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

图2A是依照本发明一实施例的数据读写与校正部的电路示意图。FIG. 2A is a circuit schematic diagram of a data reading, writing and correction unit according to an embodiment of the present invention.

图2B是依照本发明一实施例的半导体存储器装置的读取操作的波形示意图。FIG. 2B is a schematic waveform diagram of a read operation of a semiconductor memory device according to an embodiment of the present invention.

图3是依照本发明一实施例的读取放大器的电路示意图。FIG. 3 is a schematic circuit diagram of a sense amplifier according to an embodiment of the present invention.

图4是依照本发明一实施例的数据校正器的电路示意图。FIG. 4 is a schematic circuit diagram of a data corrector according to an embodiment of the present invention.

图5是依照本发明一实施例的写入放大器的电路示意图。FIG. 5 is a circuit schematic diagram of a write amplifier according to an embodiment of the present invention.

图6是依照本发明一实施例的校验位读写部的电路示意图。FIG. 6 is a schematic circuit diagram of a check digit reading and writing unit according to an embodiment of the present invention.

图7是依照本发明一实施例的伴随式产生与解码部的电路示意图。FIG. 7 is a schematic circuit diagram of an associated expression generation and decoding unit according to an embodiment of the present invention.

附图标号说明：Explanation of reference numbers:

100：半导体存储器装置100: Semiconductor memory device

110：数据存储器阵列110: Data memory array

120：校验位存储器阵列120: Parity bit memory array

130：数据读写与校正部130: Data reading, writing and correction department

140：校验位读写部140: Check digit reading and writing department

150：伴随式产生与解码部150: Compound Generation and Decoding Department

210、610：读取放大器210, 610: Read amplifier

220：数据校正器220: Data Corrector

230、620：写入放大器230, 620: Write amplifier

310：第一开关310: First switch

320：预充电电路320: Precharge circuit

330：放大电路330: Amplification circuit

410：第二开关410: Second switch

420：第一锁存电路420: First latch circuit

430：校正电路430: Correction circuit

440：第一输出电路440: First output circuit

510：第三开关510: Third switch

520：第四开关520: The fourth switch

530：第二锁存电路530: Second latch circuit

540：第二输出电路540: Second output circuit

710：伴随式产生器710: Adjoint generator

720：互斥或闸720: Mutual exclusion or gate

730：伴随式解码器730: adjoint decoder

CSL1、CSL2：选择信号CSL1, CSL2: selection signal

DE：读取放大器致能信号DE: Read amplifier enable signal

DOUT0～DOUT63、DOUTi：输出数据DOUT0～DOUT63, DOUTi: output data

EiT：正锁存比特信号EiT: positive latched bit signal

EiN：反锁存比特信号EiN: Anti-latch bit signal

GND：接地电压INV1～INV14：第一～第十四反相器GND: Ground voltage INV1~INV14: 1st~14th inverters

INVA：反相器INVA: inverter

LAR：读取数据锁存信号LAR: read data latch signal

LAW：写入数据锁存信号LAW: write data latch signal

MD0～MD63、MDi：应用数据MD0～MD63, MDi: application data

MD0’～MD63’、MDi’：第二应用读取数据MD0’～MD63’, MDi’: the second application reads data

MDiT：正应用数据MDiT: applying data

MDiT’：正第二应用读取数据MDiT’: Reading data from the second application

MDiN：反应用数据MDiN: reaction data

MDiN’：反第二应用读取数据MDiN’: Anti-second application to read data

NAND1～NAND3：第一～第三反及闸NAND1～NAND3: first～third anti-AND gate

NOR1～NOR4：第一～第四反或闸NOR1～NOR4: first to fourth inverse OR gate

NSDj、NSD0～NSD6：伴随式写入数据NSDj, NSD0~NSD6: accompanying write data

OE：输出致能信号OE: output enable signal

PB：预充电信号PB: Precharge signal

PMDj、PMD0～PMD6：校验位数据PMDj, PMD0~PMD6: check digit data

PRDj、PRD0～PRD6：校验位读取数据PRDj, PRD0～PRD6: Check bit reading data

QN1～QN12：第一～第十二N型场效晶体管QN1～QN12: first to twelfth N-type field effect transistors

QP1～QP17：第一～第十七P型场效晶体管QP1～QP17: The first to the seventeenth P-type field effect transistors

RDi、RD0～RD63：第一应用读取数据RDi, RD0~RD63: The first application reads data

SCDi：校正数据SCDi: correction data

SDi、SD0～SD63：校验比较数据SDi, SD0~SD63: Verification comparison data

SDE：校验比较致能信号SDE: Verification comparison enable signal

SY0～SY6、SYj：比特错误信号SY0～SY6, SYj: bit error signal

T1～T5：时间点T1～T5: time point

VDD：动作电压VDD: operating voltage

WE：写入放大器致能信号WE: write amplifier enable signal

具体实施方式Detailed ways

以下请参照图1，图1是依照本发明一实施例的一种半导体存储器装置的电路示意图。半导体存储器装置100包括数据存储器阵列110、校验位存储器阵列120、数据读写与校正部130、校验位读写部140以及伴随式产生与解码部150。数据存储器阵列110用以存储应用数据MDi。应用数据MDi具有i+1个比特。校验位存储器阵列120用以存储对应于应用数据MDi的校验位数据PMDj。校验位数据PMDj例如是将应用数据MDi进行汉明码(Hamming code)等ECC编码程序而产生的错误检查和校正码。校验位数据PMDj具有j+1个比特，此数量取决于所要进行错误检查和校正的应用数据MDi的比特数(即i+1)。举例来说，根据本发明实施例所采用的单错误校正技术，可依据7比特的校验位数据PMD0～PMD6对64比特的应用数据MD0～MD63进行单错误校正。于其他的实施例中，也可依据8比特的校验位数据对128比特的应用数据进行单错误校正，本领域技术人员可以视其实际需求以此类推。Please refer to FIG. 1 below. FIG. 1 is a schematic circuit diagram of a semiconductor memory device according to an embodiment of the present invention. The semiconductor memory device 100 includes a data memory array 110, a parity bit memory array 120, a data reading and writing and correction unit 130, a parity bit reading and writing unit 140, and a syndrome generation and decoding unit 150. The data memory array 110 is used to store application data MDi. The application data MDi has i+1 bits. The parity bit memory array 120 is used to store parity bit data PMDj corresponding to the application data MDi. The parity bit data PMDj is, for example, an error checking and correction code generated by subjecting the application data MDi to an ECC encoding process such as Hamming code. The parity bit data PMDj has j+1 bits, and this number depends on the number of bits of the application data MDi to be error checked and corrected (i.e., i+1). For example, according to the single error correction technology adopted in the embodiment of the present invention, single error correction can be performed on the 64-bit application data MD0-MD63 based on the 7-bit parity bit data PMD0-PMD6. In other embodiments, single error correction can also be performed on the 128-bit application data based on the 8-bit parity bit data. Those skilled in the art can make the same deduction based on their actual needs.

数据读写与校正部130耦接数据存储器阵列110，用以感测并放大数据存储器阵列110的应用数据MDi，并输出对应的第一应用读取数据RDi至伴随式产生与解码部150。校验位读写部140耦接校验位存储器阵列120，用以感测并放大校验位存储器阵列120的校验位数据PMDj，并输出对应的校验位读取数据PRDj至伴随式产生与解码部150。在本实施例中，i与j可以为整数，其中0≤i≤63，且0≤j≤6，但本发明并不依此为限。The data reading, writing and correcting unit 130 is coupled to the data memory array 110 for sensing and amplifying the application data MDi of the data memory array 110 and outputting the corresponding first application read data RDi to the syndrome generation and decoding unit 150 . The parity bit reading and writing unit 140 is coupled to the parity bit memory array 120 for sensing and amplifying the parity bit data PMDj of the parity bit memory array 120 and outputting the corresponding parity bit read data PRDj to the accompanying generator. and decoding unit 150. In this embodiment, i and j can be integers, where 0≤i≤63, and 0≤j≤6, but the invention is not limited thereto.

伴随式产生与解码部150耦接数据读写与校正部130以及校验位读写部140。在本发明实施例中，在一个应用数据MDi的读取周期内，伴随式产生与解码部150可将第一应用读取数据RDi进行伴随式编码(Syndrome encoding)而产生伴随式写入数据NSDj。接着，将伴随式写入数据NSDj与校验位读取数据PRDj进行比较与伴随式解码(Syndrome decoding)以产生校验比较数据SDi。校验比较数据SDi用以指示应用数据MDi是否需要校正。The syndrome generation and decoding unit 150 is coupled to the data reading, writing and correcting unit 130 and the check digit reading and writing unit 140 . In an embodiment of the present invention, within a reading cycle of application data MDi, the syndrome generation and decoding unit 150 may perform syndrome encoding on the first application read data RDi to generate syndrome write data NSDj . Next, the syndrome write data NSDj and the check bit read data PRDj are compared and syndrome decoded to generate the check comparison data SDi. The verification comparison data SDi is used to indicate whether the application data MDi needs to be corrected.

并且，在同一个读取周期内，数据读写与校正部130可接收到校验比较数据SDi，并根据校验比较数据SDi对应用数据MDi进行校正，并将校正后的应用数据MDi写回数据存储器阵列110以及作为对应的输出数据DOUTi进行输出。藉此，当应用数据MDi产生一个错误比特时，半导体存储器装置100可在同一个读取周期内完成输出数据DOUTi的输出并将校正后的应用数据MDi写回数据存储器阵列110，以避免错误比特遗留到下一个读取周期，从而提高数据的可靠度。Moreover, in the same reading cycle, the data reading, writing and correcting unit 130 can receive the verification comparison data SDi, correct the application data MDi according to the verification comparison data SDi, and write back the corrected application data MDi. The data memory array 110 and the corresponding output data DOUTi are output. Thereby, when the application data MDi generates an erroneous bit, the semiconductor memory device 100 can complete the output of the output data DOUTi in the same read cycle and write the corrected application data MDi back to the data memory array 110 to avoid erroneous bits. carried over to the next read cycle, thereby improving data reliability.

顺带一提的是，伴随式产生与解码部150也可将伴随式写入数据NSDj传送至校验位读写部140，以作为对应的校验位数据PMDj写入至校验位存储器阵列120，从而更新校验位数据PMDj(也就是错误检查和校正码)。Incidentally, the syndrome generation and decoding unit 150 may also transmit the syndrome write data NSDj to the parity bit reading and writing unit 140 to be written into the parity bit memory array 120 as the corresponding parity bit data PMDj. , thereby updating the parity bit data PMDj (that is, the error checking and correction code).

以下对本案数据读写与校正部中的详细结构举例进行说明。图2A是依照本发明一实施例的数据读写与校正部的电路示意图。如图2A所示，数据读写与校正部130包括多个读取放大器210、多个数据校正器220以及多个写入放大器230。各个读取放大器210从数据存储器阵列110读取并放大应用数据MDi，以产生对应的第一应用读取数据RDi与第二应用读取数据MDi’。The following is an example of the detailed structure of the data reading, writing and correction department in this case. FIG. 2A is a circuit schematic diagram of a data reading, writing and correction unit according to an embodiment of the present invention. As shown in FIG. 2A , the data reading, writing and correcting unit 130 includes a plurality of read amplifiers 210 , a plurality of data correctors 220 and a plurality of write amplifiers 230 . Each read amplifier 210 reads and amplifies the application data MDi from the data memory array 110 to generate corresponding first application read data RDi and second application read data MDi'.

各个数据校正器220耦接对应的读取放大器210。数据校正器220可锁存第二应用读取数据MDi’，且根据所接收到的校验比较数据SDi校正第二应用读取数据MDi’以产生正确的输出数据DOUTi，并且输出对应的校正数据SCDi至写入放大器230。Each data corrector 220 is coupled to a corresponding sense amplifier 210 . The data corrector 220 can latch the second application read data MDi', and correct the second application read data MDi' according to the received verification comparison data SDi to generate correct output data DOUTi, and output the corresponding correction data. SCDi to write amplifier 230.

各个写入放大器230耦接对应的数据校正器220。这些写入放大器230可根据校正数据SCDi以及校验比较数据SDi将校正后的应用数据MDi(即等于输出数据DOUTi)写回至数据存储器阵列110。Each write amplifier 230 is coupled to the corresponding data corrector 220 . These write amplifiers 230 can write the corrected application data MDi (ie, equal to the output data DOUTi) back to the data memory array 110 according to the correction data SCDi and the verification comparison data SDi.

此外，输入至读取放大器210、数据校正器220以及写入放大器230的预充电信号PB、读取放大器致能信号DE、读取数据锁存信号LAR、输出致能信号OE以及写入放大器致能信号WE是作为用于读取操作的控制信号，写入放大器致能信号WE以及写入数据锁存信号LAW则是作为用于写入操作的控制信号，这些控制信号可例如是由中央处理单元(CPU)或是其他利用多个逻辑门所组成的逻辑电路来提供，但本发明并不依此为限。In addition, the precharge signal PB, the read amplifier enable signal DE, the read data latch signal LAR, the output enable signal OE and the write amplifier enable signal input to the read amplifier 210, the data corrector 220 and the write amplifier 230 The enable signal WE is used as a control signal for the read operation, and the write amplifier enable signal WE and the write data latch signal LAW are used as control signals for the write operation. These control signals can be, for example, processed by a central processing unit. It is provided by a unit (CPU) or other logic circuits composed of multiple logic gates, but the invention is not limited thereto.

图2B是依照本发明一实施例的半导体存储器装置的读取操作的时序波形示意图。请同时参照图1、图2A及图2B，对本案半导体存储器装置100在一个读取周期内(即选择信号CSL1、CSL2维持于高逻辑电平的期间)完成校正与读取的动作进行说明。如图2B所示，当要开始读取操作时(即时间点T1)，传送到读取放大器210的预充电信号PB会由高逻辑电平(High)变为低逻辑电平(Low)，以结束预充电动作。同时，用以选择数据存储器阵列110的选择信号CSL1与用以选择校验位存储器阵列120的选择信号CSL2会由低逻辑电平变为高逻辑电平，以读取所选择的存储单元，从而输出对应的应用数据MDi与校验位数据PMDj。应用数据MDi包括正应用数据MDiT以及反应用数据MDiN。校验位数据PMDj包括正校验位数据PMDjT以及反校验位数据PMDjN。FIG. 2B is a timing waveform diagram of a read operation of a semiconductor memory device according to an embodiment of the present invention. Please refer to FIG. 1 , FIG. 2A and FIG. 2B at the same time to describe the correction and reading operations of the semiconductor memory device 100 of the present invention in one read cycle (ie, the period during which the selection signals CSL1 and CSL2 are maintained at a high logic level). As shown in FIG. 2B , when the read operation is to be started (i.e., time point T1 ), the precharge signal PB sent to the read amplifier 210 will change from a high logic level (High) to a low logic level (Low). to end the precharge action. At the same time, the selection signal CSL1 used to select the data memory array 110 and the selection signal CSL2 used to select the parity bit memory array 120 will change from a low logic level to a high logic level to read the selected memory cell, thereby Output the corresponding application data MDi and parity bit data PMDj. Application data MDi includes positive application data MDiT and reaction data MDiN. The parity data PMDj includes positive parity data PMDjT and negative parity data PMDjN.

接着，于时间点T2，传送到读取放大器210的读取放大器致能信号DE会由低逻辑电平变为高逻辑电平，藉此使各个读取放大器210可开始输出第二应用读取数据MDi’，并且产生对应的第一应用读取数据RDi。Then, at time point T2, the read amplifier enable signal DE sent to the sense amplifier 210 will change from a low logic level to a high logic level, thereby allowing each sense amplifier 210 to start outputting the second application read signal. data MDi', and generate corresponding first application read data RDi.

之后，如图2B所示，传送到各个数据校正器220的读取数据锁存信号LAR逻辑电平会由低变高(如时间点T3)，再由高变低(如时间点T4)，藉此使各个数据校正器220锁存第二应用读取数据MDi’，并产生对应的正锁存比特信号EiT以及反锁存比特信号EiN。After that, as shown in FIG. 2B , the logic level of the read data latch signal LAR transmitted to each data corrector 220 will change from low to high (such as time point T3), and then from high to low (such as time point T4). Thereby, each data corrector 220 latches the second application read data MDi', and generates the corresponding positive latching bit signal EiT and inverse latching bit signal EiN.

另一方面，在同一个应用数据MDi的读取周期内，接收到第一应用读取数据RDi的伴随式产生与解码部150可使用第一读取数据RDi进行伴随式运算，以产生伴随式写入数据NSDj。所述伴随式运算可例如依据查找表的方式来实现，其实施与操作可由现有技术实现。并且，伴随式产生与解码部150可将伴随式写入数据NSDj与校验位读取数据PRDj进行比较，例如进行互斥或运算，以产生比特错误信号SYj(如时间点T4)。On the other hand, in the reading cycle of the same application data MDi, the syndrome generation and decoding unit 150 that receives the first application read data RDi can use the first read data RDi to perform syndrome operations to generate the syndrome Write data NSDj. The adjoint operation can be implemented, for example, based on a lookup table, and its implementation and operation can be implemented by existing technologies. Furthermore, the syndrome generation and decoding unit 150 may compare the syndrome write data NSDj and the check bit read data PRDj, for example, perform a mutual exclusive OR operation to generate a bit error signal SYj (eg, time point T4).

在所读取的应用数据MDi发生一个错误比特时，部分的比特错误信号SYj可对应于错误比特的位置而由低逻辑电平变为高逻辑电平。如图2B所示，当伴随式产生与解码部150接收到的校验比较致能信号SDE的逻辑电平由低逻辑电平变为高逻辑电平时(如时间点T5)，伴随式产生与解码部150可经由对比特错误信号SYj进行解码以获得错误比特的位置，并将对应于错误位置的一个校验比较数据SDi由低逻辑电平变为高逻辑电平。When an erroneous bit occurs in the read application data MDi, part of the bit error signal SYj may change from a low logic level to a high logic level corresponding to the position of the erroneous bit. As shown in FIG. 2B , when the logic level of the check comparison enable signal SDE received by the syndrome generation and decoding unit 150 changes from a low logic level to a high logic level (such as time point T5), the syndrome generation and decoding unit 150 generates and The decoding part 150 may obtain the position of the error bit by decoding the bit error signal SYj, and change a check comparison data SDi corresponding to the error position from a low logic level to a high logic level.

因此，在同一个应用数据MDi的读取周期内，锁存了错误比特的数据校正器220会接收到变为高逻辑电平的校验比较数据SDi，藉此将错误比特的值进行反转，从而产生反转的正锁存比特信号EiT以及反锁存比特信号EiN。Therefore, in the same reading cycle of the application data MDi, the data corrector 220 that has latched the error bit will receive the check comparison data SDi that becomes a high logic level, thereby inverting the value of the error bit. , thereby generating an inverted positive latched bit signal EiT and an inverted latched bit signal EiN.

之后，传送到各个数据校正器220的输出致能信号OE会由低逻辑电平变为高逻辑电平(如时间点T6)。各个数据校正器220可根据输出致能信号OE与对应的正锁存比特信号EiT以及反锁存比特信号EiN，产生输出数据DOUTi与校正数据SCDi。藉此，在读取周期内，数据读写与校正部130可输出校正后的输出数据DOUTi，并将校正数据SCDi传送到对应的写入放大器230中。Afterwards, the output enable signal OE sent to each data corrector 220 will change from a low logic level to a high logic level (eg, time point T6). Each data corrector 220 can generate output data DOUTi and correction data SCDi according to the output enable signal OE and the corresponding positive latch bit signal EiT and inverse latch bit signal EiN. Thereby, during the read cycle, the data reading, writing and correction unit 130 can output the corrected output data DOUTi, and transmit the correction data SCDi to the corresponding write amplifier 230.

在同一个应用数据MDi的读取周期内，各个写入放大器230可根据接收到的校正数据SCDi以及校验比较数据SDi将校正后的应用数据MDi写入至数据存储器阵列110。具体来说，写入数据锁存信号LAW在读取周期内会保持在低逻辑电平。当写入放大器致能信号WE由低逻辑电平变为高逻辑电平时，写入放大器230可根据校正数据SCDi与由低逻辑电平变为高逻辑电平的校验比较数据SDi，产生校正后的应用数据MDi，并将校正后的应用数据MDi写入至发生错误比特的存储单元中。In the same reading cycle of the application data MDi, each write amplifier 230 can write the corrected application data MDi to the data memory array 110 according to the received correction data SCDi and the verification comparison data SDi. Specifically, the write data latch signal LAW remains at a low logic level during the read cycle. When the write amplifier enable signal WE changes from a low logic level to a high logic level, the write amplifier 230 can generate a correction according to the correction data SCDi and the check comparison data SDi that changes from a low logic level to a high logic level. The corrected application data MDi is obtained, and the corrected application data MDi is written into the storage unit where the erroneous bit occurs.

顺带一提，若在所读取的应用数据MDi中不具有错误比特，所有校验比较数据SDi会保持在低逻辑电平，数据读写与校正部130不会对所读取的应用数据MDi进行校正，而直接将所读取的应用数据MDi作为输出数据DOUTi而输出。By the way, if there are no erroneous bits in the read application data MDi, all the check comparison data SDi will remain at a low logic level, and the data reading, writing and correction unit 130 will not modify the read application data MDi. Correction is performed, and the read application data MDi is directly output as the output data DOUTi.

基于上述的读取操作，本发明实施例的半导体存储器装置100能够在同一个读取周期中(即选择信号CSL1、CSL2维持于高逻辑电平的期间)检查出间歇性地随机产生错误比特的所在位置并即时地进行校正，以确保下次读取时数据的正确性。Based on the above read operation, the semiconductor memory device 100 of the embodiment of the present invention can detect intermittently randomly generated erroneous bits in the same read cycle (that is, the period during which the selection signals CSL1 and CSL2 are maintained at a high logic level). position and perform corrections on the fly to ensure the data is correct the next time it is read.

图3是依照本发明一实施例的读取放大器的电路示意图。各读取放大器210包括第一开关310、预充电电路320以及放大电路330。请一并参照图2B与图3，在应用数据MDi的读取操作上，预充电电路320可先根据低逻辑电平的预充电信号PB结束预充电动作。接着，第一开关310可根据高逻辑电平的读取放大器致能信号DE导通，藉此使放大电路330对正应用数据MDiT以及反应用数据MDiN的电位差进行放大，以输出第二应用读取数据MDi’(包括正第二应用读取数据MDiT’以及反第二应用读取数据MDiN’)以及对应的第一应用读取数据RDi。FIG. 3 is a schematic circuit diagram of a sense amplifier according to an embodiment of the present invention. Each sense amplifier 210 includes a first switch 310 , a precharge circuit 320 and an amplification circuit 330 . Please refer to FIG. 2B and FIG. 3 together. In the reading operation of the application data MDi, the precharge circuit 320 may first end the precharge operation according to the precharge signal PB of a low logic level. Then, the first switch 310 can be turned on according to the high logic level read amplifier enable signal DE, thereby causing the amplification circuit 330 to amplify the potential difference between the positive application data MDiT and the response data MDiN to output the second application The read data MDi' (including the positive second application read data MDiT' and the reverse second application read data MDiN') and the corresponding first application read data RDi.

第一开关310的第一端耦接对应的正应用数据MDiT以及反应用数据MDiN，第一开关310的控制端耦接读取放大器致能信号DE。第一开关310例如包括第一N型场效晶体管QN1、第一P型场效晶体管QP1、第二N型场效晶体管QN2、第二P型场效晶体管QP2、第一反相器INV1以及第二反相器INV2。第一N型场效晶体管QN1的漏极耦接正应用数据MDiT。第一P型场效晶体管QP1的源极耦接第一N型场效晶体管QN1的漏极，第一P型场效晶体管QP1漏极耦接第一N型场效晶体管QN1的源极。第二N型场效晶体管QN2的漏极耦接反应用数据MDiN。第二P型场效晶体管QP2的源极耦接第二N型场效晶体管QN2的漏极，第二P型场效晶体管QP2漏极耦接第二N型场效晶体管QN2的源极。第一反相器INV1的输入端耦接读取放大器致能信号DE，第一反相器INV1的输出端耦接第一N型场效晶体管QN1的栅极及第二N型场效晶体管QN2的栅极。第二反相器INV2的输入端耦接第一反相器INV1的输出端，第二反相器INV2的输出端耦接第一P型场效晶体管QP1的栅极及第二P型场效晶体管QP1的栅极。通过上述结构，第一开关310可根据读取放大器致能信号DE进行导通或断开。The first terminal of the first switch 310 is coupled to the corresponding active application data MDiT and the response data MDiN, and the control terminal of the first switch 310 is coupled to the read amplifier enable signal DE. The first switch 310 includes, for example, a first N-type field effect transistor QN1, a first P-type field effect transistor QP1, a second N-type field effect transistor QN2, a second P-type field effect transistor QP2, a first inverter INV1 and a third Two inverters INV2. The drain of the first N-type field effect transistor QN1 is coupled to the positive application data MDiT. The source of the first P-type field effect transistor QP1 is coupled to the drain of the first N-type field effect transistor QN1, and the drain of the first P-type field effect transistor QP1 is coupled to the source of the first N-type field effect transistor QN1. The drain of the second N-type field effect transistor QN2 is coupled to reflect the data MDiN. The source of the second P-type field effect transistor QP2 is coupled to the drain of the second N-type field effect transistor QN2, and the drain of the second P-type field effect transistor QP2 is coupled to the source of the second N-type field effect transistor QN2. The input terminal of the first inverter INV1 is coupled to the sense amplifier enable signal DE, and the output terminal of the first inverter INV1 is coupled to the gate of the first N-type field effect transistor QN1 and the second N-type field effect transistor QN2 the gate. The input terminal of the second inverter INV2 is coupled to the output terminal of the first inverter INV1. The output terminal of the second inverter INV2 is coupled to the gate of the first P-type field effect transistor QP1 and the second P-type field effect transistor QP1. Gate of transistor QP1. Through the above structure, the first switch 310 can be turned on or off according to the read amplifier enable signal DE.

预充电电路320耦接第一开关310的第一端，且接收预充电信号PB。预充电电路320例如包括第三反相器INV3、第三P型场效晶体管QP3、第四P型场效晶体管QP4以及第五P型场效晶体管QP5。第三反相器INV3的输入端耦接预充电信号PB。第三P型场效晶体管QP3的源极耦接动作电压VDD，第三P型场效晶体管QP3的栅极耦接第三反相器INV3的输出端，第三P型场效晶体管QP3的漏极耦接第一N型场效晶体管QN1的漏极。第四P型场效晶体管QP4的源极耦接动作电压VDD，第四P型场效晶体管QP4的栅极耦接第三反相器INV3的输出端，第四P型场效晶体管QP4的漏极耦接第二N型场效晶体管QN2的漏极。第五P型场效晶体管QP5的源极耦接第三P型场效晶体管QP3的漏极，第五P型场效晶体管QP5的栅极耦接第四P型场效晶体管QP4的栅极，第五P型场效晶体管QP5的漏极耦接第四P型场效晶体管QP4的漏极。通过上述结构，预充电电路320可根据预充电信号PB对第一开关310的第一端进行预充电。The precharge circuit 320 is coupled to the first terminal of the first switch 310 and receives the precharge signal PB. The precharge circuit 320 includes, for example, a third inverter INV3, a third P-type field effect transistor QP3, a fourth P-type field effect transistor QP4, and a fifth P-type field effect transistor QP5. The input terminal of the third inverter INV3 is coupled to the precharge signal PB. The source of the third P-type field effect transistor QP3 is coupled to the operating voltage VDD, the gate of the third P-type field effect transistor QP3 is coupled to the output terminal of the third inverter INV3, and the drain of the third P-type field effect transistor QP3 The pole is coupled to the drain of the first N-type field effect transistor QN1. The source of the fourth P-type field effect transistor QP4 is coupled to the operating voltage VDD, the gate of the fourth P-type field effect transistor QP4 is coupled to the output terminal of the third inverter INV3, and the drain of the fourth P-type field effect transistor QP4 The pole is coupled to the drain of the second N-type field effect transistor QN2. The source of the fifth P-type field effect transistor QP5 is coupled to the drain of the third P-type field effect transistor QP3, and the gate of the fifth P-type field effect transistor QP5 is coupled to the gate of the fourth P-type field effect transistor QP4. The drain of the fifth P-type field effect transistor QP5 is coupled to the drain of the fourth P-type field effect transistor QP4. Through the above structure, the precharge circuit 320 can precharge the first terminal of the first switch 310 according to the precharge signal PB.

放大电路330的输入端耦接第一开关310的第二端，放大电路330的控制端耦接读取放大器致能信号DE。放大电路330例如包括第六P型场效晶体管QP6、第七P型场效晶体管QP7、第三N型场效晶体管QN3、第四N型场效晶体管QN4、第五N型场效晶体管QN5以及第四反相器INV4。第六P型场效晶体管QP6的源极耦接动作电压VDD，第六P型场效晶体管QP6的漏极耦接第一N型场效晶体管QN1的源极。第七P型场效晶体管QP7的源极耦接动作电压VDD，第七P型场效晶体管QP7的漏极耦接第二N型场效晶体管QN2的源极。第三N型场效晶体管QN3的漏极耦接第六P型场效晶体管QP6的漏极及第七P型场效晶体管QP7的栅极，并输出正第二应用读取数据MDiT’，第三N型场效晶体管QN3的栅极耦接第七P型场效晶体管QP7的漏极。第四N型场效晶体管QN4的漏极耦接第七P型场效晶体管QP7的漏极及第六P型场效晶体管QP6的栅极，并输出反第二应用读取数据MDiN’，第四N型场效晶体管QN4的栅极耦接第六P型场效晶体管QP6的漏极。第五N型场效晶体管QN5的漏极耦接第三N型场效晶体管QN3的源极及第四N型场效晶体管QN4的源极，第五N型场效晶体管QN5的栅极耦接读取放大器致能信号DE，第五N型场效晶体管QN5的源极耦接接地电压GND。第四反相器INV4的输入端耦接第四N型场效晶体管QN4的漏极，第四反相器INV4的输出端输出第一应用读取数据RDi。通过上述结构，放大电路330可根据读取放大器致能信号DE输出第二应用读取数据MDi’以及对应的第一应用读取数据RDi。另外，输出正第二应用读取数据MDiT’的输出端也可耦接一个输出端开路的反相器INVA，使正第二应用读取数据MDiT’的输出端与反第二应用读取数据MDiN’的输出端的负载一致。The input terminal of the amplifier circuit 330 is coupled to the second terminal of the first switch 310, and the control terminal of the amplifier circuit 330 is coupled to the read amplifier enable signal DE. The amplifier circuit 330 includes, for example, a sixth P-type field effect transistor QP6, a seventh P-type field effect transistor QP7, a third N-type field effect transistor QN3, a fourth N-type field effect transistor QN4, a fifth N-type field effect transistor QN5, and The fourth inverter INV4. The source of the sixth P-type field effect transistor QP6 is coupled to the operating voltage VDD, and the drain of the sixth P-type field effect transistor QP6 is coupled to the source of the first N-type field effect transistor QN1. The source of the seventh P-type field effect transistor QP7 is coupled to the operating voltage VDD, and the drain of the seventh P-type field effect transistor QP7 is coupled to the source of the second N-type field effect transistor QN2. The drain of the third N-type field effect transistor QN3 is coupled to the drain of the sixth P-type field effect transistor QP6 and the gate of the seventh P-type field effect transistor QP7, and outputs positive second application read data MDiT'. The gate of the third N-type field effect transistor QN3 is coupled to the drain of the seventh P-type field effect transistor QP7. The drain of the fourth N-type field effect transistor QN4 is coupled to the drain of the seventh P-type field effect transistor QP7 and the gate of the sixth P-type field effect transistor QP6, and outputs the reverse second application read data MDiN'. The gate of the fourth N-type field effect transistor QN4 is coupled to the drain of the sixth P-type field effect transistor QP6. The drain of the fifth N-type field effect transistor QN5 is coupled to the source of the third N-type field effect transistor QN3 and the source of the fourth N-type field effect transistor QN4, and the gate of the fifth N-type field effect transistor QN5 is coupled to The amplifier enable signal DE is read, and the source of the fifth N-type field effect transistor QN5 is coupled to the ground voltage GND. The input terminal of the fourth inverter INV4 is coupled to the drain of the fourth N-type field effect transistor QN4, and the output terminal of the fourth inverter INV4 outputs the first application read data RDi. Through the above structure, the amplifying circuit 330 can output the second application read data MDi' and the corresponding first application read data RDi according to the read amplifier enable signal DE. In addition, the output terminal that outputs the positive second application read data MDiT' can also be coupled to an inverter INVA with an open output terminal, so that the output terminal of the positive second application read data MDiT' is connected to the inverse second application read data The load on the output of MDiN' is uniform.

图4是依照本发明一实施例的数据校正器的电路示意图。各数据校正器220包括第二开关410、第一锁存电路420、校正电路430以及第一输出电路440。请一并参照图2B与图4，在应用数据MDi的读取操作上，第二开关410可先根据高逻辑电平的读取数据锁存信号LAR进行导通。接着，第一锁存电路420可锁存第二应用读取数据MDi’。当所读取的应用数据MDi存在一个错误比特时，对应于错误比特的数据校正器220中的校正电路430可接收到用以表示错误的校验比较数据SDi，以在同一个读取周期内对所锁存的第二应用读取数据MDi’进行校正，并输出对应的校正数据SCDi。第一输出电路440可根据高逻辑电平的输出致能信号OE输出对应的输出数据DOUTi。FIG. 4 is a schematic circuit diagram of a data corrector according to an embodiment of the present invention. Each data corrector 220 includes a second switch 410, a first latch circuit 420, a correction circuit 430 and a first output circuit 440. Please refer to FIG. 2B and FIG. 4 together. In the reading operation of the application data MDi, the second switch 410 may first be turned on according to the read data latch signal LAR of a high logic level. Then, the first latch circuit 420 may latch the second application read data MDi'. When there is an erroneous bit in the read application data MDi, the correction circuit 430 in the data corrector 220 corresponding to the erroneous bit can receive the verification comparison data SDi to indicate the error, so as to correct the error in the same reading cycle. The latched second application reads the data MDi' for correction and outputs the corresponding correction data SCDi. The first output circuit 440 may output corresponding output data DOUTi according to the high logic level output enable signal OE.

第二开关410的第一端耦接正第二应用读取数据MDiT’以及反第二应用读取数据MDiN’，第二开关410的控制端耦接读取数据锁存信号LAR。第二开关410包括第六N型场效晶体管QN6、第八P型场效晶体管QP8、第七N型场效晶体管QN7、第九P型场效晶体管QP9以及第五反相器INV5。第六N型场效晶体管QN6的漏极耦接正第二应用读取数据MDiT’，第六N型场效晶体管QN6的栅极耦接读取数据锁存信号LAR。第八P型场效晶体管QP8的源极耦接第六N型场效晶体管QN6的漏极，第八P型场效晶体管QP8的漏极耦接第六N型场效晶体管QN6的源极。第七N型场效晶体管QN7的漏极耦接反第二应用读取数据MDiN’，第七N型场效晶体管QN7的栅极耦接读取数据锁存信号LAR。第九P型场效晶体管QP9的源极耦接第七N型场效晶体管QN7的漏极，第九P型场效晶体管QP9的漏极耦接第七N型场效晶体管QN7的源极。第五反相器INV5输入端耦接读取数据锁存信号LAR，第五反相器INV5的输出端耦接第八P型场效晶体管QP8的栅极及第九P型场效晶体管QP9的栅极。通过上述结构，第二开关410可根据读取数据锁存信号LAR进行导通或断开。The first terminal of the second switch 410 is coupled to the positive second application read data MDiT' and the negative second application read data MDiN', and the control terminal of the second switch 410 is coupled to the read data latch signal LAR. The second switch 410 includes a sixth N-type field effect transistor QN6, an eighth P-type field effect transistor QP8, a seventh N-type field effect transistor QN7, a ninth P-type field effect transistor QP9 and a fifth inverter INV5. The drain of the sixth N-type field effect transistor QN6 is coupled to the second application read data MDiT', and the gate of the sixth N-type field effect transistor QN6 is coupled to the read data latch signal LAR. The source of the eighth P-type field effect transistor QP8 is coupled to the drain of the sixth N-type field effect transistor QN6, and the drain of the eighth P-type field effect transistor QP8 is coupled to the source of the sixth N-type field effect transistor QN6. The drain of the seventh N-type field effect transistor QN7 is coupled to the second application read data MDiN', and the gate of the seventh N-type field effect transistor QN7 is coupled to the read data latch signal LAR. The source of the ninth P-type field effect transistor QP9 is coupled to the drain of the seventh N-type field effect transistor QN7, and the drain of the ninth P-type field effect transistor QP9 is coupled to the source of the seventh N-type field effect transistor QN7. The input terminal of the fifth inverter INV5 is coupled to the read data latch signal LAR, and the output terminal of the fifth inverter INV5 is coupled to the gate of the eighth P-type field effect transistor QP8 and the gate of the ninth P-type field effect transistor QP9. gate. Through the above structure, the second switch 410 can be turned on or off according to the read data latch signal LAR.

第一锁存电路420耦接第二开关410的第二端，用以锁存第二应用读取数据MDi’，并输出正锁存比特信号EiT与反锁存比特信号EiN至校正电路430。第一锁存电路420可通过已知的锁存电路来实现。举例而言，第一锁存电路可包括两个反向器，其中一反向器的输入端耦接另一反向器的输出端，且其中一反向器的输出端耦接另一反向器的输入端。The first latch circuit 420 is coupled to the second end of the second switch 410 for latching the second application read data MDi', and outputs the positive latching bit signal EiT and the inverse latching bit signal EiN to the correction circuit 430. The first latch circuit 420 may be implemented by a known latch circuit. For example, the first latch circuit may include two inverters, the input terminal of one inverter is coupled to the output terminal of the other inverter, and the output terminal of one of the inverters is coupled to the other inverter. input terminal of the controller.

校正电路430耦接第一锁存电路420，且接收对应的校验比较数据SDi。校正电路430包括第六反相器INV6、第十P型场效晶体管QP10、第十一P型场效晶体管QP11、第十二P型场效晶体管QP12、第十三P型场效晶体管以及第七反相器INV7。第六反相器INV6的输入端耦接校验比较数据SDi。第十P型场效晶体管QP10的源极耦接动作电压VDD，第十P型场效晶体管QP10的栅极耦接第六反相器INV6的输出端。第十一P型场效晶体管QP11的源极耦接第十P型场效晶体管QP10的漏极，第十一P型场效晶体管QP11的栅极耦接正第二应用读取数据MDiT’，第十一P型场效晶体管QP11的漏极耦接第一锁存电路420。第十二P型场效晶体管QP12的源极耦接动作电压VDD，第十二P型场效晶体管QP12的栅极耦接第六反相器INV6的输出端。第十三P型场效晶体管QP13的源极耦接第十二P型场效晶体管QP12的漏极，第十三P型场效晶体管QP13的栅极耦接反第二应用读取数据MDiN’，第十三P型场效晶体管QP13的漏极耦接第一锁存电路420。第七反相器INV7的输入端耦接第一锁存电路420，第七反相器INV7的输出端输出校正数据SCDi。通过上述结构，校正电路430可根据校验比较数据SDi对锁存电路420所锁存的第二应用读取数据MDi’进行校正，以输出对应的校正数据SCDi。The correction circuit 430 is coupled to the first latch circuit 420 and receives the corresponding verification comparison data SDi. The correction circuit 430 includes a sixth inverter INV6, a tenth P-type field effect transistor QP10, an eleventh P-type field effect transistor QP11, a twelfth P-type field effect transistor QP12, a thirteenth P-type field effect transistor and a third Seven inverters INV7. The input terminal of the sixth inverter INV6 is coupled to the verification comparison data SDi. The source of the tenth P-type field effect transistor QP10 is coupled to the operating voltage VDD, and the gate of the tenth P-type field effect transistor QP10 is coupled to the output terminal of the sixth inverter INV6. The source of the eleventh P-type field effect transistor QP11 is coupled to the drain of the tenth P-type field effect transistor QP10, and the gate of the eleventh P-type field effect transistor QP11 is coupled to the positive second application read data MDiT', The drain of the eleventh P-type field effect transistor QP11 is coupled to the first latch circuit 420 . The source of the twelfth P-type field effect transistor QP12 is coupled to the operating voltage VDD, and the gate of the twelfth P-type field effect transistor QP12 is coupled to the output terminal of the sixth inverter INV6. The source of the thirteenth P-type field effect transistor QP13 is coupled to the drain of the twelfth P-type field effect transistor QP12, and the gate of the thirteenth P-type field effect transistor QP13 is coupled to the second application read data MDiN' , the drain of the thirteenth P-type field effect transistor QP13 is coupled to the first latch circuit 420 . The input terminal of the seventh inverter INV7 is coupled to the first latch circuit 420, and the output terminal of the seventh inverter INV7 outputs the correction data SCDi. Through the above structure, the correction circuit 430 can correct the second application read data MDi' latched by the latch circuit 420 according to the verification comparison data SDi to output the corresponding correction data SCDi.

第一输出电路440耦接校正电路430，且接收输出致能信号OE。第一输出电路440包括第八反相器INV8、第一反及闸NAND1、第一反或闸NOR1、第十四P型场效晶体管QP14、第八N型场效晶体管QN8、第九反相器INV9以及第十反相器INV10。第八反相器INV8的输入端耦接输出致能信号OE。第一反及闸NAND1的第一输入端耦接第十一P型场效晶体管QP11的漏极，第一反及闸NAND1的第二输入端耦接输出致能信号OE。第一反或闸NOR1的第一输入端耦接第十一P型场效晶体管QP11的漏极，第一反或闸NOR1的第二输入端耦接第八反相器INV8的输出端。第十四P型场效晶体管QP14的源极耦接动作电压VDD，第十四P型场效晶体管QP14的栅极耦接第一反及闸NAND1的输出端。第八N型场效晶体管QN8的漏极耦接第十四P型场效晶体管QP14的漏极并输出校正后的输出数据DOUTi，第八N型场效晶体管QN8的栅极耦接第一反或闸NOR1的输出端，第八N型场效晶体管QN8的源极耦接接地电压GND。第九反相器INV9的输入端耦接第十四P型场效晶体管QP14的漏极。第十反相器INV10的输入端耦接第九反相器INV9的输出端，第十反相器INV10的输出端耦接第九反相器INV9的输入端。通过上述结构，第一输出电路440可根据输出致能信号OE输出对应的输出数据DOUTi。The first output circuit 440 is coupled to the correction circuit 430 and receives the output enable signal OE. The first output circuit 440 includes an eighth inverter INV8, a first inverter NAND1, a first inverter NOR1, a fourteenth P-type field effect transistor QP14, an eighth N-type field effect transistor QN8, a ninth inverter inverter INV9 and the tenth inverter INV10. The input terminal of the eighth inverter INV8 is coupled to the output enable signal OE. The first input terminal of the first NAND gate NAND1 is coupled to the drain of the eleventh P-type field effect transistor QP11, and the second input terminal of the first NAND gate NAND1 is coupled to the output enable signal OE. The first input terminal of the first NOR gate NOR1 is coupled to the drain of the eleventh P-type field effect transistor QP11, and the second input terminal of the first NOR gate NOR1 is coupled to the output terminal of the eighth inverter INV8. The source of the fourteenth P-type field effect transistor QP14 is coupled to the operating voltage VDD, and the gate of the fourteenth P-type field effect transistor QP14 is coupled to the output terminal of the first NAND gate NAND1. The drain of the eighth N-type field effect transistor QN8 is coupled to the drain of the fourteenth P-type field effect transistor QP14 and outputs the corrected output data DOUTi. The gate of the eighth N-type field effect transistor QN8 is coupled to the first inverter. The output terminal of the OR gate NOR1 and the source of the eighth N-type field effect transistor QN8 are coupled to the ground voltage GND. The input terminal of the ninth inverter INV9 is coupled to the drain of the fourteenth P-type field effect transistor QP14. The input terminal of the tenth inverter INV10 is coupled to the output terminal of the ninth inverter INV9, and the output terminal of the tenth inverter INV10 is coupled to the input terminal of the ninth inverter INV9. Through the above structure, the first output circuit 440 can output corresponding output data DOUTi according to the output enable signal OE.

图5是依照本发明一实施例的写入放大器的电路示意图。各写入放大器230包括第十一反相器INV11、第三开关510、第四开关520、第二锁存电路530以及第二输出电路540。第十一反相器INV11的输入端耦接对应的输出数据DOUTi。第二锁存电路530耦接第三开关510的第二端以及第四开关520的第二端。第二锁存电路530可通过已知的锁存电路来实现。FIG. 5 is a circuit schematic diagram of a write amplifier according to an embodiment of the present invention. Each write amplifier 230 includes an eleventh inverter INV11, a third switch 510, a fourth switch 520, a second latch circuit 530, and a second output circuit 540. The input terminal of the eleventh inverter INV11 is coupled to the corresponding output data DOUTi. The second latch circuit 530 is coupled to the second terminal of the third switch 510 and the second terminal of the fourth switch 520 . The second latch circuit 530 may be implemented by a known latch circuit.

请一并参照图2B与图5，在同一个应用数据MDi的读取周期内，由于写入数据锁存信号LAW会保持在低逻辑电平，因此第三开关510会断开。第四开关520可依据变为高逻辑电平的校验比较数据SDi而读入校正数据SCDi。藉此，第二输出电路540可根据校正数据SCDi以及校验比较数据SDi输出校正后的应用数据MDi(包括正应用数据MDiT以及反应用数据MDiN)。Please refer to FIG. 2B and FIG. 5 together. In the same reading cycle of the application data MDi, since the write data latch signal LAW will remain at a low logic level, the third switch 510 will be turned off. The fourth switch 520 may read in the correction data SCDi according to the verification comparison data SDi that becomes a high logic level. Thereby, the second output circuit 540 can output the corrected application data MDi (including the positive application data MDiT and the reaction data MDiN) according to the correction data SCDi and the verification comparison data SDi.

第三开关510的第一端耦接第十一反相器INV11的输出端，第三开关510的控制端耦接写入数据锁存信号LAW。第三开关510包括第九N型场效晶体管QN9、第十四P型场效晶体管QP14以及第十二反相器INV12。第九N型场效晶体管QN9的漏极耦接第十一反相器INV11的输出端，第九N型场效晶体管QN9的栅极耦接写入数据锁存信号LAW。第十四P型场效晶体管QP14的源极耦接第九N型场效晶体管QN9的漏极，第十四P型场效晶体管QP14的漏极耦接第九N型场效晶体管QN9的源极。第十二反相器INV12的输入端耦接写入数据锁存信号LAW，第十二反相器INV12的输出端耦接第十四P型场效晶体管QP14的栅极。通过上述结构，第三开关510可根据写入数据锁存信号LAW进行导通或断开。The first terminal of the third switch 510 is coupled to the output terminal of the eleventh inverter INV11, and the control terminal of the third switch 510 is coupled to the write data latch signal LAW. The third switch 510 includes a ninth N-type field effect transistor QN9, a fourteenth P-type field effect transistor QP14, and a twelfth inverter INV12. The drain of the ninth N-type field effect transistor QN9 is coupled to the output terminal of the eleventh inverter INV11, and the gate of the ninth N-type field effect transistor QN9 is coupled to the write data latch signal LAW. The source of the fourteenth P-type field effect transistor QP14 is coupled to the drain of the ninth N-type field effect transistor QN9. The drain of the fourteenth P-type field effect transistor QP14 is coupled to the source of the ninth N-type field effect transistor QN9. pole. The input terminal of the twelfth inverter INV12 is coupled to the write data latch signal LAW, and the output terminal of the twelfth inverter INV12 is coupled to the gate of the fourteenth P-type field effect transistor QP14. Through the above structure, the third switch 510 can be turned on or off according to the write data latch signal LAW.

第四开关520的第一端耦接对应的校正数据SCDi，第四开关520的控制端耦接对应的校验比较数据SDi。第四开关520包括第十N型场效晶体管QN10、第十五P型场效晶体管QP15以及第十三反相器INV13。第十N型场效晶体管QN10的漏极耦接校正数据SCDi，第十N型场效晶体管QN10的栅极耦接校验比较数据SDi。第十五P型场效晶体管QP15的源极耦接第十N型场效晶体管QN10的漏极，第十五P型场效晶体管QP15的漏极耦接第十N型场效晶体管QN10的源极。第十三反相器INV13的输入端耦接校验比较数据SDi，第十三反相器INV13的输出端耦接第十五P型场效晶体管QP15的栅极。通过上述结构，第四开关520可根据校验比较数据SDi进行导通或断开。The first terminal of the fourth switch 520 is coupled to the corresponding correction data SCDi, and the control terminal of the fourth switch 520 is coupled to the corresponding verification comparison data SDi. The fourth switch 520 includes a tenth N-type field effect transistor QN10, a fifteenth P-type field effect transistor QP15, and a thirteenth inverter INV13. The drain coupling correction data SCDi of the tenth N-type field effect transistor QN10, and the gate coupling verification comparison data SDi of the tenth N-type field effect transistor QN10. The source of the fifteenth P-type field effect transistor QP15 is coupled to the drain of the tenth N-type field effect transistor QN10, and the drain of the fifteenth P-type field effect transistor QP15 is coupled to the source of the tenth N-type field effect transistor QN10. pole. The input terminal of the thirteenth inverter INV13 is coupled to the verification comparison data SDi, and the output terminal of the thirteenth inverter INV13 is coupled to the gate of the fifteenth P-type field effect transistor QP15. Through the above structure, the fourth switch 520 can be turned on or off according to the verification comparison data SDi.

第二输出电路540耦接第四开关520的第二端以及第二锁存电路530。第二输出电路540包括第二反或闸NOR2、第十四反相器INV14、第二反及闸NAND2、第三反或闸NOR3、第十六P型场效晶体管QP16、第十一N型场效晶体管QN11、第三反及闸NAND3、第四反或闸NOR4、第十七P型场效晶体管QP17以及第十二N型场效晶体管QN12。第二反或闸NOR2的第一输入端耦接写入放大器致能信号WE，第二反或闸NOR2的第二输入端耦接校验比较数据SDi。第十四反相器INV14的输入端耦接第二反或闸NOR2的输出端。第二反及闸NAND2的第一输入端耦接第二锁存电路530，第二反及闸NAND2的第二输入端耦接第十四反相器INV14的输出端。第三反或闸NOR3的第一输入端耦接第二锁存电路530，第三反或闸NOR3的第二输入端耦接第二反或闸NOR2的输出端。第十六P型场效晶体管QP16的源极耦接动作电压VDD，第十六P型场效晶体管QP16的栅极耦接第二反及闸NAND2的输出端。第十一N型场效晶体管QN11的漏极耦接第十六P型场效晶体管QP16的漏极并输出对应的正应用数据MDiT，第十一N型场效晶体管QN11的栅极耦接第三反或闸NOR3的输出端，第十一N型场效晶体管QN11的源极耦接接地电压GND。第三反及闸NAND3的第一输入端耦接第二锁存电路530及第四开关520的第二端，第三反及闸NAND3的第二输入端耦接第十四反相器INV14的输出端。第四反或闸NOR4的第一输入端耦接第二锁存电路530及第四开关520的第二端，第四反或闸NOR4的第二输入端耦接第二反或闸NOR2的输出端。第十七P型场效晶体管QP17的源极耦接动作电压VDD，第十七P型场效晶体管QP17的栅极耦接第三反及闸NAND3的输出端。第十二N型场效晶体管QN12的漏极耦接第十七P型场效晶体管QP17的漏极并输出对应的反应用数据MDiN，第十二N型场效晶体管QN12的栅极耦接第四反或闸NOR4的输出端，第十二N型场效晶体管QN12的源极耦接接地电压GND。通过上述结构，第二输出电路540可根据写入放大器致能信号WE、对应的校验比较数据SDi以及校正数据SCDi输出校正后的应用数据MDi。The second output circuit 540 is coupled to the second terminal of the fourth switch 520 and the second latch circuit 530 . The second output circuit 540 includes a second inverter NOR2, a fourteenth inverter INV14, a second inverter NAND2, a third inverter NOR3, a sixteenth P-type field effect transistor QP16, an eleventh N-type The field effect transistor QN11, the third inversion NAND gate NAND3, the fourth inversion NOR gate NOR4, the seventeenth P-type field effect transistor QP17 and the twelfth N-type field effect transistor QN12. The first input terminal of the second NOR gate NOR2 is coupled to the write amplifier enable signal WE, and the second input terminal of the second NOR gate NOR2 is coupled to the verification comparison data SDi. The input terminal of the fourteenth inverter INV14 is coupled to the output terminal of the second inverter NOR2. The first input terminal of the second NAND gate NAND2 is coupled to the second latch circuit 530 , and the second input terminal of the second NAND gate NAND2 is coupled to the output terminal of the fourteenth inverter INV14 . The first input terminal of the third NOR gate NOR3 is coupled to the second latch circuit 530 , and the second input terminal of the third NOR gate NOR3 is coupled to the output terminal of the second NOR gate NOR2 . The source of the sixteenth P-type field effect transistor QP16 is coupled to the operating voltage VDD, and the gate of the sixteenth P-type field effect transistor QP16 is coupled to the output terminal of the second inverter gate NAND2. The drain of the eleventh N-type field effect transistor QN11 is coupled to the drain of the sixteenth P-type field effect transistor QP16 and outputs the corresponding positive application data MDiT. The gate of the eleventh N-type field effect transistor QN11 is coupled to the drain of the sixteenth P-type field effect transistor QP16. The output terminal of the triple inverter NOR gate NOR3 and the source of the eleventh N-type field effect transistor QN11 are coupled to the ground voltage GND. The first input terminal of the third NAND gate NAND3 is coupled to the second latch circuit 530 and the second terminal of the fourth switch 520. The second input terminal of the third NAND gate NAND3 is coupled to the fourteenth inverter INV14. output terminal. The first input terminal of the fourth NOR gate NOR4 is coupled to the second latch circuit 530 and the second terminal of the fourth switch 520 , and the second input terminal of the fourth NOR gate NOR4 is coupled to the output of the second NOR gate NOR2 end. The source of the seventeenth P-type field effect transistor QP17 is coupled to the operating voltage VDD, and the gate of the seventeenth P-type field effect transistor QP17 is coupled to the output terminal of the third NAND gate NAND3. The drain of the twelfth N-type field effect transistor QN12 is coupled to the drain of the seventeenth P-type field effect transistor QP17 and outputs the corresponding response data MDiN. The gate of the twelfth N-type field effect transistor QN12 is coupled to the drain of the seventeenth P-type field effect transistor QP17. The output terminal of the quad-IN-OR gate NOR4 and the source of the twelfth N-type field effect transistor QN12 are coupled to the ground voltage GND. Through the above structure, the second output circuit 540 can output the corrected application data MDi according to the write amplifier enable signal WE, the corresponding verification comparison data SDi and the correction data SCDi.

图6是依照本发明一实施例的校验位读写部的电路示意图。本发明实施例的校验位读写部140包括多个读取放大器610以及多个写入放大器620。多个读取放大器610从校验位存储器阵列120读取并放大校验位数据PMDj(PMD0～PMD6)，以产生对应的校验位读取数据PRDj(PRD0～PRD6)。FIG. 6 is a schematic circuit diagram of a check digit reading and writing unit according to an embodiment of the present invention. The parity bit reading and writing unit 140 in the embodiment of the present invention includes a plurality of read amplifiers 610 and a plurality of write amplifiers 620. The plurality of read amplifiers 610 read and amplify the parity data PMDj (PMD0˜PMD6) from the parity memory array 120 to generate corresponding parity read data PRDj (PRD0˜PRD6).

在图6中，各个写入放大器620耦接对应的读取放大器610。在需要更新校验位数据PMDj(也就是错误检查和校正码)时，这些写入放大器620可根据伴随式写入数据NSDj将校验位数据PMDj写入至校验位存储器阵列110。藉此，当伴随式产生与解码部150要进行伴随式运算时，再由多个读取放大器610进行读取。此时，伴随式写入数据NSDj与校验位数据PMDj实质上相等。读取放大器610以及写入放大器620的详细结构可由现有存储器读取电路及存储器写入电路的相关技术来实现，其细节就不赘述。In FIG. 6 , each write amplifier 620 is coupled to a corresponding read amplifier 610 . When the parity data PMDj (ie, the error checking and correction code) needs to be updated, these write amplifiers 620 can write the parity data PMDj to the parity memory array 110 according to the accompanying write data NSDj. Therefore, when the syndrome generation and decoding unit 150 wants to perform a syndrome operation, the plurality of read amplifiers 610 perform reading. At this time, the syndrome write data NSDj and the parity bit data PMDj are substantially equal. The detailed structures of the read amplifier 610 and the write amplifier 620 can be implemented by the related technologies of existing memory read circuits and memory write circuits, and the details will not be described again.

图7是依照本发明一实施例的伴随式产生与解码部的电路示意图。请参照图7，伴随式产生与解码部150包括伴随式产生器710、多个互斥或闸720以及伴随式解码器730。伴随式产生器710通过使用第一应用读取数据RDi(RD0～RD63)进行伴随式运算，以产生伴随式写入数据NSDj(NSD0～NSD6)。多个互斥或闸720可分别将对应的伴随式写入数据NSDj与对应的校验位读取数据PRDj进行互斥或运算，以产生比特错误信号SYj(SY0～SY6)。FIG. 7 is a schematic circuit diagram of an associated expression generation and decoding unit according to an embodiment of the present invention. Referring to FIG. 7 , the syndrome generation and decoding unit 150 includes a syndrome generator 710 , a plurality of mutually exclusive OR gates 720 , and a syndrome decoder 730 . The syndrome generator 710 performs a syndrome operation by using the first application read data RDi (RD0-RD63) to generate the syndrome write data NSDj (NSD0-NSD6). The plurality of mutually exclusive OR gates 720 can respectively perform a mutually exclusive OR operation on the corresponding syndrome write data NSDj and the corresponding check bit read data PRDj to generate bit error signals SYj (SY0˜SY6).

伴随式解码器730耦接多个互斥或闸720。伴随式解码器730可依据校验比较致能信号SDE将比特错误信号SYj进行解码以获得错误比特的位置，并藉此产生校验比较数据SDi(SD0～SD63)。伴随式产生器710及伴随式解码器730的详细结构可由现有伴随式编码及伴随式解码的相关技术来实现，其细节就不赘述。The syndrome decoder 730 is coupled to a plurality of mutually exclusive OR gates 720 . The syndrome decoder 730 can decode the bit error signal SYj according to the check comparison enable signal SDE to obtain the position of the error bit, and thereby generate the check comparison data SDi (SD0˜SD63). The detailed structures of the syndrome generator 710 and the syndrome decoder 730 can be implemented by existing technologies related to syndrome encoding and syndrome decoding, and the details will not be described again.

综上所述，当在数据的读取周期中发生了一个错误比特时，本发明的半导体存储器装置能够在同一个读取周期内即时地检查出错误比特的所在位置并进行校正。特别是针对因软错误而间歇性随机产生的错误比特，可避免累积到两个比特以上。藉此，对于采用单错误校正技术的存储器装置，可大幅提高数据的可靠度。In summary, when an erroneous bit occurs during the data reading cycle, the semiconductor memory device of the present invention can instantly detect the location of the erroneous bit and perform corrections within the same reading cycle. Especially for erroneous bits that are intermittently generated randomly due to soft errors, accumulation of more than two bits can be avoided. In this way, the reliability of data can be greatly improved for memory devices using single error correction technology.

虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中的技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求所界定的为准。Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Any person skilled in the art may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention is The protection scope of the invention shall be determined by the claims.