CN113014263A - Successive approximation ADC (analog to digital converter) capacitor array and switch logic circuit - Google Patents

the DAC array comprises 2ⁿ⁺¹A unit capacitor having positive and negative differential input terminals each provided with 2ⁿUnit capacitance, n is the number of bits of ADC; each step of quantization process control corresponds to 4 unit capacitors, the unit capacitors corresponding to each step of quantization process control are not repeated, and the capacitor weight correspondingly controlled in the jth step of quantization is

And

Furthermore, the output quantization result of the SAR logic circuit is connected to the grid of a lower plate switch of the DAC array, and the lower plate level of the capacitor array at the same phase end of the first comparator and the third comparator is subjected to D of the output quantization result<i>Controlling the output quantization result of the lower plate level of the capacitor array at the inverting terminal

And controlling to generate new three threshold values to continuously quantize the signal.

the invention provides a capacitor array and a switch logic circuit of a 2 b/cycle-oriented Successive Approximation-Register (SAR) Analog-to-Digital Converter (ADC). The circuit respectively generates three different thresholds during each step of quantization through two groups of Digital-to-Analog (DAC) arrays and three comparators, so that the function of outputting 2-bit data in each step is realized. Meanwhile, the invention also realizes extremely simple switch controlThe logic scheme is that the capacitor array is switched by the output of the circuit rear-end part SAR logic circuit, namely the quantization result D of each step<i>Or after it has passed through an inverter

To direct control so that the corresponding threshold value for the next quantization step can be generated.

The DAC array comprises 2ⁿ⁺¹A unit capacitor having positive and negative differential input terminals each provided with 2ⁿUnit capacitance, n is the number of bits of ADC; each step of quantization process control corresponds to 4 unit capacitors, the unit capacitors corresponding to each step of quantization process control are not repeated, and the capacitor weight correspondingly controlled in the jth step of quantization is

And

For an n-bit ADC, 2 for each of the positive and negative differential inputsⁿA total of 2 for each unit capacitor, ADCⁿ⁺¹Unit capacitance, scheme requirement of adopting 2b/cycle

Step quantization operation, the number of the capacitors controlled in each step is 4, the weight of the four capacitors is 4: 3: 1, wherein the weight of the capacitor controlled correspondingly in the

1 quantization is

The 2 nd step quantizes the corresponding controlled capacitance weight as

By analogy with that

The step quantization corresponds to the controlled capacitance weight of 4 multiplied by 4⁰，4×4⁰，3×4⁰，1×4⁰. The circuit adopts a lower polar plate sampling mode, the lower polar plate of the capacitor is connected with an input signal for sampling before quantization of each step, and the upper polar plate of the capacitor is connected with the input end of the comparator and is in short circuit with the common-mode voltage V at the moment_CMThe upper polar plate is disconnected with the V when the sampling is finished_CMThe connection of the lower plates and the disconnection of the lower plates of the two plates and the input signal are changed into connection with a preset fixed voltage, threshold reset operation required by the first step of comparison is generated while the charge of the lower plates is transferred to the upper plates, and the comparator starts to work after the DAC is established to carry out 2-bit data quantization of the first step. The split capacitor method can also be generalized to 3bit/cycle or higher quantization modes, e.g. when used in M bit/cycle, requiring 2 bits in total^M1 comparator with high order capacitance split ratio of (2)^MSimilar functions can be realized by 1 to 1.

Wherein, due to the weight distribution of 4: 3: 1, and assuming Vref ═ Vrefp-Vrefn, in the first placeThe voltage at the non-inverting terminal of CMP1 at the beginning of the step comparison is

The voltage value of the inverting terminal is

The value compared by CMP1 is therefore V_ip-V_inWhether the +1/2Vref is greater than 0, the equivalent threshold is-1/2 Vref, and the equivalent thresholds of the same CMP2 and CMP3 are 0 and 1/2Vref, so that V can be judged according to the results respectively output by the three comparators_ip-V_inThe 2-bit data of the first step is obtained at the position between the three thresholds; the low 4-bit capacitor is connected with V in the sampling phase_inAnd the reset phase is connected with Vrefp or Vrefn according to the ratio of 3: 1 so as to construct the total capacitance of integral power of 2 and form the corresponding threshold voltage of the comparator. In the conversion process until the last step, three of four Cu capacitors at the lowest bits in DAC at two ends of the comparator are connected with Vrefp, and one capacitor is connected with Vrefn. The lowest order capacitance can have many equivalent connections. For example, two of them are connected to Vrefp and the other two are connected to a common mode voltage. Connecting two differential capacitors to the same Vrefp or Vrefn can realize differential zero level by equivalent common mode voltage connection.

And after the quantization result is output in the first step, the control of the reset signal on the four capacitors in the step is turned off, the voltage of the lower electrode plate of the capacitor in the step is controlled by the SAR logic output signal, and a new threshold value is generated. Wherein the output quantization result of SAR logic is connected to the gate of the switch of the lower plate of DAC capacitor array, and the lower plate level of the capacitor array at the same phase terminal of CMP1 and CMP3 is subject to D of the output quantization result<i>Controlling the output quantization result of the lower plate level of the capacitor array at the inverting terminal

Controlling, and then generating new three thresholds according to the same principle to continuously quantize the signal; the significance of the method is that the outputs of the three comparators directly control the corresponding capacitor polesThe plate switch simplifies a logic circuit and further improves the quantization speed.

FIG. 1 is a schematic diagram of an n-bit capacitor array dedicated to this embodiment, and the circuit is composed of two sets of DAC array DAC1, DAC2, and three comparators CMP3, CMP2, and CMP1, which can generate D respectively₃<i>、D₂<i>、D₁<i>The three bits of quantization result are used to control the gate of the capacitor bottom plate switch. n-bit SAR ADC sharing a need

And step quantization operation, wherein each step of quantized controlled capacitors has four capacitors, and each step of capacitors are rearranged into a weight ratio of 4: 3: 1 by a capacitor division method. In addition, the circuit adopts a bottom plate sampling mode, and the bottom plate of the capacitor is connected with the input signal V before the quantization of each step is started_inAnd V_ipThe connection is sampled, and the capacitor upper polar plate is connected with the input end of the comparator and is short-circuited to the common mode level V_CMThe upper polar plate is disconnected with the V when the sampling is finished_CMWhile disconnecting their bottom plates from the input signal, to effect bottom plate charge transfer, so that the comparator's in-phase terminal voltage is V_CM-V_inAt a voltage of V at the reverse terminal_CM-V_ip. After the sampling phase, the DAC capacitor array is reset, as shown in fig. 2, before the first step of quantization starts, the capacitor array needs to be reset by preset fixed levels Vrefp and Vrefn, the capacitors at the same phase end of CMP3 are all connected to fixed levels of Vrefn, Vrefp, and Vrefn, and the capacitors at the opposite phase end are connected to fixed levels of Vrefp, Vrefn, and Vrefp; similarly, the lower plates of the same-phase-end step capacitors of CMP1 are connected to Vrefp, Vrefn, and Vrefp, respectively, and the lower plates of the counter-phase-end step capacitors thereof are connected to Vrefn, Vrefp, and Vrefn, respectively, assuming that Vref is Vrefp-Vrefn, the same-phase voltage of CMP1 at the time of the first comparison is equal to Vrefp-Vrefn

At a reverse terminal voltage of

The value compared by CMP1 is therefore V_ip-V_inWhether + Vref/2 is greater than 0, the equivalent threshold is-Vref/2, and the equivalent thresholds of CMP2 and CMP3 are 0 and Vref/2, respectively, so that V can be determined according to the results output by the three comparators respectively_ip-V_inAnd (4) falling at the position between the three thresholds to obtain the 2-bit data of the first step. After the reset phase is finished, the SAR ADC starts each step of conversion, as shown in FIG. 3, in the first step, three bits of quantized output signals D obtained by three comparators are obtained₃<1>D₂<1>D₁<1>The grid of the lower electrode plate switch of the capacitor array at the same phase end of CMP3 and CMP1 is controlled, and further the access signal of the lower electrode plate of the capacitor is controlled to be Vrefp or Vrefn; the gate of the lower plate switch of the capacitor array at the inverting terminal of CMP3 and CMP1 is not of the quantized output signal

And (5) controlling.

As shown in FIG. 4, the lower plate of the 8-bit capacitor array has been connected to a predetermined fixed voltage. When the reference level Vrefp is represented by 1 and Vrefn is represented by 0, the preset fixed voltages accessed by the capacitors at each step of the non-inverting terminal of CMP3 are 0, 1, and 0, and the preset fixed voltages accessed by the capacitors at each step of the inverting terminal of CMP3 are 1, 0, and 1, and similarly, the preset fixed voltage access of CMP1 is shown in fig. 4. Due to the weight distribution of the capacitors 4: 3: 1, and assuming Vref ═ Vrefp-Vrefn, the voltage at the non-inverting terminal of CMP3 at the beginning of the first comparison step is V_CM-V_in+64/256 × Vrefp +192/256 × Vrefn, and the voltage value at the inverting terminal is V_CM-V_ip+192/256 × Vrefp +64/256 × Vrefn, so the value compared by CMP3 is V_ip-V_inWhether-1/2 XVref is greater than 0, the equivalent threshold is 1/2 XVref, the equivalent thresholds of CMP2 and CMP1 are 0 and-1/2 Vref, and V is determined according to three

1/2 XVref, 0 and-1/2 XVref respectively generated by CMP3, CMP2 and CMP1_ip-V_inAt a position falling between the above three thresholds, obtaining a quantized output result, and using D₃<i>D₂<i>D₁<i>To indicate. A total of four quantization results are produced, namely: 111. 011, 001, 000, wherein 011 represents V_ip-V_inFalling within the interval of 0 to 1/2 × Vref, the other quantization results are treated similarly, and the 2-bit data of the first step is obtained.

Fig. 5 is a specific quantization process of this embodiment, assuming that the sampled input signal is +201/256 × Vref, the circuit is reset to obtain the threshold required for the first step of comparison, and according to the three thresholds-1/2 × Vref, 0, 1/2 × Vref generated before the first step of quantization, it can be seen that the input signal falls between 1/2 × Vref and Vref, and the output quantization results obtained by the SAR logic circuit at the rear end of the circuit are 1, and 1, respectively denoted as D₃<1>、D₂<1>、D₁<1>The quantization result is used to control the four capacitors of the first step of the capacitor array of FIG. 4, and the quantization result D is used to control the four capacitors of the capacitor array of FIG. 4_i<1>(i-1, 2, 3) or after passing through an inverter

The voltage of the lower plate of the capacitor at the same phase end of CMP3 is switched from a preset fixed voltage 0010 to 0000, the voltage of the lower plate of the capacitor at the opposite phase end of CMP3 is switched from a preset fixed voltage 1101 to 1111, the process changes the threshold used for the first comparison step, and accordingly the threshold voltage required for the second comparison step is generated, for example, the voltage value at the same phase end of CMP3 is switched from V to V, and the voltage of the lower plate of the capacitor at the two phase ends of CMP3 and CMP1 is kept unchanged_CM-V_in+64/256 XVrefp +192/256 XVrefn to V_CM-V_in+16/256 × Vrefp +240/256 × Vrefn, the voltage value of the inverting terminal is from V_CM-V_ip+192/256 XVrefp +64/256 XVrefn to V_CM-V_ip+240/256 × Vrefp +16/256 × Vrefn, so the value compared by CMP3 is V_ip-V_in-224/256 XVref is greater than 0, the equivalent threshold is 224/256 XVref, the equivalent thresholds for CMP2 and CMP1 are 192/256 XVref and 160/256 XVref, which result in the threshold needed for the second comparison step, with the first one described aboveThe same step comparison process can be carried out, the quantization result is 011 through the SAR logic circuit, and is marked as D₃<2>D₂<2>D₁<2>(ii) a As shown in fig. 4, the quantization result or the quantization result is not connected to the gates of the second-step capacitor bottom plate switches of CMP1 and CMP3, the level of the connected second-step capacitor bottom plate at the same phase end of CMP3 is changed from 0010 to 0011, the level of the connected second-step capacitor bottom plate at the opposite phase end is changed from 0010 to 1100, the equivalent threshold generated by CMP3 is 216/256 × Vref, the equivalent thresholds generated by CMP2 and CMP1 are 208/256 × Vref and 200/256 × Vref, the positions between the three equivalent thresholds where the input signal falls are observed, the quantization result finally output by the SAR logic circuit is 001, and the result is marked as D₃<3>D₂<3>D₁<3>Repeating the above operations to obtain a value close to the input signal, and completing the ADC conversion.