CN113434331B - Cross-frame code management method, memory storage device and memory control circuit - Google Patents

The invention provides a cross-frame coding management method, a memory storage device and a memory control circuit unit. The method comprises the following steps: reading tag replacement information corresponding to the first entity group; encoding first data; storing a first portion of the encoded first data to at least one first entity unit in the first entity group corresponding to the first tag information; and storing the second part of the encoded first data to at least one second entity unit corresponding to the second tag information in the first entity group according to the tag replacement information. The first tag information corresponds to a first cross-frame encoding group. The second tag information corresponds to a second cross-frame coding group. The first cross-frame coding group is different from the second cross-frame coding group. Therefore, the use efficiency of the rewritable nonvolatile memory module can be improved.

跨框编码管理方法、存储器存储装置及存储器控制电路Cross-frame encoding management method, memory storage device and memory control circuit

技术领域technical field

本发明涉及一种存储器内部的群组编码管理技术，且尤其涉及一种跨框编码管理方法、存储器存储装置及存储器控制电路单元。The invention relates to a group coding management technology inside a memory, and in particular to a cross-frame coding management method, a memory storage device and a memory control circuit unit.

背景技术Background technique

移动电话与笔记本计算机等可携式电子装置在这几年来的成长十分迅速，使得消费者对存储媒体的需求也急速增加。由于可复写式非易失性存储器模块(rewritable non-volatile memory module)(例如，快闪存储器)具有数据非易失性、省电、体积小，以及无机械结构等特性，所以非常适合内建于上述所举例的各种可携式电子装置中。Portable electronic devices such as mobile phones and notebook computers have grown rapidly in recent years, and consumers' demand for storage media has also increased rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built into various portable electronic devices mentioned above.

在独立磁碟冗余阵列(Redundant Array of Independent Disks,RAID)错误更正码(Error Correction Code,ECC)架构下，存入可复写式非易失性存储器模块的多个实体程序化单元(例如实体页)的数据可被编码，以产生可同时保护多个实体程序化单元中的数据的奇偶(parity)数据(亦称为全域(global)奇偶数据)。在解码数据时，此全域奇偶数据可利用多个实体程序化单元中的数据位元彼此间的逻辑关系来执行跨实体程序化单元的错误检测和/或更正。Under the redundant array of independent disks (Redundant Array of Independent Disks, RAID) error correction code (Error Correction Code, ECC) architecture, data stored in multiple physical programming units (such as physical pages) of the rewritable non-volatile memory module can be encoded to generate parity data (also called global parity data) that can simultaneously protect data in multiple physical programming units. When decoding data, the global parity data can utilize the logical relationship between data bits in multiple physical programming units to perform error detection and/or correction across physical programming units.

然而，在包含可复写式非易失性存储器模块的存储器存储装置出厂时，可复写式非易失性存储器模块中可被同步编码的多个实体程序化单元是固定的并且可被赋予同一个标签(亦称为编码标签)。当存储数据时，对应于同一个标签的实体程序化单元中的数据可被同步编码以产生对应的全域奇偶数据。但是，随着可复写式非易失性存储器模块的损耗增加(例如P/E周期增加)，一旦被赋予相同标签的多个实体程序化单元中同时出现多个位元错误率(Bit Error Rate,BER)较高的实体程序化单元，往后从这几个实体程序化单元读取的数据可能就无法被成功解码。However, when the memory storage device including the rewritable nonvolatile memory module leaves the factory, the multiple physical programming units that can be encoded synchronously in the rewritable nonvolatile memory module are fixed and can be given the same label (also called encoding label). When storing data, the data in the physical programming unit corresponding to the same tag can be encoded synchronously to generate corresponding global parity data. However, as the loss of the rewritable non-volatile memory module increases (for example, the P/E cycle increases), once multiple physical programming units with a higher bit error rate (Bit Error Rate, BER) appear in multiple physical programming units assigned the same tag at the same time, the data read from these physical programming units may not be successfully decoded.

发明内容Contents of the invention

本发明提供一种跨框编码管理方法、存储器存储装置及存储器控制电路单元，可动态管理可复写式非易失性存储器模块中对数据的群组编码配置，从而提高可复写式非易失性存储器模块的使用效率。The present invention provides a cross-frame encoding management method, a memory storage device and a memory control circuit unit, which can dynamically manage the group encoding configuration of data in a rewritable nonvolatile memory module, thereby improving the use efficiency of the rewritable nonvolatile memory module.

本发明的范例实施例提供一种跨框编码管理方法，其用于可复写式非易失性存储器模块。所述可复写式非易失性存储器模块包括多个实体群组。所述多个实体群组中的每一个实体群组包括多个实体单元。所述跨框编码管理方法包括：读取对应于所述多个实体群组中的第一实体群组的标签置换信息；编码第一数据；将经编码的所述第一数据的第一部分数据存储至所述第一实体群组中对应于第一标签信息的至少一第一实体单元；以及根据所述标签置换信息将经编码的所述第一数据的第二部分数据存储至所述第一实体群组中对应于第二标签信息的至少一第二实体单元。所述第一标签信息对应于第一跨框编码群组。所述第二标签信息对应于第二跨框编码群组。所述第一跨框编码群组不同于所述第二跨框编码群组。An exemplary embodiment of the present invention provides a cross-frame encoding management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of entity groups. Each entity group of the plurality of entity groups includes a plurality of entity units. The cross-frame encoding management method includes: reading label replacement information corresponding to a first entity group in the plurality of entity groups; encoding first data; storing the encoded first part of the first data in at least one first entity unit corresponding to the first label information in the first entity group; and storing the encoded second part of the first data in at least one second entity unit corresponding to the second label information in the first entity group according to the label replacement information. The first tag information corresponds to a first cross-frame encoding group. The second label information corresponds to a second cross-frame coding group. The first frame-crossing coding group is different from the second frame-crossing coding group.

在本发明的一范例实施例中，所述的跨框编码管理方法还包括：为所述第一实体群组中的每一实体单元配置标签信息，其中所述标签信息反映所述每一实体单元所属的跨框编码群组。In an exemplary embodiment of the present invention, the cross-frame coding management method further includes: configuring label information for each physical unit in the first physical group, wherein the label information reflects the cross-frame coding group to which each physical unit belongs.

在本发明的一范例实施例中，所述的跨框编码管理方法还包括：根据所述第一数据的编码结果产生奇偶数据。所述奇偶数据用以保护存储于所述至少一第一实体单元的所述第一数据的所述第一部分数据以及存储于所述至少一第二实体单元的所述第一数据的所述第二部分数据。In an exemplary embodiment of the present invention, the cross-frame coding management method further includes: generating parity data according to the coding result of the first data. The parity data is used to protect the first part of the first data stored in the at least one first physical unit and the second part of the first data stored in the at least one second physical unit.

在本发明的一范例实施例中，根据所述标签置换信息将经编码的所述第一数据的所述第二部分数据存储至所述第一实体群组中对应于所述第二标签信息的所述至少一第二实体单元的步骤包括：根据所述标签置换信息将所述至少一第二实体单元所对应的所述第二标签信息与所述第一实体群组中的至少一第三实体单元所对应的所述第一标签信息对调；以及根据标签对调结果将所述第二部分数据存储至所述至少一第二实体单元。In an exemplary embodiment of the present invention, the step of storing the encoded second part of the first data into the at least one second entity unit corresponding to the second label information in the first entity group according to the label replacement information includes: swapping the second label information corresponding to the at least one second entity unit with the first label information corresponding to at least one third entity unit in the first entity group according to the label substitution information; and storing the second part of data in the at least one second entity unit according to a label swap result.

在本发明的一范例实施例中，根据所述标签置换信息将经编码的所述第一数据的所述第二部分数据存储至所述第一实体群组中对应于所述第二标签信息的所述至少一第二实体单元的步骤包括：将经编码的所述第一数据的所述第二部分数据存储至所述至少一第二实体单元中的数据区；以及将所述标签置换信息存储至所述至少一第二实体单元中的闲置区。In an exemplary embodiment of the present invention, the step of storing the encoded second partial data of the first data in the at least one second physical unit corresponding to the second label information in the first entity group according to the label replacement information includes: storing the encoded second partial data of the first data in a data area in the at least one second physical unit; and storing the label replacement information in a spare area in the at least one second physical unit.

在本发明的一范例实施例中，所述的跨框编码管理方法还包括：在读取对应于所述第一实体群组的所述标签置换信息之前，从所述第一实体群组中读取第二数据；根据所述第二数据的位元错误状况存储所述标签置换信息；将所述第二数据搬移到所述多个实体群组中的第二实体群组进行存储；以及抹除所述第一实体群组。In an exemplary embodiment of the present invention, the cross-frame encoding management method further includes: before reading the tag replacement information corresponding to the first entity group, reading second data from the first entity group; storing the tag replacement information according to a bit error status of the second data; moving the second data to a second entity group among the plurality of entity groups for storage; and erasing the first entity group.

在本发明的一范例实施例中，根据所述第二数据的所述位元错误状况存储所述标签置换信息的步骤包括：响应于从所述第一实体群组中的至少一第三实体单元读取的数据的位元错误率高于预设值，存储对应于所述至少一第三实体单元的所述标签置换信息。In an exemplary embodiment of the present invention, the step of storing the tag replacement information according to the bit error status of the second data includes: storing the tag replacement information corresponding to the at least one third physical unit in response to a bit error rate of data read from at least one third physical unit in the first physical group being higher than a preset value.

本发明的范例实施例另提供一种存储器存储装置，其包括连接接口单元、可复写式非易失性存储器模块及存储器控制电路单元。所述连接接口单元用以连接至主机系统。所述可复写式非易失性存储器模块包括多个实体群组。所述多个实体群组中的每一个实体群组包括多个实体单元。所述存储器控制电路单元连接至所述连接接口单元与所述可复写式非易失性存储器模块。所述存储器控制电路单元用以读取对应于所述多个实体群组中的第一实体群组的标签置换信息。所述存储器控制电路单元还用以编码第一数据。所述存储器控制电路单元还用以将经编码的所述第一数据的第一部分数据存储至所述第一实体群组中对应于第一标签信息的至少一第一实体单元。所述存储器控制电路单元还用以根据所述标签置换信息将经编码的所述第一数据的第二部分数据存储至所述第一实体群组中对应于第二标签信息的至少一第二实体单元。所述第一标签信息对应于第一跨框编码群组。所述第二标签信息对应于第二跨框编码群组。所述第一跨框编码群组不同于所述第二跨框编码群组。An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable non-volatile memory module includes a plurality of entity groups. Each entity group of the plurality of entity groups includes a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used for reading tag replacement information corresponding to a first entity group in the plurality of entity groups. The memory control circuit unit is also used for encoding first data. The memory control circuit unit is further configured to store the encoded first part of the first data in at least one first entity unit corresponding to the first tag information in the first entity group. The memory control circuit unit is further configured to store the encoded second part of the first data into at least one second entity unit corresponding to the second label information in the first entity group according to the label replacement information. The first tag information corresponds to a first cross-frame encoding group. The second label information corresponds to a second cross-frame encoding group. The first frame-crossing coding group is different from the second frame-crossing coding group.

在本发明的一范例实施例中，所述存储器控制电路单元还用以为所述第一实体群组中的每一实体单元配置标签信息，其中所述标签信息反映所述每一实体单元所属的跨框编码群组。In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to configure label information for each physical unit in the first physical group, wherein the label information reflects the cross-frame coding group to which each physical unit belongs.

在本发明的一范例实施例中，所述存储器控制电路单元还用以根据所述第一数据的编码结果产生奇偶数据。所述奇偶数据用以保护存储于所述至少一第一实体单元的所述第一数据的所述第一部分数据以及存储于所述至少一第二实体单元的所述第一数据的所述第二部分数据。In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to generate parity data according to an encoding result of the first data. The parity data is used to protect the first part of the first data stored in the at least one first physical unit and the second part of the first data stored in the at least one second physical unit.

在本发明的一范例实施例中，所述存储器控制电路单元还用以：在读取对应于所述第一实体群组的所述标签置换信息之前，从所述第一实体群组中读取第二数据；根据所述第二数据的位元错误状况存储所述标签置换信息；将所述第二数据搬移到所述多个实体群组中的第二实体群组进行存储；以及抹除所述第一实体群组。In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: read second data from the first physical group before reading the tag replacement information corresponding to the first physical group; store the tag replacement information according to a bit error condition of the second data; move the second data to a second physical group of the plurality of physical groups for storage; and erase the first physical group.

本发明的范例实施例另提供一种存储器控制电路单元，其用于控制可复写式非易失性存储器模块。所述可复写式非易失性存储器模块包括多个实体群组。所述多个实体群组中的每一个实体群组包括多个实体单元。所述存储器控制电路单元包括主机接口、存储器接口、错误检查与校正电路及存储器管理电路。所述主机接口用以连接至主机系统。所述存储器接口用以连接至所述可复写式非易失性存储器模块。所述存储器管理电路连接至所述主机接口、所述存储器接口及所述错误检查与校正电路。所述存储器管理电路用以读取对应于所述多个实体群组中的第一实体群组的标签置换信息。所述错误检查与校正电路用以编码第一数据。所述存储器管理电路还用以将经编码的所述第一数据的第一部分数据存储至所述第一实体群组中对应于第一标签信息的至少一第一实体单元。所述存储器管理电路还用以根据所述标签置换信息将经编码的所述第一数据的第二部分数据存储至所述第一实体群组中对应于第二标签信息的至少一第二实体单元。所述第一标签信息对应于第一跨框编码群组。所述第二标签信息对应于第二跨框编码群组。所述第一跨框编码群组不同于所述第二跨框编码群组。An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of entity groups. Each entity group of the plurality of entity groups includes a plurality of entity units. The memory control circuit unit includes a host interface, a memory interface, an error checking and correction circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface and the error checking and correction circuit. The memory management circuit is used for reading tag replacement information corresponding to a first entity group in the plurality of entity groups. The error checking and correcting circuit is used for encoding first data. The memory management circuit is further configured to store the encoded first part of the first data in at least one first entity unit corresponding to the first tag information in the first entity group. The memory management circuit is further configured to store the encoded second part of the first data in at least one second entity unit corresponding to the second label information in the first entity group according to the label replacement information. The first tag information corresponds to a first cross-frame encoding group. The second label information corresponds to a second cross-frame encoding group. The first frame-crossing coding group is different from the second frame-crossing coding group.

在本发明的一范例实施例中，所述存储器管理电路还用以为所述第一实体群组中的每一实体单元配置标签信息。所述标签信息反映所述每一实体单元所属的跨框编码群组。In an exemplary embodiment of the present invention, the memory management circuit is further configured to configure tag information for each physical unit in the first physical group. The label information reflects the cross-frame coding group to which each entity unit belongs.

在本发明的一范例实施例中，所述错误检查与校正电路还用以根据所述第一数据的编码结果产生奇偶数据。所述奇偶数据用以保护存储于所述至少一第一实体单元的所述第一数据的所述第一部分数据以及存储于所述至少一第二实体单元的所述第一数据的所述第二部分数据。In an exemplary embodiment of the present invention, the error checking and correcting circuit is further configured to generate parity data according to an encoding result of the first data. The parity data is used to protect the first part of the first data stored in the at least one first physical unit and the second part of the first data stored in the at least one second physical unit.

在本发明的一范例实施例中，根据所述标签置换信息将经编码的所述第一数据的所述第二部分数据存储至所述第一实体群组中对应于所述第二标签信息的所述至少一第二实体单元的操作包括：根据所述标签置换信息将所述至少一第二实体单元所对应的所述第二标签信息与所述第一实体群组中的至少一第三实体单元所对应的所述第一标签信息对调；以及根据标签对调结果将所述第二部分数据存储至所述至少一第二实体单元。In an exemplary embodiment of the present invention, the operation of storing the encoded second part of the first data to the at least one second entity unit corresponding to the second label information in the first entity group according to the label replacement information includes: swapping the second label information corresponding to the at least one second entity unit with the first label information corresponding to at least one third entity unit in the first entity group according to the label substitution information; and storing the second part of data in the at least one second entity unit according to a label swap result.

在本发明的一范例实施例中，所述至少一第二实体单元的位元错误率低于所述至少一第三实体单元的位元错误率。In an exemplary embodiment of the present invention, the bit error rate of the at least one second physical unit is lower than the bit error rate of the at least one third physical unit.

在本发明的一范例实施例中，根据所述标签置换信息将经编码的所述第一数据的所述第二部分数据存储至所述第一实体群组中对应于所述第二标签信息的所述至少一第二实体单元的操作包括：将经编码的所述第一数据的所述第二部分数据存储至所述至少一第二实体单元中的数据区；以及将所述标签置换信息存储至所述至少一第二实体单元中的闲置区。In an exemplary embodiment of the present invention, the operation of storing the encoded second partial data of the first data in the at least one second physical unit corresponding to the second label information in the first entity group according to the label replacement information includes: storing the encoded second partial data of the first data in a data area in the at least one second physical unit; and storing the label replacement information in a spare area in the at least one second physical unit.

在本发明的一范例实施例中，所述存储器管理电路还用以：在读取对应于所述第一实体群组的所述标签置换信息之前，从所述第一实体群组中读取第二数据；根据所述第二数据的位元错误状况存储所述标签置换信息；将所述第二数据搬移到所述多个实体群组中的第二实体群组进行存储；以及抹除所述第一实体群组。In an exemplary embodiment of the present invention, the memory management circuit is further configured to: read second data from the first entity group before reading the tag replacement information corresponding to the first entity group; store the tag replacement information according to a bit error condition of the second data; move the second data to a second entity group among the plurality of entity groups for storage; and erase the first entity group.

在本发明的一范例实施例中，根据所述第二数据的所述位元错误状况存储所述标签置换信息的操作包括：响应于从所述第一实体群组中的至少一第三实体单元读取的数据的位元错误率高于预设值，存储对应于所述至少一第三实体单元的所述标签置换信息。In an exemplary embodiment of the present invention, the operation of storing the tag replacement information according to the bit error status of the second data includes: storing the tag replacement information corresponding to the at least one third physical unit in response to a bit error rate of data read from at least one third physical unit in the first physical group being higher than a preset value.

本发明的范例实施例另提供一种存储器存储装置，其包括连接接口单元、可复写式非易失性存储器模块及存储器控制电路单元。所述连接接口单元用以连接至主机系统。所述可复写式非易失性存储器模块包括多个实体群组。所述多个实体群组中的每一个实体群组包括多个实体单元。所述存储器控制电路单元连接至所述连接接口单元与所述可复写式非易失性存储器模块。所述存储器控制电路单元用以发送读取指令序列，其指示从所述多个实体群组中的第一实体群组读取第二数据。所述存储器控制电路单元还用以根据所述第二数据的位元错误状况调整所述第一实体群组的跨框编码群组的配置。所述跨框编码群组的配置反映所述第一实体群组中的多个实体单元属于同一个跨框编码群组。所述存储器控制电路单元还用以根据经调整的所述跨框编码群组的配置来存取所述第一实体群组。An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable non-volatile memory module includes a plurality of entity groups. Each entity group of the plurality of entity groups includes a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used for sending a read instruction sequence, which instructs to read second data from a first entity group in the plurality of entity groups. The memory control circuit unit is further configured to adjust the configuration of the cross-frame coding group of the first physical group according to the bit error status of the second data. The configuration of the cross-frame coding group reflects that multiple physical units in the first physical group belong to the same cross-frame coding group. The memory control circuit unit is further configured to access the first physical group according to the adjusted configuration of the cross-frame encoding group.

在本发明的一范例实施例中，根据所述第二数据的所述位元错误状况调整所述第一实体群组的所述跨框编码群组的配置的操作包括：响应于从所述第一实体群组中的至少一第三实体单元读取的数据的位元错误率高于预设值，调整所述第一实体群组的所述跨框编码群组的配置。In an exemplary embodiment of the present invention, the operation of adjusting the configuration of the cross-frame coding group of the first physical group according to the bit error condition of the second data includes: adjusting the configuration of the cross-frame coding group of the first physical group in response to a bit error rate of data read from at least one third physical unit in the first physical group being higher than a preset value.

在本发明的一范例实施例中，根据所述第二数据的所述位元错误状况调整所述第一实体群组的所述跨框编码群组的配置的操作包括：将所述第一实体群组中的一部分的实体单元所属的跨框编码群组与所述第一实体群组中的另一部分的实体单元所属的跨框编码群组对调，以改变所述第一实体群组的所述跨框编码群组的配置。In an exemplary embodiment of the present invention, the operation of adjusting the configuration of the cross-frame coding group of the first physical group according to the bit error status of the second data includes: swapping the cross-frame coding group to which a part of the physical units in the first physical group belongs to the cross-frame coding group to which another part of the physical units in the first physical group belongs, so as to change the configuration of the cross-frame coding group in the first physical group.

在本发明的一范例实施例中，将所述第一实体群组中的所述部分的实体单元所属的跨框编码群组与所述第一实体群组中的所述另一部分的实体单元所属的跨框编码群组对调的操作包括：将所述第一实体群组中的所述部分的实体单元所对应的标签信息与所述第一实体群组中的所述另一部分的实体单元所对应的标签信息对调。In an exemplary embodiment of the present invention, the operation of swapping the cross-frame coding group to which the part of the physical units in the first physical group belongs to the cross-frame coding group to which the other part of the physical units in the first physical group belongs includes: swapping label information corresponding to the part of the physical units in the first physical group with label information corresponding to the other part of the physical units in the first physical group.

本发明的一范例实施例中，根据经调整的所述跨框编码群组的配置来存取所述第一实体群组的操作包括：存储标签置换信息，其反映经调整的所述第一实体群组的所述跨框编码群组的配置；以及根据所述标签置换信息来存取所述第一实体群组。In an exemplary embodiment of the present invention, the operation of accessing the first entity group according to the adjusted configuration of the cross-frame coding group includes: storing tag replacement information reflecting the adjusted configuration of the cross-frame coding group of the first entity group; and accessing the first entity group according to the tag replacement information.

基于上述，在读取对应于第一实体群组的标签置换信息后，经编码的第一数据的第一部分数据可被存储至第一实体群组中对应于第一标签信息的第一实体单元。另一方面，经编码的第一数据的第二部分数据则可根据所述标签置换信息而被存储至第一实体群组中对应于第二标签信息的第二实体单元。第一标签信息对应于第一跨框编码群组。第二标签信息对应于第二跨框编码群组。第一跨框编码群组不同于第二跨框编码群组。通过动态管理可复写式非易失性存储器模块中对数据的群组编码配置，可提高可复写式非易失性存储器模块的使用效率。Based on the above, after reading the tag replacement information corresponding to the first entity group, the encoded first part of the first data may be stored in the first entity unit corresponding to the first tag information in the first entity group. On the other hand, the encoded second part of the first data may be stored in the second entity unit corresponding to the second label information in the first entity group according to the label replacement information. The first label information corresponds to the first cross-frame encoding group. The second label information corresponds to the second frame-crossing coding group. The first frame-spanning coding group is different from the second frame-spanning coding group. The use efficiency of the rewritable nonvolatile memory module can be improved by dynamically managing the group coding configuration of data in the rewritable nonvolatile memory module.

附图说明Description of drawings

图1是根据本发明的一范例实施例所示出的主机系统、存储器存储装置及输入/输出(I/O)装置的示意图；1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention;

图2是根据本发明的一范例实施例所示出的主机系统、存储器存储装置及I/O装置的示意图；2 is a schematic diagram of a host system, a memory storage device and an I/O device according to an exemplary embodiment of the present invention;

图3是根据本发明的一范例实施例所示出的主机系统与存储器存储装置的示意图；3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

图4是根据本发明的一范例实施例所示出的存储器存储装置的概要方块图；FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

图5是根据本发明的一范例实施例所示出的存储器控制电路单元的概要方块图；FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

图6是根据本发明的一范例实施例所示出的管理可复写式非易失性存储器模块的示意图；FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

图7是根据本发明的一范例实施例所示出的写入新数据的示意图；FIG. 7 is a schematic diagram of writing new data according to an exemplary embodiment of the present invention;

图8是根据本发明的一范例实施例所示出的实体群组的预设标签配置的示意图；Fig. 8 is a schematic diagram showing a default label configuration of an entity group according to an exemplary embodiment of the present invention;

图9是根据本发明的一范例实施例所示出的高位元错误率的实体单元的示意图；FIG. 9 is a schematic diagram of a physical unit with a high bit error rate according to an exemplary embodiment of the present invention;

图10是根据本发明的一范例实施例所示出的存储标签置换信息与搬移数据的示意图；Fig. 10 is a schematic diagram of storing tag replacement information and moving data according to an exemplary embodiment of the present invention;

图11是根据本发明的一范例实施例所示出的标签置换的示意图；Fig. 11 is a schematic diagram of label replacement according to an exemplary embodiment of the present invention;

图12是根据本发明的一范例实施例所示出的写入新数据的示意图；FIG. 12 is a schematic diagram of writing new data according to an exemplary embodiment of the present invention;

图13是根据本发明的一范例实施例所示出的根据调整后的标签配置存储数据的示意图；Fig. 13 is a schematic diagram of storing data according to an adjusted tag configuration according to an exemplary embodiment of the present invention;

图14是根据本发明的一范例实施例所示出的跨框编码管理方法的流程图；FIG. 14 is a flow chart of a method for managing cross-frame coding according to an exemplary embodiment of the present invention;

图15是根据本发明的一范例实施例所示出的跨框编码管理方法的流程图；FIG. 15 is a flow chart of a method for managing cross-frame coding according to an exemplary embodiment of the present invention;

图16是根据本发明的一范例实施例所示出的跨框编码管理方法的流程图；FIG. 16 is a flow chart of a method for managing cross-frame coding according to an exemplary embodiment of the present invention;

图17是根据本发明的一范例实施例所示出的跨框编码管理方法的流程图。Fig. 17 is a flowchart of a method for managing cross-frame coding according to an exemplary embodiment of the present invention.

具体实施方式Detailed ways

现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同元件符号在附图和描述中用来表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and description to refer to the same or like parts.

一般而言，存储器存储装置(亦称，存储器存储系统)包括可复写式非易失性存储器模块(rewritable non-volatile memory module)与控制器(亦称，控制电路)。存储器存储装置可与主机系统一起使用，以使主机系统可将数据写入至存储器存储装置或从存储器存储装置中读取数据。Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also called a control circuit). A memory storage device can be used with a host system such that the host system can write data to or read data from the memory storage device.

图1是根据本发明的一范例实施例所示出的主机系统、存储器存储装置及输入/输出(I/O)装置的示意图。图2是根据本发明的一范例实施例所示出的主机系统、存储器存储装置及I/O装置的示意图。FIG. 1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to an exemplary embodiment of the present invention.

请参照图1与图2，主机系统11可包括处理器111、随机存取存储器(random accessmemory,RAM)112、只读存储器(read only memory,ROM)113及数据传输接口114。处理器111、随机存取存储器112、只读存储器113及数据传输接口114可连接至系统总线(systembus)110。Referring to FIG. 1 and FIG. 2 , the host system 11 may include a processor 111 , a random access memory (random access memory, RAM) 112 , a read only memory (read only memory, ROM) 113 and a data transmission interface 114 . The processor 111 , random access memory 112 , ROM 113 and data transmission interface 114 can be connected to a system bus (systembus) 110 .

在一范例实施例中，主机系统11可通过数据传输接口114与存储器存储装置10连接。例如，主机系统11可通过数据传输接口114将数据存储至存储器存储装置10或从存储器存储装置10中读取数据。此外，主机系统11可通过系统总线110与I/O装置12连接。例如，主机系统11可通过系统总线110将输出信号传送至I/O装置12或从I/O装置12接收输入信号。In an exemplary embodiment, the host system 11 can be connected to the memory storage device 10 through the data transmission interface 114 . For example, the host system 11 can store data into the memory storage device 10 or read data from the memory storage device 10 through the data transmission interface 114 . In addition, the host system 11 can be connected to the I/O device 12 through the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O devices 12 via system bus 110 .

在一范例实施例中，处理器111、随机存取存储器112、只读存储器113及数据传输接口114可设置在主机系统11的主机板20上。数据传输接口114的数目可以是一或多个。通过数据传输接口114，主机板20可以通过有线或无线方式连接至存储器存储装置10。In an exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11 . The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114 , the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner.

在一范例实施例中，存储器存储装置10可例如是U盘201、存储卡202、固态硬盘(Solid State Drive,SSD)203或无线存储器存储装置204。无线存储器存储装置204可例如是近场通信(Near Field Communication,NFC)存储器存储装置、无线保真(WiFi)存储器存储装置、蓝牙(Bluetooth)存储器存储装置或低功耗蓝牙存储器存储装置(例如，iBeacon)等以各式无线通信技术为基础的存储器存储装置。此外，主机板20也可以通过系统总线110连接至全球定位系统(Global Positioning System,GPS)模块205、网络接口卡206、无线传输装置207、键盘208、屏幕209、喇叭210等各式I/O装置。例如，在一范例实施例中，主机板20可通过无线传输装置207存取无线存储器存储装置204。In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201 , a memory card 202 , a solid state drive (Solid State Drive, SSD) 203 or a wireless memory storage device 204 . The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a Wireless Fidelity (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy storage device (eg, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be connected to various I/O devices such as a Global Positioning System (GPS) module 205 , a network interface card 206 , a wireless transmission device 207 , a keyboard 208 , a screen 209 , and a speaker 210 through the system bus 110 . For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

在一范例实施例中，主机系统11为计算机系统。在一范例实施例中，主机系统11可为可实质地与存储器存储装置配合以存储数据的任意系统。In an exemplary embodiment, the host system 11 is a computer system. In an example embodiment, the host system 11 may be any system that can cooperate substantially with a memory storage device to store data.

图3是根据本发明的一范例实施例所示出的主机系统与存储器存储装置的示意图。请参照图3，在一范例实施例中，主机系统31可以是数码相机、摄像机、通信装置、音频播放器、视频播放器或平板计算机等系统。存储器存储装置30可为主机系统31所使用的安全数字(Secure Digital,SD)卡32、小型快闪(Compact Flash,CF)卡33或嵌入式存储装置34等各式非易失性存储器存储装置。嵌入式存储装置34包括嵌入式多媒体卡(embeddedMulti Media Card,eMMC)341和/或嵌入式多芯片封装(embedded Multi Chip Package,eMCP)存储装置342等各类型将存储器模块直接连接于主机系统的基板上的嵌入式存储装置。FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG. 3 , in an exemplary embodiment, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. The memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32 , a Compact Flash (CF) card 33 or an embedded storage device 34 used by the host system 31 . The embedded storage device 34 includes various types of embedded storage devices such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342, which directly connects the memory module to the substrate of the host system.

图4是根据本发明的一范例实施例所示出的存储器存储装置的概要方块图。请参照图4，存储器存储装置10包括连接接口单元402、存储器控制电路单元404与可复写式非易失性存储器模块406。FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

连接接口单元402用以将存储器存储装置10连接主机系统11。存储器存储装置10可通过连接接口单元402与主机系统11通信。在一范例实施例中，连接接口单元402是相容于高速周边零件连接接口(Peripheral Component Interconnect Express,PCI Express)标准。在一范例实施例中，连接接口单元402亦可以是相容于串行高级技术附件(SerialAdvanced Technology Attachment,SATA)标准、并行高级技术附件(Parallel AdvancedTechnology Attachment,PATA)标准、电气和电子工程师协会(Institute of Electricaland Electronic Engineers,IEEE)1394标准、通用串行总线(Universal Serial Bus,USB)标准、SD接口标准、超高速一代(Ultra High Speed-I,UHS-I)接口标准、超高速二代(UltraHigh Speed-II,UHS-II)接口标准、存储棒(Memory Stick,MS)接口标准、MCP接口标准、MMC接口标准、eMMC接口标准、通用快闪存储器(Universal Flash Storage,UFS)接口标准、eMCP接口标准、CF接口标准、整合式驱动电子接口(Integrated Device Electronics,IDE)标准或其他适合的标准。连接接口单元402可与存储器控制电路单元404封装在一个芯片中，或者连接接口单元402是布设于一包含存储器控制电路单元404的芯片外。The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11 . The memory storage device 10 can communicate with the host system 11 through the connection interface unit 402 . In an exemplary embodiment, the connection interface unit 402 is compatible with the high-speed peripheral component interconnect express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 402 may also be compatible with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (Parallel Advanced Technology Attachment, PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, the Universal Serial Bus (Universal Serial Bus) Bus, USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, integrated driver Electronic interface (Integrated Device Electronics, IDE) standard or other suitable standards. The connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404 .

存储器控制电路单元404连接至连接接口单元402与可复写式非易失性存储器模块406。存储器控制电路单元404用以执行以硬件型式或固件型式实作的多个逻辑门或控制指令并且根据主机系统11的指令在可复写式非易失性存储器模块406中进行数据的写入、读取与抹除等运作。The memory control circuit unit 404 is connected to the connection interface unit 402 and the rewritable non-volatile memory module 406 . The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11.

可复写式非易失性存储器模块406用以存储主机系统11所写入的数据。可复写式非易失性存储器模块406可包括单阶存储单元(Single Level Cell,SLC)NAND型快闪存储器模块(即，一个存储单元中可存储1个位元的快闪存储器模块)、二阶存储单元(MultiLevel Cell,MLC)NAND型快闪存储器模块(即，一个存储单元中可存储2个位元的快闪存储器模块)、三阶存储单元(Triple Level Cell,TLC)NAND型快闪存储器模块(即，一个存储单元中可存储3个位元的快闪存储器模块)、四阶存储单元(Quad Level Cell,QLC)NAND型快闪存储器模块(即，一个存储单元中可存储4个位元的快闪存储器模块)、其他快闪存储器模块或其他具有相同特性的存储器模块。The rewritable non-volatile memory module 406 is used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 may include a single-level storage unit (Single Level Cell, SLC) NAND flash memory module (that is, a flash memory module that can store 1 bit in a storage unit), a second-order storage unit (MultiLevel Cell, MLC) NAND flash memory module (that is, a storage unit that can store 2 bits of flash memory module), and a third-level storage unit (Triple Level Cell, TLC) NAND flash memory module. A memory module (that is, a flash memory module that can store 3 bits in a storage unit), a quad level cell (Quad Level Cell, QLC) NAND flash memory module (that is, a flash memory module that can store 4 bits in a storage unit), other flash memory modules, or other memory modules with the same characteristics.

可复写式非易失性存储器模块406中的每一个存储单元是以电压(以下亦称为临界电压)的改变来存储一或多个位元。具体来说，每一个存储单元的控制门(control gate)与通道之间有一个电荷捕捉层。通过施予一写入电压至控制门，可以改变电荷补捉层的电子量，进而改变存储单元的临界电压。此改变存储单元的临界电压的操作亦称为“把数据写入至存储单元”或“程序化(programming)存储单元”。随着临界电压的改变，可复写式非易失性存储器模块406中的每一个存储单元具有多个存储状态。通过施予读取电压可以判断一个存储单元是属于哪一个存储状态，藉此取得此存储单元所存储的一或多个位元。Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing a voltage (also referred to as threshold voltage hereinafter). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a writing voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. The operation of changing the threshold voltage of the memory cell is also called "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple storage states. Which storage state a memory cell belongs to can be determined by applying a read voltage, thereby obtaining one or more bits stored in the memory cell.

在一范例实施例中，可复写式非易失性存储器模块406的存储单元可构成多个实体程序化单元，并且此些实体程序化单元可构成多个实体抹除单元。具体来说，同一条字线上的存储单元可组成一或多个实体程序化单元。若每一个存储单元可存储2个以上的位元，则同一条字线上的实体程序化单元可至少可被分类为下实体程序化单元与上实体程序化单元。例如，一存储单元的最低有效位元(Least Significant Bit，LSB)是属于下实体程序化单元，并且一存储单元的最高有效位元(Most Significant Bit，MSB)是属于上实体程序化单元。一般来说，在MLC NAND型快闪存储器中，下实体程序化单元的写入速度会大于上实体程序化单元的写入速度，和/或下实体程序化单元的可靠度是高于上实体程序化单元的可靠度。In an exemplary embodiment, the storage units of the rewritable non-volatile memory module 406 can constitute a plurality of physical programming units, and these physical programming units can constitute a plurality of physical erasing units. Specifically, memory cells on the same word line can form one or more physical programming cells. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the Least Significant Bit (LSB) of a storage unit belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a storage unit belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is higher than that of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

在一范例实施例中，实体程序化单元为程序化的最小单元。即，实体程序化单元为写入数据的最小单元。例如，实体程序化单元可为实体页(page)或是实体扇(sector)。若实体程序化单元为实体页，则此些实体程序化单元可包括数据位元区与冗余(redundancy)位元区。数据位元区包含多个实体扇，用以存储使用者数据，而冗余位元区用以存储系统数据(例如，错误更正码等管理数据)。在一范例实施例中，数据位元区包含32个实体扇，且一个实体扇的大小为512字节(byte,B)。然而，在其他范例实施例中，数据位元区中也可包含8个、16个或数目更多或更少的实体扇，并且每一个实体扇的大小也可以是更大或更小。另一方面，实体抹除单元为抹除的最小单位。亦即，每一实体抹除单元含有最小数目的一并被抹除的存储单元。例如，实体抹除单元为实体区块(block)。In an exemplary embodiment, the entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming units are physical pages, these physical programming units may include data bit fields and redundancy (redundancy) bit fields. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains the minimum number of memory cells to be erased together. For example, the physical erasing unit is a physical block.

图5是根据本发明的一范例实施例所示出的存储器控制电路单元的概要方块图。请参照图5，存储器控制电路单元404包括存储器管理电路502、主机接口504、存储器接口506及错误检查与校正电路508。FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG. 5 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 , a memory interface 506 and an error checking and correction circuit 508 .

存储器管理电路502用以控制存储器控制电路单元404的整体运作。具体来说，存储器管理电路502具有多个控制指令，并且在存储器存储装置10运作时，此些控制指令会被执行以进行数据的写入、读取与抹除等运作。以下说明存储器管理电路502的操作时，等同于说明存储器控制电路单元404的操作。The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data. When describing the operation of the memory management circuit 502 below, it is equivalent to describing the operation of the memory control circuit unit 404 .

在一范例实施例中，存储器管理电路502的控制指令是以固件型式来实作。例如，存储器管理电路502具有微处理器单元(未示出)与只读存储器(未示出)，并且此些控制指令是被烧录至此只读存储器中。当存储器存储装置10运作时，此些控制指令会由微处理器单元来执行以进行数据的写入、读取与抹除等运作。In an exemplary embodiment, the control commands of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

在一范例实施例中，存储器管理电路502的控制指令亦可以程序码型式存储于可复写式非易失性存储器模块406的特定区域(例如，存储器模块中专用于存放系统数据的系统区)中。此外，存储器管理电路502具有微处理器单元(未示出)、只读存储器(未示出)及随机存取存储器(未示出)。特别是，此只读存储器具有开机码(boot code)，并且当存储器控制电路单元404被致能时，微处理器单元会先执行此开机码来将存储于可复写式非易失性存储器模块406中的控制指令载入至存储器管理电路502的随机存取存储器中。之后，微处理器单元会运转此些控制指令以进行数据的写入、读取与抹除等运作。In an exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in a specific area of the rewritable non-volatile memory module 406 (eg, a system area dedicated to storing system data in the memory module) in the form of program codes. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 406 into the random access memory of the memory management circuit 502. Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

在一范例实施例中，存储器管理电路502的控制指令亦可以一硬件型式来实作。例如，存储器管理电路502包括微控制器、存储单元管理电路、存储器写入电路、存储器读取电路、存储器抹除电路与数据处理电路。存储单元管理电路、存储器写入电路、存储器读取电路、存储器抹除电路与数据处理电路是连接至微控制器。存储单元管理电路用以管理可复写式非易失性存储器模块406的存储单元或存储单元群组。存储器写入电路用以对可复写式非易失性存储器模块406下达写入指令序列以将数据写入至可复写式非易失性存储器模块406中。存储器读取电路用以对可复写式非易失性存储器模块406下达读取指令序列以从可复写式非易失性存储器模块406中读取数据。存储器抹除电路用以对可复写式非易失性存储器模块406下达抹除指令序列以将数据从可复写式非易失性存储器模块406中抹除。数据处理电路用以处理欲写入至可复写式非易失性存储器模块406的数据以及从可复写式非易失性存储器模块406中读取的数据。写入指令序列、读取指令序列及抹除指令序列可各别包括一或多个程序码或指令码并且用以指示可复写式非易失性存储器模块406执行相对应的写入、读取及抹除等操作。在一范例实施例中，存储器管理电路502还可以下达其他类型的指令序列给可复写式非易失性存储器模块406以指示执行相对应的操作。In an exemplary embodiment, the control instructions of the memory management circuit 502 may also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The storage unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 406 . The memory writing circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406 . The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406 . The memory erasing circuit is used for issuing an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406 . The data processing circuit is used for processing data to be written into the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406 . The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 502 may also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

主机接口504是连接至存储器管理电路502。存储器管理电路502可通过主机接口504与主机系统11通信。主机接口504可用以接收与识别主机系统11所传送的指令与数据。例如，主机系统11所传送的指令与数据可通过主机接口504来传送至存储器管理电路502。此外，存储器管理电路502可通过主机接口504将数据传送至主机系统11。在本范例实施例中，主机接口504是相容于PCI Express标准。然而，必须了解的是本发明不限于此，主机接口504亦可以是相容于SATA标准、PATA标准、IEEE 1394标准、USB标准、SD标准、UHS-I标准、UHS-II标准、MS标准、MMC标准、eMMC标准、UFS标准、CF标准、IDE标准或其他适合的数据传输标准。The host interface 504 is connected to the memory management circuit 502 . Memory management circuitry 502 may communicate with host system 11 through host interface 504 . The host interface 504 can be used to receive and recognize commands and data transmitted by the host system 11 . For example, the commands and data transmitted by the host system 11 can be transmitted to the memory management circuit 502 through the host interface 504 . In addition, the memory management circuit 502 can transmit data to the host system 11 through the host interface 504 . In this exemplary embodiment, the host interface 504 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards or other suitable data transmission standards.

存储器接口506是连接至存储器管理电路502并且用以存取可复写式非易失性存储器模块406。也就是说，欲写入至可复写式非易失性存储器模块406的数据会通过存储器接口506转换为可复写式非易失性存储器模块406所能接受的格式。具体来说，若存储器管理电路502要存取可复写式非易失性存储器模块406，存储器接口506会传送对应的指令序列。例如，这些指令序列可包括指示写入数据的写入指令序列、指示读取数据的读取指令序列、指示抹除数据的抹除指令序列、以及用以指示各种存储器操作(例如，改变读取电压电平或执行垃圾回收操作等等)的相对应的指令序列。这些指令序列例如是由存储器管理电路502产生并且通过存储器接口506传送至可复写式非易失性存储器模块406。这些指令序列可包括一或多个信号，或是在总线上的数据。这些信号或数据可包括指令码或程序码。例如，在读取指令序列中，会包括读取的识别码、存储器地址等信息。The memory interface 506 is connected to the memory management circuit 502 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 through the memory interface 506 . Specifically, if the memory management circuit 502 wants to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit a corresponding instruction sequence. For example, these command sequences may include a write command sequence for writing data, a read command sequence for reading data, an erase command sequence for erasing data, and corresponding command sequences for instructing various memory operations (for example, changing a read voltage level or performing a garbage collection operation, etc.). These instruction sequences are, for example, generated by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506 . These command sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program codes. For example, in the read command sequence, information such as read identification code and memory address will be included.

错误检查与校正电路508是连接至存储器管理电路502并且用以执行错误检查与校正操作以确保数据的正确性。具体来说，当存储器管理电路502从主机系统11中接收到写入指令时，错误检查与校正电路508会为对应此写入指令的数据产生对应的错误更正码(error correcting code,ECC)和/或错误检查码(error detecting code，EDC)，并且存储器管理电路502会将对应此写入指令的数据与对应的错误更正码和/或错误检查码写入至可复写式非易失性存储器模块406中。之后，当存储器管理电路502从可复写式非易失性存储器模块406中读取数据时会同时读取此数据对应的错误更正码和/或错误检查码，并且错误检查与校正电路508会依据此错误更正码和/或错误检查码对所读取的数据执行错误检查与校正操作。The error checking and correction circuit 508 is connected to the memory management circuit 502 and configured to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 will generate a corresponding error correcting code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 502 will write the data corresponding to the write command and the corresponding error correction code and/or error check code into the rewritable non-volatile memory module 4 06 in. Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will simultaneously read the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 508 will perform error check and correction operations on the read data according to the error correction code and/or error check code.

在一范例实施例中，存储器控制电路单元404还包括缓冲存储器510与电源管理电路512。缓冲存储器510是连接至存储器管理电路502并且用以暂存来自于主机系统11的数据与指令或来自于可复写式非易失性存储器模块406的数据。电源管理电路512是连接至存储器管理电路502并且用以控制存储器存储装置10的电源。In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512 . The buffer memory 510 is connected to the memory management circuit 502 and used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . The power management circuit 512 is connected to the memory management circuit 502 and used to control the power of the memory storage device 10 .

在一范例实施例中，图4的存储器存储装置10亦称为快闪存储器存储装置，可复写式非易失性存储器模块406亦称为快闪存储器模块，且存储器控制电路单元404亦称为快闪存储器控制器。在一范例实施例中，图5的存储器管理电路502亦称为快闪存储器管理电路。In an exemplary embodiment, the memory storage device 10 of FIG. 4 is also called a flash memory storage device, the rewritable non-volatile memory module 406 is also called a flash memory module, and the memory control circuit unit 404 is also called a flash memory controller. In an exemplary embodiment, the memory management circuit 502 of FIG. 5 is also called a flash memory management circuit.

图6是根据本发明的一范例实施例所示出的管理可复写式非易失性存储器模块的示意图。请参照图6，存储器管理电路502可将可复写式非易失性存储器模块406中的实体单元610(0)～610(B)逻辑地分组至存储区(storage region)601与闲置(spare region)区602。在本范例实施例中，一个实体单元是指一个实体地址或一个实体程序化单元。在另一范例实施例中，一个实体单元亦可以是由多个连续或不连续的实体地址组成。FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6 , the memory management circuit 502 can logically group the physical units 610 ( 0 )˜ 610 (B) in the rewritable non-volatile memory module 406 into a storage region 601 and a spare region 602 . In this exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In another exemplary embodiment, a physical unit may also be composed of multiple continuous or discontinuous physical addresses.

存储区601中的实体单元610(0)～610(A)用以存储使用者数据(例如来自图1的主机系统11的使用者数据)。例如，存储区601中的实体单元610(0)～610(A)可存储有效(valid)数据与无效(invalid)数据。闲置区602中的实体单元610(A+1)～610(B)未存储数据(例如有效数据)。例如，若某一个实体单元未存储有效数据，则此实体单元可被关联(或加入)至闲置区602。此外，闲置区602中的实体单元(或未存储有效数据的实体单元)可被抹除。在写入新数据时，一个实体单元可被从闲置区602中提取以存储此新数据。在一范例实施例中，闲置区602亦称为闲置池(free pool)。The physical units 610( 0 )˜610(A) in the storage area 601 are used for storing user data (such as user data from the host system 11 in FIG. 1 ). For example, the physical units 610(0)˜610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)˜610(B) in the spare area 602 do not store data (eg valid data). For example, if a certain physical unit does not store valid data, this physical unit may be associated (or added) to the spare area 602 . In addition, physical units (or physical units that do not store valid data) in the spare area 602 can be erased. When new data is written, a physical unit can be extracted from spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also called a free pool.

存储器管理电路502可配置逻辑单元612(0)～612(C)以映射存储区601中的实体单元610(0)～610(A)。在一范例实施例中，每一个逻辑单元对应一个逻辑地址。例如，一个逻辑地址可包括一或多个逻辑区块地址(Logical Block Address,LBA)或其他的逻辑管理单元。在另一范例实施例中，一个逻辑单元也可对应一个逻辑程序化单元或者由多个连续或不连续的逻辑地址组成。此外，一个逻辑单元可被映射至一或多个实体单元。须注意的是，若某一实体单元当前有被某一逻辑单元映射，则表示此实体单元当前存储的数据为有效数据。反之，若某一实体单元当前未被任一逻辑单元映射，则表示此实体单元当前存储的数据为无效数据。The memory management circuit 502 can configure the logical units 612 ( 0 )˜ 612 (C) to map the physical units 610 ( 0 )˜ 610 (A) in the storage area 601 . In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBA) or other logical management units. In another exemplary embodiment, one logical unit may also correspond to one logical programming unit or consist of multiple consecutive or discontinuous logical addresses. Furthermore, a logical unit can be mapped to one or more physical units. It should be noted that if a physical unit is currently mapped by a logical unit, it means that the data currently stored in the physical unit is valid data. Conversely, if a certain physical unit is not currently mapped by any logical unit, it means that the data currently stored in this physical unit is invalid data.

存储器管理电路502可将描述逻辑单元与实体单元之间的映射关系的管理数据(亦称为逻辑至实体映射信息)记录于至少一逻辑至实体映射表。当主机系统11欲从存储器存储装置10读取数据或写入数据至存储器存储装置10时，存储器管理电路502可根据此逻辑至实体映射表来执行对于存储器存储装置10的数据存取操作。The memory management circuit 502 can record management data (also referred to as logical-to-physical mapping information) describing the mapping relationship between logical units and physical units in at least one logical-to-physical mapping table. When the host system 11 intends to read data from or write data to the memory storage device 10 , the memory management circuit 502 can perform a data access operation to the memory storage device 10 according to the logical-to-physical mapping table.

图7是根据本发明的一范例实施例所示出的写入新数据的示意图。请参照图7，在从主机系统11接收指示存储数据701的写入指令后，存储器管理电路502可指示编码电路71对数据701进行编码。然后，存储器管理电路502可指示可复写式非易失性存储器模块将经编码电路71编码的数据701存储至可复写式非易失性存储器模块406中的实体群组70(0)～70(D)的其中之一。实体群组70(0)～70(D)中的每一个实体群组可包含图6中的多个实体单元。在一范例实施例中，一或多个实体群组亦可形成一个虚拟区块。FIG. 7 is a schematic diagram of writing new data according to an exemplary embodiment of the present invention. Referring to FIG. 7 , after receiving a write command from the host system 11 indicating to store the data 701 , the memory management circuit 502 can instruct the encoding circuit 71 to encode the data 701 . Then, the memory management circuit 502 can instruct the rewritable nonvolatile memory module to store the data 701 encoded by the encoding circuit 71 into one of the entity groups 70 ( 0 )˜70 (D) in the rewritable nonvolatile memory module 406 . Each of the entity groups 70(0)˜70(D) may include a plurality of entity units in FIG. 6 . In an exemplary embodiment, one or more physical groups may also form a virtual block.

编码电路71可包含于错误检查与校正电路508中并可用以对数据701执行编码(与解码)。须注意的是，编码电路71可对数据701执行RAID ECC编码或类似的多框(亦称为跨框)编码(与解码)操作。例如，在RAID ECC编码或类似的多框编码操作中，数据701可被执行跨实体单元(例如跨实体程序化单元)的编码，以产生可用以同时保护多个实体单元(例如多个实体程序化单元)的奇偶数据(即全域奇偶数据)。例如，编码电路71可采用里德-所罗门码(Reed-solomon code,RS code)或异或(Exclusive OR,XOR)等编/解码演算法来进行数据的编码(与解码)。经编码电路71编码的数据701与通过对数据701进行编码而产生的全域奇偶数据可被存储至具有相同标签(亦称为编码标签)的多个实体单元中。尔后，当读取数据时，若所读取的数据701中存在错误，则编码电路71可从具有相同标签的多个实体单元中读取经编码的数据701以及相应的全域奇偶数据并使用此些数据对所读取的数据701进行解码，以尝试更正所读取的数据701中的错误。Encoding circuitry 71 may be included in error checking and correction circuitry 508 and may be used to perform encoding (and decoding) on data 701 . It should be noted that the encoding circuit 71 can perform RAID ECC encoding or similar multi-frame (also called cross-frame) encoding (and decoding) operations on the data 701 . For example, in RAID ECC encoding or similar multi-block encoding operations, the data 701 may be encoded across physical units (e.g., across physical programming units) to generate parity data (i.e., global parity data) that can be used to simultaneously protect multiple physical units (e.g., multiple physical programming units). For example, the encoding circuit 71 may use encoding/decoding algorithms such as Reed-Solomon code (RS code) or Exclusive OR (XOR) to encode (and decode) data. The data 701 encoded by the encoding circuit 71 and the global parity data generated by encoding the data 701 can be stored in a plurality of physical units with the same tag (also referred to as an encoding tag). Thereafter, when reading data, if there is an error in the read data 701, the encoding circuit 71 may read the encoded data 701 and the corresponding global parity data from multiple physical units with the same tag and use these data to decode the read data 701 in an attempt to correct the error in the read data 701.

图8是根据本发明的一范例实施例所示出的实体群组的标签配置的示意图。请参照图8，以实体群组70(0)～70(D)中的实体群组70(i)为例，存储器管理电路502可为实体群组70(i)中的每一个实体单元预先配置一个标签(亦称为初始标签)，例如，标签Tag_0～Tag_5的其中之一。例如，每一个实体单元所对应的标签可在存储器存储装置10或可复写式非易失性存储器模块406出厂前就预先存储于每一个实体单元中或系统管理表格中。所述标签可反映每一实体单元所属的跨框编码群组。在对数据执行RAID ECC编码或类似的多框编码操作后，经编码的数据以及相应的全域奇偶数据可被存储于具有相同标签的多个实体单元中。尔后，存储于具有相同标签的多个实体单元中的数据可共同用以解码其中的一或多个实体单元中的数据的错误。Fig. 8 is a schematic diagram showing a label configuration of an entity group according to an exemplary embodiment of the present invention. Referring to FIG. 8, taking the entity group 70(i) among the entity groups 70(0)-70(D) as an example, the memory management circuit 502 can pre-configure a tag (also called an initial tag) for each entity unit in the entity group 70(i), for example, one of the tags Tag_0-Tag_5. For example, the label corresponding to each physical unit may be pre-stored in each physical unit or in the system management table before the memory storage device 10 or the rewritable non-volatile memory module 406 leaves the factory. The labels may reflect the spanning coding group to which each physical unit belongs. After performing RAID ECC encoding or a similar multi-block encoding operation on the data, the encoded data and corresponding global parity data can be stored in multiple physical units with the same label. Then, the data stored in multiple physical units with the same tag can be used together to decode errors in the data in one or more of the physical units.

在一范例实施例中，一个特定的标签对应于一个特定的跨框编码群组。不同的标签对应于不同的跨框编码群组。以图7为例，经编码的数据701以及通过编码数据701而产生的全域奇偶数据可预设为存储于实体群组70(i)中对应于相同的标签Tag_0的实体单元810(0)～810(7)中。例如，经编码的数据701可分段存储于实体单元810(0)～810(6)中，且通过编码数据701而产生的全域奇偶数据则可存储于实体单元810(7)中。当后续需要从实体群组70(i)中读取数据701时，存储于实体单元810(0)～810(7)中的所有或至少部分数据可用于解码从实体单元810(0)～810(7)中的任一者读取的数据，从而尝试更正所读取的数据中的错误。依此类推，经编码的某一数据与相应的奇偶数据(即全域奇偶数据)可存储于对应于标签Tag_k的多个实体单元中，且k可为0～5中的任一整数。In an exemplary embodiment, a specific label corresponds to a specific spanning coding group. Different labels correspond to different groups of cross-box encodings. Taking FIG. 7 as an example, the encoded data 701 and the global parity data generated by encoding the data 701 can be preset to be stored in the entity units 810(0)-810(7) corresponding to the same tag Tag_0 in the entity group 70(i). For example, the encoded data 701 can be segmented and stored in the physical units 810(0)˜810(6), and the global parity data generated by encoding the data 701 can be stored in the physical unit 810(7). When the data 701 needs to be read from the physical group 70(i) subsequently, all or at least part of the data stored in the physical units 810(0)-810(7) can be used to decode the data read from any one of the physical units 810(0)-810(7), thereby attempting to correct errors in the read data. By analogy, certain coded data and corresponding parity data (ie global parity data) can be stored in a plurality of physical units corresponding to the tag Tag_k, and k can be any integer from 0 to 5.

在一范例实施例中，若实体群组70(i)中对应于标签Tag_k的多个实体单元中的数据中存在太多错误，则编码电路71可能无法顺利更正从对应于同一个标签Tag_k的某一实体单元中读取的数据中的所有错误。In an exemplary embodiment, if there are too many errors in the data in a plurality of physical units corresponding to the tag Tag_k in the physical group 70(i), the encoding circuit 71 may not be able to correct all errors in the data read from a certain physical unit corresponding to the same tag Tag_k smoothly.

在一范例实施例中，若实体群组70(i)中对应于标签Tag_k的多个实体单元中的数据中存在太多错误，则存储器管理电路502可更新、调整或改变实体群组70(i)的跨框编码群组的配置(例如将标签Tag_k所对应的某一个实体单元与标签Tag_p所对应的某一个实体单元对调，且k不等于p)，从而提高往后存储于实体群组70(i)中的数据可靠度。In an exemplary embodiment, if there are too many errors in the data in the multiple physical units corresponding to the tag Tag_k in the physical group 70(i), the memory management circuit 502 can update, adjust or change the configuration of the cross-frame encoding group of the physical group 70(i) (for example, swap a certain physical unit corresponding to the tag Tag_k with a certain physical unit corresponding to the tag Tag_p, and k is not equal to p), thereby improving the reliability of data stored in the physical group 70(i).

图9是根据本发明的一范例实施例所示出的高位元错误率的实体单元的示意图。请参照图9，以标签Tag_0为例，假设从对应于标签Tag_0的实体单元810(3)与810(5)中读取的数据中存在太多错误位元(图9中标记为HECC)，则后续从实体单元810(3)和/或810(5)中读取的数据中的错误可能无法被完全更正。在此状况下，若未动态调整对应于标签Tag_0的实体单元的分组配置，则可能导致往后从对应于标签Tag_0的实体单元读取的数据都无法被成功解码，甚至可能导致整个实体群组70(i)无法使用。FIG. 9 is a schematic diagram of a physical unit with a high bit error rate according to an exemplary embodiment of the present invention. Referring to FIG. 9, taking the tag Tag_0 as an example, assuming that there are too many error bits (marked as HECC in FIG. 9 ) in the data read from the physical units 810(3) and 810(5) corresponding to the tag Tag_0, errors in the subsequent data read from the physical units 810(3) and/or 810(5) may not be completely corrected. In this case, if the grouping configuration of the physical unit corresponding to the tag Tag_0 is not dynamically adjusted, the data read from the physical unit corresponding to the tag Tag_0 may not be successfully decoded, and may even cause the entire physical group 70(i) to be unusable.

图10是根据本发明的一范例实施例所示出的存储标签置换信息与搬移数据的示意图。请参照图10，在一范例实施例中，存储器管理电路502可从图7的实体群组70(0)～70(D)中选择实体群组70(i)。在实体群组70(i)已存储有数据的状态下，存储器管理电路502可发送读取指令序列至可复写式非易失性存储器模块406，以指示可复写式非易失性存储器模块406从实体群组70(i)中读取数据(亦称为第二数据)。存储器管理电路502可根据第二数据的位元错误状况存储标签置换信息1001。例如，存储器管理电路502可指示错误检查与校正电路508(或编码电路71)解码第二数据并根据解码结果获得第二数据的位元错误状况。例如，假设第二数据的解码结果可反映第二数据的位元错误率，则存储器管理电路502可根据第二数据的位元错误率获得第二数据的位元错误状况。然后，存储器管理电路502可根据第二数据的位元错误状况产生标签置换信息1001。存储器管理电路502可将标签置换信息1001存储于缓冲存储器510中。Fig. 10 is a schematic diagram of storing tag replacement information and moving data according to an exemplary embodiment of the present invention. Referring to FIG. 10 , in an exemplary embodiment, the memory management circuit 502 can select an entity group 70 ( i ) from the entity groups 70 ( 0 )˜70 (D) in FIG. 7 . In the state that the physical group 70(i) has stored data, the memory management circuit 502 can send a read command sequence to the rewritable non-volatile memory module 406 to instruct the rewritable non-volatile memory module 406 to read data (also referred to as second data) from the physical group 70(i). The memory management circuit 502 can store the tag replacement information 1001 according to the bit error status of the second data. For example, the memory management circuit 502 may instruct the ECC circuit 508 (or the encoding circuit 71 ) to decode the second data and obtain the bit error status of the second data according to the decoding result. For example, assuming that the decoding result of the second data can reflect the bit error rate of the second data, the memory management circuit 502 can obtain the bit error status of the second data according to the bit error rate of the second data. Then, the memory management circuit 502 can generate the tag replacement information 1001 according to the bit error status of the second data. The memory management circuit 502 can store the tag replacement information 1001 in the buffer memory 510 .

在一范例实施例中，标签置换信息1001是用以对实体群组70(i)中的至少两个实体单元执行标签置换。通过此标签置换，可将原先指向位元错误率较高(例如位元错误率高于一预设值)的实体单元的某一标签改为指向位元错误率较低(例如位元错误率不高于此预设值)的另一实体单元。在一范例实施例中，相较于始终使用固定的标签配置，动态调整实体群组70(i)中的至少部分实体单元的标签配置(即跨框编码的分组配置)，可有效提高尔后对实体群组70(i)中的数据的解码效率和/或延长实体群组70(i)的使用寿命。In an exemplary embodiment, the tag replacement information 1001 is used to perform tag replacement on at least two physical units in the physical group 70(i). Through this tag replacement, a tag originally pointing to a physical unit with a higher bit error rate (eg, the bit error rate is higher than a preset value) can be changed to point to another physical unit with a lower bit error rate (eg, the bit error rate is not higher than the preset value). In an exemplary embodiment, compared with always using a fixed tag configuration, dynamically adjusting the tag configuration of at least some of the physical units in the physical group 70(i) (i.e., the grouping configuration of cross-frame coding) can effectively improve the subsequent decoding efficiency of data in the physical group 70(i) and/or prolong the service life of the physical group 70(i).

在一范例实施例中，存储器管理电路502可根据第二数据的位元错误状况将原先存储于实体群组70(i)中的第二数据搬移到另一实体群组70(j)。i的数值不等于j的数值。例如，在搬移第二数据的过程中，第二数据可被从实体群组70(i)中读取出来并通过错误检查与校正电路508(或编码电路71)解码。然后，经解码的第二数据可被存储至实体群组70(j)中。在完成第二数据的搬移后，仍存储于实体群组70(i)中的第二数据可被标记为无效，且实体群组70(i)可被抹除。In an exemplary embodiment, the memory management circuit 502 may move the second data originally stored in the physical group 70(i) to another physical group 70(j) according to the bit error status of the second data. The value of i is not equal to the value of j. For example, during the process of moving the second data, the second data may be read from the entity group 70(i) and decoded by the ECC circuit 508 (or the encoding circuit 71). The decoded second data may then be stored into entity group 70(j). After the transfer of the second data is completed, the second data still stored in the entity group 70(i) can be marked as invalid, and the entity group 70(i) can be erased.

在一范例实施例中，存储器管理电路502可判断第二数据的位元错误状况是否符合特定条件。若第二数据的位元错误状况符合特定条件，存储器管理电路502可产生标签置换信息1001。然而，若第二数据的位元错误状况不符合特定条件，存储器管理电路502可不产生标签置换信息1001且不将所述第二数据搬移至实体群组70(j)。In an exemplary embodiment, the memory management circuit 502 can determine whether the bit error condition of the second data meets a specific condition. If the bit error condition of the second data meets a specific condition, the memory management circuit 502 can generate tag replacement information 1001 . However, if the bit error status of the second data does not meet the specified condition, the memory management circuit 502 may not generate the tag replacement information 1001 and not move the second data to the entity group 70(j).

在一范例实施例中，存储器管理电路502可判断从实体群组70(i)中的某一实体单元读取的数据的位元错误率是否高于预设值。若从实体群组70(i)中的某一实体单元读取的数据的位元错误率高于预设值，存储器管理电路502可标记此实体单元，例如将此实体单元标记为高位元错误率(图9中标记为HECC)的实体单元。In an exemplary embodiment, the memory management circuit 502 can determine whether the bit error rate of data read from a certain physical unit in the physical group 70(i) is higher than a preset value. If the bit error rate of data read from a certain physical unit in the physical group 70(i) is higher than a preset value, the memory management circuit 502 may mark the physical unit, for example, mark the physical unit as a high bit error rate (marked as HECC in FIG. 9 ).

在一范例实施例中，存储器管理电路502可判断实体群组70(i)中对应于同一个标签Tag_k的多个实体单元中，属于高位元错误率的实体单元的总数是否高于或等于一预设数目。若实体群组70(i)中对应于同一个标签Tag_k的多个实体单元中，属于高位元错误率的实体单元的总数高于或等于预设数目，存储器管理电路502可产生对应于标签Tag_k的标签置换信息1001。反之，若实体群组70(i)中对应于同一个标签Tag_k的实体单元中，属于高位元错误率的实体单元的总数低于预设数目，则存储器管理电路502可不产生标签置换信息1001。In an exemplary embodiment, the memory management circuit 502 can determine whether the total number of physical units with a high BER among the physical units corresponding to the same tag Tag_k in the physical group 70(i) is greater than or equal to a preset number. If the total number of physical units with high BER among the physical units corresponding to the same tag Tag_k in the physical group 70(i) is greater than or equal to the preset number, the memory management circuit 502 may generate tag replacement information 1001 corresponding to the tag Tag_k. On the contrary, if the total number of physical units with high BER among the physical units corresponding to the same tag Tag_k in the physical group 70(i) is lower than the preset number, the memory management circuit 502 may not generate the tag replacement information 1001 .

以图8与图9为例，假设此预设数目为2。当侦测到实体单元810(3)与810(5)皆属于高位元错误率的实体单元时，存储器管理电路502可判定实体群组70(i)中对应于标签Tag_0的多个实体单元中，属于高位元错误率的实体单元的总数(例如2)等于预设数目(例如2)。因此，存储器管理电路502可产生对应于标签Tag_0的标签置换信息1001。对应于标签Tag_0的标签置换信息1001可记载用以将位元错误率较高的实体单元810(3)与810(5)所对应的标签(即Tag_0)分别与其余位元错误率较低的实体单元所对应的标签对调的信息。Taking FIG. 8 and FIG. 9 as an example, assume that the preset number is 2. When detecting that both the physical units 810(3) and 810(5) belong to the physical units with a high BER, the memory management circuit 502 may determine that among the physical units corresponding to the tag Tag_0 in the physical group 70(i), the total number of physical units with a high BER (for example, 2) is equal to a preset number (for example, 2). Therefore, the memory management circuit 502 can generate the tag replacement information 1001 corresponding to the tag Tag_0. The tag replacement information 1001 corresponding to the tag Tag_0 may record information for swapping the tags corresponding to the physical units 810(3) and 810(5) with higher bit error rates (ie Tag_0) with the tags corresponding to the remaining physical units with lower bit error rates.

图11是根据本发明的一范例实施例所示出的标签置换的示意图。请参照图11，根据标签置换信息1001，在将数据存储至实体群组70(i)时，对应于实体单元810(3)的标签Tag_0与对应于实体单元1110(3)的标签Tag_2可被对调，且对应于实体单元810(5)的标签Tag_0与对应于实体单元1120(5)的标签Tag_4可被对调。藉此，当将数据存储至实体群组70(i)时，原先对应于标签Tag_0且位元错误率较高的实体单元810(3)与810(5)可分别被调整为对应于标签Tag_2与Tag_4，从而避免太多位元错误率较高的实体单元同时存储对应于同一个标签Tag_0的数据。Fig. 11 is a schematic diagram of label replacement according to an exemplary embodiment of the present invention. Referring to FIG. 11 , according to the tag replacement information 1001, when data is stored in the entity group 70(i), the tag Tag_0 corresponding to the entity unit 810(3) and the tag Tag_2 corresponding to the entity unit 1110(3) can be swapped, and the tag Tag_0 corresponding to the entity unit 810(5) can be swapped with the tag Tag_4 corresponding to the entity unit 1120(5). Thereby, when data is stored in the entity group 70(i), the physical units 810(3) and 810(5) originally corresponding to the tag Tag_0 and having a higher bit error rate can be adjusted to correspond to the tags Tag_2 and Tag_4 respectively, thereby avoiding too many physical units with a higher bit error rate simultaneously storing data corresponding to the same tag Tag_0.

换言之，在一范例实施例中，标签置换信息1001的用途可包括将原先对应于同一个标签Tag_k且位元错误率较高的多个实体单元分散用于存储对应于其他标签Tag_p的数据，p的数值不同于k的数值。藉此，可减少对应于同一个标签Tag_k的数据中的错误位元的总数。In other words, in an exemplary embodiment, the use of the tag replacement information 1001 may include distributing a plurality of physical units originally corresponding to the same tag Tag_k and having a high bit error rate to store data corresponding to other tags Tag_p, and the value of p is different from the value of k. Thereby, the total number of error bits in the data corresponding to the same tag Tag_k can be reduced.

图12是根据本发明的一范例实施例所示出的写入新数据的示意图。请参照图12，接续于图7至图11的范例实施例，在将标签置换信息1001存储至缓冲存储器510后，存储器管理电路502可从主机系统11接收指示存储数据1201(亦称为第一数据)的写入指令。根据此写入指令，存储器管理电路502可指示编码电路71对数据1201进行编码。另一方面，存储器管理电路502可从图6的闲置区602中提取经抹除的实体群组70(i)并从缓冲存储器510中读取对应于实体群组70(i)的标签置换信息1001。存储器管理电路502可根据标签置换信息1001指示可复写式非易失性存储器模块将经编码电路71编码的数据1201存储至可复写式非易失性存储器模块406中的实体群组70(i)中。FIG. 12 is a schematic diagram of writing new data according to an exemplary embodiment of the present invention. Please refer to FIG. 12 , following the example embodiments of FIG. 7 to FIG. 11 , after the tag replacement information 1001 is stored in the buffer memory 510, the memory management circuit 502 may receive a write command from the host system 11 indicating to store the data 1201 (also referred to as first data). According to the write instruction, the memory management circuit 502 can instruct the encoding circuit 71 to encode the data 1201 . On the other hand, the memory management circuit 502 can extract the erased entity group 70(i) from the spare area 602 of FIG. 6 and read the tag replacement information 1001 corresponding to the entity group 70(i) from the buffer memory 510 . The memory management circuit 502 can instruct the rewritable nonvolatile memory module to store the data 1201 encoded by the encoding circuit 71 into the entity group 70(i) in the rewritable nonvolatile memory module 406 according to the tag replacement information 1001 .

图13是根据本发明的一范例实施例所示出的根据调整后的标签配置存储数据的示意图。请参照图13，接续于图12的范例实施例，存储器管理电路502可将经编码的数据1201与通过对数据1201进行编码所产生的奇偶数据(即全域奇偶数据)存储至实体群组70(i)中。例如，根据实体群组70(i)预设的标签配置，存储器管理电路502可将经编码的数据1201的一部分数据(亦称为第一部分数据)存储于标签Tag_0所预设指向的实体单元810(0)～810(2)、810(4)、810(6)并将对应于数据1201的全域奇偶数据存储于实体单元810(7)。Fig. 13 is a schematic diagram of storing data according to an adjusted tag configuration according to an exemplary embodiment of the present invention. Referring to FIG. 13 , following the exemplary embodiment of FIG. 12 , the memory management circuit 502 can store the encoded data 1201 and the parity data generated by encoding the data 1201 (ie global parity data) into the entity group 70(i). For example, according to the preset tag configuration of the entity group 70(i), the memory management circuit 502 can store a part of the encoded data 1201 (also referred to as the first part of data) in the entity units 810(0)-810(2), 810(4), and 810(6) preset by the tag Tag_0 and store global parity data corresponding to the data 1201 in the entity unit 810(7).

另一方面，根据标签置换信息1001，存储器管理电路502可将经编码的数据1201的另一部分数据(亦称为第二部分数据)存储于经对调的标签Tag_0所指向的实体单元1110(3)与1120(5)。例如，实体单元1110(3)与1120(5)是用以替换标签Tag_0所预设指向的实体单元810(3)与810(5)，以降低数据1201所属的跨框编码群组的位元错误率。On the other hand, according to the tag replacement information 1001, the memory management circuit 502 can store another part of the encoded data 1201 (also referred to as the second part of data) in the physical units 1110(3) and 1120(5) pointed to by the swapped tag Tag_0. For example, the physical units 1110 ( 3 ) and 1120 ( 5 ) are used to replace the physical units 810 ( 3 ) and 810 ( 5 ) targeted by the tag Tag_0 to reduce the bit error rate of the cross-frame coding group to which the data 1201 belongs.

在一范例实施例中，实体单元1110(3)的位元错误率(必须)低于实体单元810(3)的位元错误率，且实体单元1120(5)的位元错误率(必须)低于实体单元810(5)的位元错误率。相较于实体群组70(i)预设的标签配置(即跨框编码的群组配置)，根据标签置换信息1001来执行标签置换并存储经编码的数据1201，对应于标签Tag_0的所有实体单元所存储的数据的位元错误率可被有效降低。此外，经过所述标签置换，原先对应于标签Tag_0且位元错误率较高的实体单元810(3)与810(5)可被分散调整为用以存储对应于标签Tag_2与Tag_4的部分数据，从而避免位元错误率较高的实体单元在使用上过度集中。In an exemplary embodiment, the bit error rate of physical unit 1110(3) is (must) be lower than the bit error rate of physical unit 810(3), and the bit error rate of physical unit 1120(5) is (must) be lower than the bit error rate of physical unit 810(5). Compared with the preset tag configuration of the entity group 70(i) (i.e., the group configuration of cross-frame coding), the tag replacement is performed according to the tag replacement information 1001 and the coded data is stored 1201, and the bit error rate of the data stored in all the physical units corresponding to the tag Tag_0 can be effectively reduced. In addition, after the tag replacement, the physical units 810(3) and 810(5) originally corresponding to the tag Tag_0 and having a higher bit error rate can be distributed and adjusted to store part of the data corresponding to the tags Tag_2 and Tag_4, so as to avoid excessive concentration of the physical units with a higher bit error rate.

在一范例实施例中，在将经编码的数据1201及相应的全域奇偶数据存储至实体单元810(0)～810(2)、1110(3)、810(4)、1120(5)、810(6)及810(7)的过程中，数据1201的数据片段可存储于各个实体单元中的数据区(data area)。同时，存储器管理电路502可将标签置换信息1001存储至经标签置换的实体单元中的闲置区(spare area)。例如，存储器管理电路502可将标签置换信息1001中与实体单元1110(3)有关的标签置换信息存储于实体单元1110(3)中的闲置区，将标签置换信息1001中与实体单元1120(5)有关的标签置换信息存储于实体单元1120(5)中的闲置区，将标签置换信息1001中与实体单元810(3)有关的标签置换信息存储于实体单元810(3)中的闲置区，并将标签置换信息1001中与实体单元810(5)有关的标签置换信息存储于实体单元810(5)中的闲置区。然后，存储器管理电路502可删除缓冲存储器510中的标签置换信息1001。尔后，当从实体单元1110(3)、1120(5)、810(3)和/或810(5)读取数据时，存储器管理电路502可根据实体单元1110(3)、1120(5)、810(3)和/或810(5)中的标签置换信息得知当前实体单元1110(3)和/或1120(5)皆是用以存储属于标签Tag_0的数据(非预设的属于标签Tag_2或Tag_4的数据)，当前实体单元810(3)是用以存储属于标签Tag_2的数据(非预设的属于标签Tag_0的数据)和/或当前实体单元810(5)是用以存储属于标签Tag_4的数据(非预设的属于标签Tag_0的数据)。在一范例实施例中，当欲从实体群组70(i)读取数据1201时，存储器管理电路502可指示可复写式非易失性存储器模块406从实体单元810(0)～810(2)、1110(3)、810(4)、1120(5)、810(6)及810(7)中读取数据并指示编码电路71对所读取的数据进行解码。In an exemplary embodiment, during the process of storing the encoded data 1201 and the corresponding global parity data in the physical units 810(0)˜810(2), 1110(3), 810(4), 1120(5), 810(6) and 810(7), the data segments of the data 1201 may be stored in data areas of the respective physical units. At the same time, the memory management circuit 502 can store the tag replacement information 1001 in a spare area in the tag-substituted physical unit. For example, the memory management circuit 502 may store the label replacement information related to the physical unit 1110(3) in the label replacement information 1001 in the idle area of the physical unit 1110(3), store the label replacement information related to the physical unit 1120(5) in the label replacement information 1001 in the idle area of the physical unit 1120(5), and store the label replacement information related to the physical unit 810(3) in the label replacement information 1001 in the In the idle area of the physical unit 810(3), store the label replacement information related to the physical unit 810(5) in the label replacement information 1001 in the idle area of the physical unit 810(5). Then, the memory management circuit 502 can delete the tag replacement information 1001 in the buffer memory 510 . Afterwards, when reading data from the physical units 1110(3), 1120(5), 810(3) and/or 810(5), the memory management circuit 502 can know from the tag replacement information in the physical units 1110(3), 1120(5), 810(3) and/or 810(5) that the current physical units 1110(3) and/or 1120(5) are all used to store tags belonging to Tag_0 data (non-preset data belonging to tag Tag_2 or Tag_4), the current entity unit 810(3) is used to store data belonging to tag Tag_2 (non-preset data belonging to tag Tag_0) and/or the current entity unit 810(5) is used to store data belonging to tag Tag_4 (non-preset data belonging to tag Tag_0). In an exemplary embodiment, when data 1201 is to be read from the physical group 70(i), the memory management circuit 502 can instruct the rewritable non-volatile memory module 406 to read data from the physical units 810(0)˜810(2), 1110(3), 810(4), 1120(5), 810(6) and 810(7) and instruct the encoding circuit 71 to decode the read data.

在一范例实施例中，当欲将特定数据存储至实体群组70(i)或从实体群组70(i)读取特定数据时，存储器管理电路502可判断是否存在对应于实体群组70(i)的标签置换信息(例如标签置换信息1001)。例如，存储器管理电路502可判断缓冲存储器510中是否存在对应于实体群组70(i)的标签置换信息(例如标签置换信息1001)。或者，存储器管理电路502可判断当前欲存储此数据的一或多个实体单元或者当前欲读取的一或多个实体单元中是否存在所述标签置换信息。若存储器管理电路502可取得对应于实体群组70(i)的标签置换信息，表示对应于实体群组70(i)的标签置换信息(例如标签置换信息1001)存在，则存储器管理电路502可根据对应于实体群组70(i)的标签置换信息(例如标签置换信息1001)来对实体群组70(i)执行标签置换后的数据存取。相关操作细节皆已详述于上，在此便不赘述。此外，若存储器管理电路502无法取得对应于实体群组70(i)的标签置换信息，表示对应于实体群组70(i)的标签置换信息(例如标签置换信息1001)不存在，则存储器管理电路502可根据实体群组70(i)预设的标签配置(即预设的跨框编码的群组配置)来存取实体群组70(i)。In an exemplary embodiment, when specific data is to be stored in or read from the entity group 70(i), the memory management circuit 502 may determine whether there is tag replacement information corresponding to the entity group 70(i) (eg, tag replacement information 1001). For example, the memory management circuit 502 may determine whether there is tag replacement information corresponding to the entity group 70(i) in the buffer memory 510 (eg, tag replacement information 1001 ). Alternatively, the memory management circuit 502 may determine whether the tag replacement information exists in one or more physical units currently intended to store the data or one or more physical units currently intended to be read. If the memory management circuit 502 can obtain the label replacement information corresponding to the entity group 70(i), indicating that the label replacement information corresponding to the entity group 70(i) (such as label replacement information 1001) exists, then the memory management circuit 502 can perform data access after label replacement to the entity group 70(i) according to the label replacement information (such as label replacement information 1001) corresponding to the entity group 70(i). The relevant operation details have been described in detail above, and will not be repeated here. In addition, if the memory management circuit 502 cannot obtain the label replacement information corresponding to the entity group 70(i), indicating that the label replacement information corresponding to the entity group 70(i) (such as the label replacement information 1001) does not exist, the memory management circuit 502 can access the entity group 70(i) according to the preset label configuration of the entity group 70(i) (i.e., the preset cross-frame coding group configuration).

在一范例实施例中，存储器管理电路502可发送读取指令序列至可复写式非易失性存储器模块406。此读取指令序列指示从实体群组70(i)读取数据(例如所述第二数据)。存储器管理电路502可根据第二数据的位元错误状况来调整实体群组70(i)的跨框编码群组的配置。特别是，此跨框编码群组的配置可反映实体群组70(i)中的多个实体单元是属于同一个跨框编码群组(和/或实体群组70(i)中的某一个实体单元是属于某一个跨框编码群组)。尔后，存储器控制电路单元502可根据经调整的跨框编码群组的配置来存取实体群组70(i)。In an exemplary embodiment, the memory management circuit 502 can send a read command sequence to the rewritable non-volatile memory module 406 . This sequence of read commands instructs to read data (eg, the second data) from entity group 70(i). The memory management circuit 502 can adjust the configuration of the cross-frame coding group of the entity group 70(i) according to the bit error condition of the second data. In particular, the configuration of the cross-frame coding group can reflect that multiple physical units in the entity group 70(i) belong to the same cross-frame coding group (and/or a certain physical unit in the entity group 70(i) belongs to a certain cross-frame coding group). Thereafter, the memory control circuit unit 502 can access the entity group 70(i) according to the adjusted configuration of the cross-frame encoding group.

在一范例实施例中，调整实体群组70(i)的跨框编码群组的配置可通过产生或记录所述对应于实体群组70(i)的标签置换信息来达成，以供往后存取实体群组70(i)时查询。关于如何产生与使用对应于实体群组70(i)的标签置换信息的相关细节皆已详述于上，在此便不赘述。In an exemplary embodiment, adjusting the configuration of the cross-frame coding group of the entity group 70(i) can be achieved by generating or recording the label replacement information corresponding to the entity group 70(i), for querying when accessing the entity group 70(i) later. The relevant details on how to generate and use the tag replacement information corresponding to the entity group 70(i) have been described in detail above, and will not be repeated here.

在一范例实施例中，调整实体群组70(i)的跨框编码群组的配置亦可包括直接调整实体群组70(i)的跨框编码的群组配置或直接调整产生实体群组70(i)的跨框编码群组的配置的演算法，从而改变调整实体群组70(i)的跨框编码群组的预设配置(或当前配置)。在一范例实施例中，通过直接调整实体群组70(i)的跨框编码群组的配置或调整产生实体群组70(i)的跨框编码群组的配置的演算法，存储器管理电路502可使用或不使用对应于实体群组70(i)的标签置换信息来根据调整后的实体群组70(i)的跨框编码群组的配置来存取实体群组70(i)。In an exemplary embodiment, adjusting the configuration of the cross-frame coding group of the entity group 70(i) may also include directly adjusting the group configuration of the cross-frame coding group of the entity group 70(i) or directly adjusting the algorithm for generating the configuration of the cross-frame coding group of the entity group 70(i), thereby changing and adjusting the default configuration (or current configuration) of the cross-frame coding group of the entity group 70(i). In an exemplary embodiment, by directly adjusting the configuration of the cross-frame coding group of the entity group 70(i) or adjusting the algorithm for generating the configuration of the cross-frame coding group of the entity group 70(i), the memory management circuit 502 can use or not use the label replacement information corresponding to the entity group 70(i) to access the entity group 70(i) according to the adjusted configuration of the cross-frame coding group of the entity group 70(i).

从另一角度而言，在一范例实施例中，针对同一个实体群组70(i)，随着实体群组70(i)中的至少部分实体单元的位元错误状况(例如位元错误率)改变，实体群组70(i)中针对数据存储的标签配置(即跨框编码的群组配置)可被持续改变。例如，在图7与图8的范例实施例中，存储于实体群组70(i)中的数据是以第一种标签配置模式(亦称为跨框编码的第一群组配置)来进行数据存储。然而，随着实体群组70(i)中的至少部分实体单元的位元错误率改变，在图12与图13的范例实施例中，存储于实体群组70(i)中的数据则改变为以第二种标签配置模式(亦称为跨框编码的第二群组配置)来进行数据存储。通过改变实体群组70(i)的跨框编码群组的配置，可有效提高实体群组70(i)的使用效率，延长实体群组70(i)的使用寿命，甚至延长整个可复写式非易失性存储器模块406的使用寿命。From another point of view, in an exemplary embodiment, for the same physical group 70(i), as the bit error status (such as bit error rate) of at least some of the physical units in the physical group 70(i) changes, the tag configuration for data storage in the physical group 70(i) (ie, the group configuration of the cross-frame coding) can be continuously changed. For example, in the exemplary embodiments of FIG. 7 and FIG. 8 , the data stored in the entity group 70(i) is stored in the first tag configuration mode (also called the first group configuration of cross-frame encoding). However, as the bit error rate of at least some of the physical units in the physical group 70(i) changes, in the exemplary embodiments of FIG. 12 and FIG. 13 , the data stored in the physical group 70(i) is changed to the second tag configuration mode (also known as the second group configuration of cross-frame coding) for data storage. By changing the configuration of the cross-frame encoding group of the entity group 70(i), the usage efficiency of the entity group 70(i) can be effectively improved, the service life of the entity group 70(i), and even the service life of the entire rewritable non-volatile memory module 406 can be extended.

图14是根据本发明的一范例实施例所示出的跨框编码管理方法的流程图。请参照图14，在步骤S1401中，读取对应于第一实体群组的标签置换信息。在步骤S1402中，编码第一数据。在步骤S1403中，将经编码的第一数据的第一部分数据存储至所述第一实体群组中对应于某一标签信息(亦称为第一标签信息)的至少一第一实体单元。在步骤S1404中，根据所述标签置换信息将经编码的第一数据的第二部分数据存储至所述第一实体群组中对应于另一标签信息(亦称为第二标签信息)的至少一第二实体单元。须注意的是，所述第一标签信息对应于某一跨框编码群组(亦称为第一跨框编码群组)，所述第二标签信息对应于另一跨框编码群组(亦称为第二跨框编码群组)，且第一跨框编码群组不同于第二跨框编码群组。Fig. 14 is a flowchart of a method for managing cross-frame coding according to an exemplary embodiment of the present invention. Referring to FIG. 14 , in step S1401 , read tag replacement information corresponding to the first entity group. In step S1402, first data is encoded. In step S1403, store the encoded first part of the first data in at least one first entity unit corresponding to certain tag information (also referred to as first tag information) in the first entity group. In step S1404, store the encoded second part of the first data in at least one second entity unit corresponding to another label information (also referred to as second label information) in the first entity group according to the label replacement information. It should be noted that the first label information corresponds to a certain frame-crossing coding group (also called the first frame-crossing coding group), the second label information corresponds to another frame-crossing coding group (also called the second frame-crossing coding group), and the first frame-crossing coding group is different from the second frame-crossing coding group.

以图13为例，第一实体单元可包括实体单元810(0)～810(2)、810(4)、810(6)(及810(7))，而第二实体单元可包括实体单元1110(3)与1120(5)。其中，实体单元810(0)～810(2)、810(4)、810(6)(及810(7))所对应的初始标签为Tag_0，而实体单元1110(3)与1120(5)所对应的初始标签则分别为Tag_2与Tag_4。标签Tag_2与Tag_4所对应的跨框编码群组不同于标签Tag_0所对应的跨框编码群组。但是，在调整跨框编码群组的配置(例如参考标签置换信息1001)后，实体单元810(0)～810(2)、810(4)、810(6)、810(7)、1110(3)及1120(5)可用以存储同一个跨框编码群组中的数据。相关操作细节皆已详述于上，在此便不赘述。Taking FIG. 13 as an example, the first physical unit may include physical units 810(0)-810(2), 810(4), 810(6) (and 810(7)), and the second physical unit may include physical units 1110(3) and 1120(5). Among them, the initial tags corresponding to the physical units 810(0)-810(2), 810(4), 810(6) (and 810(7)) are Tag_0, and the initial tags corresponding to the physical units 1110(3) and 1120(5) are Tag_2 and Tag_4 respectively. The cross-frame encoding group corresponding to tags Tag_2 and Tag_4 is different from the cross-frame encoding group corresponding to tag Tag_0. However, after adjusting the configuration of the cross-frame coding group (for example, the reference label replacement information 1001), the physical units 810(0)-810(2), 810(4), 810(6), 810(7), 1110(3) and 1120(5) can be used to store data in the same cross-frame coding group. The relevant operation details have been described in detail above, and will not be repeated here.

须注意的是，在前述范例实施例中，每一个实体群组中包含的实体单元的总数、预设的标签配置、及经调整的标签配置等都仅为范例且可根据实务需求调整，而非用以限制本发明。此外，标签置换信息(例如标签置换信息1001)可记载任何可用以调整所述标签配置的相关信息，本发明不限制其具体内容。It should be noted that, in the aforementioned exemplary embodiments, the total number of physical units contained in each physical group, the default label configuration, and the adjusted label configuration are just examples and can be adjusted according to practical requirements, rather than limiting the present invention. In addition, the label replacement information (for example, label replacement information 1001 ) may record any relevant information that can be used to adjust the label configuration, and the present invention does not limit its specific content.

图15是根据本发明的一范例实施例所示出的跨框编码管理方法的流程图。请参照图15，在步骤S1501中，从多个实体群组中选择一个实体群组作为第一实体群组。在步骤S1502中，从所述第一实体群组中读取数据(即第二数据)。在步骤S1503中，判断所述数据的错误位元状况是否符合特定条件。若所述数据的错误位元状况符合特定条件，在步骤S1504中，存储对应于所述第一实体群组的标签置换信息。若所述数据的错误位元状况不符合特定条件，可回到步骤S1501中，选择另一实体群组作为第一实体群组。Fig. 15 is a flow chart of a method for managing cross-frame coding according to an exemplary embodiment of the present invention. Referring to FIG. 15 , in step S1501 , an entity group is selected from multiple entity groups as the first entity group. In step S1502, read data (that is, second data) from the first entity group. In step S1503, it is determined whether the error bit status of the data meets a specific condition. If the error bit status of the data meets a specific condition, in step S1504, store tag replacement information corresponding to the first entity group. If the error bit status of the data does not meet the specific condition, return to step S1501 to select another entity group as the first entity group.

在步骤S1504之后，步骤S1505中，将所述数据从所述第一实体群组搬移到所述多个实体群组中的另一实体群组(即第二实体群组)进行存储。在步骤S1506中，第一实体群组可被抹除。After step S1504, in step S1505, the data is moved from the first entity group to another entity group (ie, the second entity group) among the plurality of entity groups for storage. In step S1506, the first entity group may be erased.

图16是根据本发明的一范例实施例所示出的跨框编码管理方法的流程图。请参照图16，在步骤S1601中，接收指示存储第一数据的写入指令。在步骤S1602中，编码第一数据。在步骤S1603中，判断是否存在对应于第一实体群组的标签置换信息。若存在对应于第一实体群组的标签置换信息，在步骤S1604中，读取对应于所述第一实体群组的标签置换信息。在步骤S1605中，将经编码的第一数据的第一部分数据存储至所述第一实体群组中对应于第一标签信息的至少一第一实体单元。在步骤S1606中，根据所述标签置换信息将经编码的第一数据的第二部分数据存储至所述第一实体群组中对应于第二标签信息的至少一第二实体单元。此外，若步骤S1603判断为否，则在步骤S1607中，(仅)将经编码的第一数据存储至所述第一实体群组中对应于第一标签信息的多个第一实体单元，而不须根据标签置换结果存取第一实体群组。Fig. 16 is a flowchart of a method for managing cross-frame coding according to an exemplary embodiment of the present invention. Referring to FIG. 16, in step S1601, a write instruction indicating to store first data is received. In step S1602, first data is encoded. In step S1603, it is determined whether there is label replacement information corresponding to the first entity group. If there is tag replacement information corresponding to the first entity group, in step S1604, read the tag replacement information corresponding to the first entity group. In step S1605, store the encoded first part of the first data in at least one first entity unit corresponding to the first tag information in the first entity group. In step S1606, store the encoded second part of the first data in at least one second entity unit corresponding to the second label information in the first entity group according to the label replacement information. In addition, if step S1603 judges no, then in step S1607, (only) store the encoded first data in a plurality of first entity units corresponding to the first label information in the first entity group, without accessing the first entity group according to the label replacement result.

图17是根据本发明的一范例实施例所示出的跨框编码管理方法的流程图。请参照图17，在步骤S1701中，接收指示读取第一数据的读取指令。在步骤S1702中，判断是否存在对应于第一实体群组的标签置换信息。若存在对应于第一实体群组的标签置换信息，在步骤S1703中，读取对应于所述第一实体群组的标签置换信息。在步骤S1704中，从所述第一实体群组中对应于第一标签信息的至少一第一实体单元中读取第一数据的第一部分数据。在步骤S1705中，根据所述标签置换信息从所述第一实体群组中对应于第二标签信息的至少一第二实体单元读取第一数据的第二部分数据。此外，若步骤S1702判断为否，则在步骤S1706中，(仅)从所述第一实体群组中对应于第一标签信息的多个第一实体单元中读取所述第一数据，而不须根据标签置换结果存取第一实体群组。尔后，在步骤S1707中，解码所读取的第一数据。经解码的第一数据可被回传以回应所述读取指令。Fig. 17 is a flowchart of a method for managing cross-frame coding according to an exemplary embodiment of the present invention. Referring to FIG. 17 , in step S1701, a read instruction indicating to read first data is received. In step S1702, it is determined whether there is label replacement information corresponding to the first entity group. If there is tag replacement information corresponding to the first entity group, in step S1703, read the tag replacement information corresponding to the first entity group. In step S1704, read a first part of the first data from at least one first entity unit corresponding to the first tag information in the first entity group. In step S1705, read the second part of the first data from at least one second entity unit corresponding to the second label information in the first entity group according to the label replacement information. In addition, if the determination in step S1702 is negative, then in step S1706, (only) read the first data from a plurality of first entity units corresponding to the first tag information in the first entity group, without accessing the first entity group according to the tag replacement result. Thereafter, in step S1707, the read first data is decoded. The decoded first data may be returned in response to the read command.

然而，图14～图17中各步骤已详细说明如上，在此便不再赘述。值得注意的是，图14～图17中各步骤可以实作为多个程序码或是电路，本发明不加以限制。此外，图14～图17的方法可以搭配以上范例实施例使用，也可以单独使用，本发明不加以限制。However, the steps in FIGS. 14 to 17 have been described in detail above, and will not be repeated here. It should be noted that each step in FIGS. 14-17 can be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the methods in FIGS. 14 to 17 can be used in combination with the above exemplary embodiments, or can be used alone, which is not limited by the present invention.

综上所述，本发明所提出的范例实施例可根据可复写式非易失性存储器模块中的特定实体群组的使用状态(例如各实体单元的损耗程度和/或位元错误状态)来动态改变此实体群组的标签配置(即跨框编码群组的配置)。通过动态管理可复写式非易失性存储器模块中的跨框编码群组的配置，可有效提高可复写式非易失性存储器模块的使用效率(例如提高对存储于可复写式非易失性存储器模块中的数据的错误更正能力和/或延长可复写式非易失性存储器模块的使用寿命)。To sum up, the exemplary embodiments of the present invention can dynamically change the tag configuration (ie, the configuration of the cross-frame encoding group) of a specific physical group in the rewritable non-volatile memory module according to the usage status of the specific physical group (such as the degree of wear and/or bit error status of each physical unit). By dynamically managing the configuration of the cross-frame coding group in the rewritable nonvolatile memory module, the usage efficiency of the rewritable nonvolatile memory module can be effectively improved (for example, improving the error correction capability of data stored in the rewritable nonvolatile memory module and/or prolonging the service life of the rewritable nonvolatile memory module).

最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.