CN113555324B - Electronic packaging - Google Patents

An electronic package is characterized in that two wrapping parts made of different materials are distributed among a plurality of mutually stacked electronic components to adjust stress distribution of the electronic package, so that the warping degree of the electronic package can be optimally regulated.

Electronic package

Technical Field

The present invention relates to a semiconductor package process, and more particularly, to a multi-chip stacked electronic package and a method for fabricating the same.

Background

With the development of the electronic industry, the electronic products now tend to be thin, light, small and functionally diversified, and different packaging types are developed in the semiconductor packaging technology. In order to meet the requirements of high Integration, miniaturization (Miniaturization), high circuit performance, and the like of semiconductor devices, flip chip (Flip chip) bonding packaging technology has been developed, and in order to improve the performance (ability) and capacity (capability) of a single semiconductor package to meet the trend of miniaturization, high capacity, and high speed of electronic products, the industry has presented a multi-chip module (Multichip Module, abbreviated as MCM) form in a semiconductor package to Flip-chip stack a plurality of chips on a single carrier (such as a package substrate or a lead frame), such as the TWI331371 patent (hereinafter referred to as the first proposal) or the TWI527170 patent (hereinafter referred to as the second proposal).

However, in the conventional multi-chip module, as in the first case, there is a gap between the upper and lower chips, which results in the chip being prone to warp and even crack during the subsequent high temperature process.

In addition, in the first prior art, the conductive bumps (e.g. 39) for electrically connecting the upper and lower chips are not covered by the encapsulant (e.g. 38), so that the stress of the conductive bumps cannot be effectively dispersed, and the chips are easily warped, so that the alignment between the upper and lower chips is offset, and even the electrical connection between the upper and lower chips is greatly affected, resulting in the problems of low yield and poor product reliability. Furthermore, when stacking more wafers, stress is continuously accumulated, so that the warpage degree is more obvious when bending in the same direction, and wafer breakage is more likely to occur.

On the other hand, the upper and lower chips of the second prior art are also filled with a primer (such as reference numerals 18a,18b,18 c) to encapsulate the conductive bumps (such as reference numerals 172,173,262,263,25 a) for electrically connecting the upper and lower chips, but the conductive bumps are not matched with the thermal expansion coefficient (Coefficient of thermal expansion, abbreviated as CTE) of the primer (mismatch), so that uneven thermal stress is likely to occur, and when thermal cycle (THERMAL CYCLE) is performed, the primer and the chips are pushed against each other to warp (warpage) the chips, so that misalignment between the upper and lower chips is caused, and even the electrical connection between the upper and lower chips is greatly affected, resulting in problems of too low yield and poor product reliability. Furthermore, when stacking more wafers, stress is continuously accumulated, so that the warpage degree is more obvious when bending in the same direction, and wafer breakage is more likely to occur.

In addition, although the second case covers the primer with the encapsulant (such as reference numerals 19a,19b,19 c) to assist the primer in dispersing the stress of the conductive bumps, the encapsulant does not cover the conductive bumps and cannot effectively disperse the stress of the conductive bumps.

Therefore, how to overcome the above problems of the prior art has been an urgent issue.

Disclosure of Invention

In view of the foregoing drawbacks of the prior art, the present invention provides an electronic package, which can optimally control the warpage of the electronic package.

The electronic package comprises a bearing piece, a first package module and a second package module, wherein the first package module is arranged on the bearing piece and comprises at least one first electronic element, a first layout area is defined on the lower surface of the first electronic element, one of a first cladding part and a second cladding part is arranged in the first layout area, the material of the second cladding part is different from that of the first cladding part, the second package module is overlapped on the first package module and comprises a plurality of second electronic elements which are stacked, the lower surface of each second electronic element is respectively defined with a second layout area, at least one of the second layout areas is provided with the first cladding part and the second cladding part which are oppositely arranged in the other one of the first layout area, and a stress balance line is defined between the first package module and the second package module, so that the strain of the first package module and the strain of the second package module are complementary, and the stress of the first package module and the second package module are mutually offset.

In the foregoing electronic package, the first coating portion and the second coating portion are partially disposed on the first layout area.

In the foregoing electronic package, the first coating portion and the second coating portion are partially disposed on the second layout area.

In the foregoing electronic package, the first covering portion is disposed entirely on the first layout area.

In the foregoing electronic package, the first coating portion is disposed entirely on the second layout area.

In the foregoing electronic package, the second coating portion is disposed entirely on the first layout area.

In the foregoing electronic package, the second coating portion is disposed entirely on the second layout area.

In the foregoing electronic package, the thermal expansion coefficient of the first coating portion is different from the thermal expansion coefficient of the second coating portion.

In the aforementioned electronic package, the second coating portion is a solid filler.

In the foregoing electronic package, the plurality of second electronic components are stacked with each other by a plurality of conductive components.

In the foregoing electronic package, the second electronic component is stacked on the first electronic component by a plurality of conductive elements.

In the foregoing electronic package, the first electronic component is stacked on the carrier by a plurality of conductive elements.

In the foregoing electronic package, a plurality of the first electronic components are stacked on the carrier, and each of the first electronic components is stacked by a plurality of conductive components.

The electronic package further includes a packaging layer for packaging the first electronic component and the second electronic component.

In the foregoing electronic package, the first layout area defines a first section and a second section adjacent to the first section, so that the first section is cross-shaped or rectangular.

In the foregoing electronic package, the second layout area defines a first section and a second section adjacent to the first section, so that the first section is cross-shaped or rectangular.

In the foregoing electronic package, the second coating portion is disposed at a corner of the first or second layout area.

In the foregoing electronic package, the second coating portion is disposed on two opposite outer sides of the first or second layout area.

Therefore, compared with the prior art, the electronic package of the invention can arrange the first and second coating parts according to the whole strain condition of the electronic package so as to adjust the stress distribution of the electronic package, thereby optimally regulating the warping degree of the electronic package.

Drawings

Fig. 1 is a schematic cross-sectional view of an electronic package according to an embodiment of the invention.

Fig. 1' and 1 "are top views of different versions of fig. 1.

Fig. 1A and 1A' are schematic cross-sectional views of other patterns of fig. 1.

Fig. 2 is a schematic cross-sectional view of another embodiment of the electronic package of the present invention.

Fig. 2', 2A and 2A' are schematic cross-sectional views of other versions of fig. 2.

Fig. 3 is a schematic cross-sectional view of another embodiment of the electronic package of the present invention.

Fig. 3A and 3A' are schematic cross-sectional views of other patterns of fig. 3.

Fig. 4 and 4' are schematic cross-sectional views of the other different embodiments of fig. 1.

Symbol description

1,2,3,4 Electronic package

1A first Package Module

1B second packaging Module

1C cladding structure

10. Bearing piece

11. First electronic component

11A flip chip side

11B stacking side

12. Second electronic component

12A flip chip side

12B stacking side

13. Conductive element

14,24 First coating portion

15,25 Second coating portions

16. Encapsulation layer

A first layout area

A' second layout area

A1 First section

A2 Second section

F filling direction

L stress balance line

S1 first filling space

S2 second filling space

S3 third filling space

S4 fourth filling space

And W1 and W2 warp directions.

Detailed Description

Further advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure, by describing embodiments of the present invention with reference to specific examples.

It should be understood that the structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure for the understanding and reading by those skilled in the art, and are not intended to limit the scope of the invention, which is defined by the claims, so that any structural modifications, proportional changes, or dimensional adjustments should not be made in the essential significance of the invention, and should still fall within the scope of the present disclosure without affecting the efficacy or achievement of the present invention. In the meantime, the terms such as "first", "second", "third", "upper", "lower", and "a" and the like are also used in the present specification for convenience of description, but are not intended to limit the scope of the present invention, and the relative relation is changed or adjusted without substantial change of technical content, and are considered as the scope of the present invention.

Fig. 1 is a schematic cross-sectional view of an electronic package 1 of the present invention. As shown in fig. 1, the electronic package 1 includes a carrier 10, a first package module 1a disposed on the carrier 10, and a second package module 1b stacked on the first package module 1a, wherein the first package module 1a and the second package module 1b are stacked by a plurality of conductive elements 13, and the first package module 1a and the second package module 1b are covered by a package layer 16.

The first package module 1a includes at least one first electronic device 11, and a first layout area a is defined on a lower surface of the first electronic device 11 to layout a cladding structure 1c, wherein the cladding structure 1c includes a first cladding portion 14 and/or a second cladding portion 15, and a material of the second cladding portion 15 is different from a material of the first cladding portion 14.

The second package module 1b includes a plurality of stacked second electronic components 12, and a second layout area a' is defined on a lower surface of the second electronic components 12 to layout the first cladding portion 14 and/or the second cladding portion 15, wherein the plurality of conductive components 13 are stacked with each other to enable the cladding structure 1c to cladding the conductive components 13.

The carrier 10 is, for example, a package substrate having a core layer and a circuit structure or a circuit structure without a core layer (coreless), and includes at least one insulating layer and at least one circuit layer combined with the insulating layer, such as at least one fan out (fan out) redistribution circuit layer (redistribution layer, RDL for short). It should be understood that the carrier 10 may be other boards for carrying chips, such as a leadframe (LEAD FRAME), a wafer (wafer), or other carrier board with metal wiring (routing), and the like, and is not limited to the above.

In this embodiment, the carrier 10 can be manufactured by various processes, for example, a wafer process may be used to manufacture a copper circuit layer and a chemical vapor deposition (Chemical vapor deposition, CVD) may be used to form a silicon nitride or silicon oxide layer as an insulating layer, or a general amorphous wafer process may be used to form a copper circuit layer, i.e. a low-cost polymer dielectric material may be used as an insulating layer, such as Polyimide (PI), poly-p-phenylene terephtalate (Polybenzoxazole, PBO), prepreg (Prepreg, PP), molding compound (molding compound), photosensitive dielectric layer or other materials, etc. may be formed by a coating method.

In the present embodiment, the number of the first electronic components 11 is two, the first electronic components 11 are stacked on each other and are connected to the carrier 10 by one of them, and the plurality of second electronic components 12 are stacked on each other and are stacked on the first electronic components 11 by one of them.

In the present embodiment, the first electronic device 11 is an active device, a passive device or a combination thereof, wherein the active device is a semiconductor chip, and the passive device is a resistor, a capacitor or an inductor. For example, the first electronic device 11 is a semiconductor chip, the upper surface thereof is a stacking side 11b, and the lower surface thereof is a flip-chip side 11a, such that the first electronic devices 11 are electrically connected to each other by flip-chip bonding of the flip-chip side 11a to the stacking side 11b of the other via a plurality of bump-like conductive devices 13, such as solder materials, metal pillars (pillars), or others, and such that the lowermost first electronic device 11 is flip-chip bonded to the carrier 10 via the conductive devices 13 and electrically connected to the circuit layer of the carrier 10.

In addition, the second electronic device 12 is an active device, such as a semiconductor chip, a passive device, such as a resistor, a capacitor, and an inductor, or a combination thereof. For example, the second electronic component 12 is a semiconductor chip, the upper surface thereof is a stacking side 12b, and the lower surface thereof is a flip-chip side 12a, so that the second electronic components 12 are electrically connected to each other by the flip-chip side 12a being flip-chip bonded to the stacking side 12b of the other by the conductive components 13, and the lowermost second electronic component 12 is flip-chip bonded to the stacking side 11b of the first electronic component 11 by the conductive components 13 and is electrically connected to the first electronic component 11.

In addition, the entire lower surface (e.g., the flip-chip side 11 a) of each of the first electronic devices 11 and the entire lower surface (e.g., the flip-chip side 12 a) of each of the second electronic devices 12 are used as the first and second layout areas a, a'. For example, the first and second layout areas a, a' are rectangular, such as square, but not particularly limited. Specifically, the first or second layout area a, a 'may define a first section A1 and a second section A2 adjacent to the first section A1 according to requirements, such as a cross-shaped first section A1 shown in fig. 1', or a rectangular first section A1 shown in fig. 1″ as a rectangle.

In addition, a first filling space S1 is formed between the first electronic component 11 and the carrier 10, a second filling space S2 is formed between the first electronic components 11, a third filling space S3 is formed between the first electronic components 11 and the second electronic components 12, and a fourth filling space S4 is formed between the second electronic components 12. It should be understood that the number of the second filling spaces S2 may be as large as desired, such as zero layers (as in the embodiment of the first electronic component 11 shown in fig. 4 or 4'), or multiple layers, and the number of the fourth filling spaces S4 may be as large as desired, such as one or multiple layers, without any particular limitation.

The first coating portion 14 is a primer material in a fluid state, and has a CTE value of about 52 to 109.

In the present embodiment, the first cladding portion 14 is partially disposed on the first and second layout areas a, a'. For example, the first coating portion 14 is disposed only on the first section A1, as shown in fig. 1' or fig. 1″. Specifically, the first cladding portion 14 is partially disposed on each of the layout areas a of the first to fourth filling spaces S1, S2, S3, S4.

In addition, in another embodiment, as shown in fig. 2, 2', 2A and 2A ', the first coating portion 24 may be disposed on the first and second layout areas a, a ' entirely. For example, the first coating portion 24 may be completely disposed on the layout area of at least one of the first to fourth filling spaces S1, S2, S3, S4 (the first filling space S1 shown in fig. 2, the second to fourth filling spaces S2, S3, S4 shown in fig. 2A, or the first and third filling spaces S1, S3 shown in fig. 2A'). It should be appreciated that the first cladding portions 14,24 may be simultaneously partially and completely disposed over different first and/or second disposition areas a, a 'as shown in fig. 3A'.

The second coating portion 15 is a solid filler, such as a non-conductive film (NCF), and has a CTE of about 32 to 98, so that the material of the first coating portion 14 is different from that of the second coating portion 15, for example, the coefficient of thermal expansion of the first coating portion 14 is different from that of the second coating portion 15.

In the present embodiment, the second coating portion 15 is partially disposed on the first and second layout areas a, a'. For example, the second coating portion 15 is disposed only on the second section A2, such as at the corner shown in fig. 1' or on two opposite outer sides as shown in fig. 1″. Specifically, the second cladding portion 15 is partially disposed on each of the layout areas of the first to fourth filling spaces S1, S2, S3, S4. It should be appreciated that the first cladding 14 and the second cladding 15 can be interchangeably laid out in the configuration shown in fig. 1' and 1″.

In addition, in another embodiment, as shown in fig. 2, 2', 2A and 2A ', the second coating portion 25 may be disposed on the first and/or second layout areas a, a ' entirely. For example, the second coating portion 25 may be completely disposed on the layout area of at least one of the first to third filling spaces S1, S2, S3, S4 (the second to third filling spaces S2, S3, S4 shown in fig. 2, the first filling space S1 shown in fig. 2A, or the second and third filling spaces S2, S4 shown in fig. 2A'). It should be appreciated that the second coating 15,25 may be simultaneously partially and completely disposed over different first and/or second routing areas a, a' of the electronic package 3 as shown in fig. 3 or 3A.

Therefore, the layout patterns of the layout areas may be the same (as shown in fig. 1 or 1A) or different (as shown in fig. 1A ', 2', 2A ', 3A or 3A'). It should be understood that, regarding the filling manners of the first to fourth filling spaces S1, S2, S3, S4, the layout patterns of the first and/or second layout areas a, a ' may be configured according to the requirement, for example, the layout patterns are not limited to the patterns of fig. 1 to 3A ' based on the first to fourth filling spaces S1, S2, S3, S4 (such as longitudinal direction) or the first and second sections A1 and A2 (such as transverse direction), which are symmetrical (such as shown in fig. 3 and 3A '), or asymmetrical (such as shown in fig. 3A), staggered (such as shown in fig. 1A ' or 2A ') or non-staggered (such as shown in fig. 3A), regular (such as shown in fig. 1 or 1A) or non-regular (such as shown in fig. 2 or 2A).

In addition, the electronic package 1 defines a stress balance line L according to the overall stress distribution thereof, so as to facilitate adjusting the layout patterns of the first and second layout areas a, a'. For example, the cladding structures 1c of the first to fourth filling spaces S1, S2, S3, S4 are complementary to appropriately control the degree of warpage (warpage) of the electronic package 1, so that the stress balance line L defines the electronic package 1 as a first package module 1a (the lower half as shown in fig. 1) and a second package module 1b (the upper half as shown in fig. 1) adjacent to each other, so that the strain of the first package module 1a (the warpage direction W1 of the convex arc line as shown in fig. 1) and the strain of the second package module 1b (the warpage direction W2 of the concave arc line as shown in fig. 1) are substantially complementary (the warpage directions W1, W2 are opposite to each other), and the stresses of the two are almost mutually eliminated. Specifically, as shown in fig. 1 to 4, the stress balance line L is located at the uppermost first electronic component 11 (or at the lowermost second electronic component 12), so that the first package module 1a includes at least one first electronic component 11, and the second package module 1b includes a plurality of second electronic components 12. It should be understood that the second encapsulation module 1b has to be provided with the second cladding 15 when the first encapsulation module 1a is provided with the first cladding 14, and that the second encapsulation module 1b has to be provided with the first cladding 14 when the first encapsulation module 1a is provided with the second cladding 15. Therefore, the present invention is configured on the first and second package modules 1a,1b according to stress distribution by the first and second coating portions 14,15 of different materials.

In addition, if the first and second coating portions 14,15 are to be disposed in a single disposition region (as shown in fig. 1 'and 1 "), the process may first attach the solid second coating portion 15 to the surface of the first or second electronic component 11,12, so that the second coating portion 15 forms a channel (i.e. the first section A1), and after the first electronic component 11 or the second electronic component 12 is stacked, the fluid first coating portion 14 is filled into one of the four ports of the channel (i.e. the first section A1) in a dispensing manner (i.e. the filling direction F shown in fig. 1'), so that the first coating portion 14 is filled into the filling space corresponding to the first section A1. Specifically, the multi-axial channel shown in fig. 1' is beneficial for the first cladding portion 14 to diffuse and overflow to fill the filling space corresponding to the first section A1 (but the manufacturing is more complicated), while the uni-axial channel shown in fig. 1 "is beneficial for the manufacturing (but it is less easy to fill the filling space).

The packaging layer 16 is made of an insulating material, such as Polyimide (PI), dry film (dry film), a molding compound such as epoxy (epoxy), or a molding compound (molding), and may be formed by lamination (lamination), coating (coating), or molding (molding).

In summary, in the electronic packages 1,2,3,4 of the present invention, the package structure 1c includes two kinds of packages (the first and second packages 14, 15) with different materials to generate different directional strains, so that when the package structure 1c is applied to the electronic packages 1,2,3,4 with multi-layer filling spaces (the first to fourth filling spaces S1, S2, S3, S4), the stress distribution of the electronic packages 1,2,3,4 can be adjusted by the arrangement of the first and second packages 14,15, so that the warpage degree of the electronic packages 1,2,3,4 can be optimally controlled, i.e. the deformation of the electronic packages 1,2,3,4 can be minimized. For example, by means of the thermal expansion coefficient of the first cladding portion 14 being different from the thermal expansion coefficient of the second cladding portion 15, the filling manners of the first to fourth filling spaces S1, S2, S3, S4 can be configured to the layout patterns of the first and second layout areas a, a' to present various arrangements and combinations, so that the stress distribution of the electronic packages 1,2,3,4 can present an equilibrium state.

In addition, by virtue of the uniform stress diffusion property of the solid NCF (the second coating portion 15), the non-uniform stress diffusion of the fluid primer material (the first coating portion 14) is suppressed, so that the stress can be mutually reduced when the solid NCF and the solid NCF are mutually overlapped, and compared with the prior art that the fluid primer material is adopted to coat all the conductive bumps, the coating structure 1c of the present invention can effectively avoid the effect of stress accumulation of the layers (the first filling space S1, the fourth filling space S2, the second filling space S3 and the third filling space S4), namely the stress from the two opposite sides of the stress balance line L can be almost mutually eliminated.

In addition, as shown in fig. 2 and 2', since the thermal expansion coefficient of the first cladding portion 24 is greater than that of the second cladding portion 25, and the solid NCF (second cladding portion 25) has the property of uniformly diffusing stress, the first cladding portion 24 can be disposed in the first and/or second filling spaces S1, S2 (i.e. corresponding to the first layout area a of the first package module 1 a), so that the manufacturing process of the second cladding portion 25 on the upper portion of the electronic package 1,2,3,4 can be performed first, and then the manufacturing process of the first cladding portion 24 on the lower portion can be performed, and at this time, the stress distribution and the warpage degree of the second cladding portion 25 are shaped, so that they are less affected by the high temperature thermal process of the first cladding portion 24. Therefore, when the first cladding portion 24 is subjected to final step filling, the overall stress distribution of the electronic package 2 can be effectively and well controlled. Specifically, after the first cladding portion 24 is filled and solidified, the first cladding portion 24 contracts during cooling, so that the strain direction is pulled back reversely, and the warping degree is reduced, so as to reach the error range of the expected warping degree.

In addition, if the first and second coating portions 14,15 are to be disposed on the single disposition area, a fluid channel is formed by the second coating portion 15 during fabrication, so that the remaining filling space corresponding to the first or second disposition area a, a' can be filled along the channel only by dispensing once during the subsequent dispensing process of the first coating portion 14, thereby accelerating the overall fabrication time.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications to the above would be obvious to those of ordinary skill in the art, without departing from the spirit and scope of the present invention. The scope of the invention is therefore intended to be indicated by the appended claims.