CN114691580B - Integrated circuit, digital circuit module, chip, camera and electronic information device - Google Patents

Embodiments of the present invention provide an integrated circuit, a digital circuit module, a chip, a camera, and an electronic information device. The integrated circuit includes: the digital circuit module comprises an I2C module and a serial bus main module; at least one serial bus slave; at least one analog circuit module; the I2C module is connected with the serial bus main module; the serial bus master module is connected with at least one serial bus slave module through a serial bus; the at least one serial bus slave module is connected with the at least one analog circuit module; the digital circuit module is adapted to receive the analog circuit configuration signal via the I2C module and to output the analog circuit configuration signal to the at least one analog circuit module via the serial bus master module and the at least one serial bus slave module. Compared with the prior art, the technical scheme provided by the embodiment of the invention can not only save the area resource of the chip, but also effectively reduce the signal interference.

Integrated circuit, digital circuit module, chip, camera and electronic information device

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to an integrated circuit, a digital circuit module, a chip, a camera, and an electronic information device.

Background

Typically, some of the digital-to-analog port connection signals inside the chip are analog circuit configuration signals, i.e., non-waveform control signals. The analog circuit configuration signal is first written into the digital circuit area and then connected to the analog circuit area through the direct connection signal line. Inside the chip, the connection of the direct connection signal wires is realized through actual circuit wiring, and hundreds of direct connection signal wires may be needed in number, so that signal interference can be generated, and the area resource of the chip can be consumed greatly.

In addition, for the digital circuit area of the chip, there is a problem that a large amount of wiring resources are consumed due to improper layout, so that the height or width of the chip layout is increased, and further the area resources of the chip are obviously consumed.

Disclosure of Invention

An object of an embodiment of the present invention is to provide an integrated circuit, a digital circuit module, a chip, a camera, and an electronic information device, so as to save area resources of the chip and reduce signal interference.

An integrated circuit provided by an embodiment of the present invention includes: the digital circuit module comprises an I2C module and a serial bus main module; at least one serial bus slave; at least one analog circuit module; the I2C module is connected with the serial bus main module; the serial bus master module is connected with at least one serial bus slave module through a serial bus; the at least one serial bus slave module is connected with the at least one analog circuit module; the digital circuit module is adapted to receive the analog circuit configuration signal via the I2C module and to output the analog circuit configuration signal to the at least one analog circuit module via the serial bus master module and the at least one serial bus slave module.

Optionally, the digital circuit module includes a first digital circuit sub-module, a second digital circuit sub-module, a circuit element at least partially occupying a wiring path between the first digital circuit sub-module and the second digital circuit sub-module, a serial bus master unit, and a serial bus slave unit, wherein one of the first digital circuit sub-module and the second digital circuit sub-module is connected with the serial bus master unit, the other is connected with the serial bus slave unit, and the serial bus master unit is connected with the serial bus slave unit through the serial bus.

Optionally, the serial bus is an SPI serial bus, or a custom serial bus.

Optionally, the analog circuit configuration signal is a digital signal.

Optionally, the I2C module is adapted to parse the analog circuit configuration signal into corresponding address information and data information based on the I2C protocol.

Optionally, the serial bus master module is adapted to encode address information and data information based on a respective serial bus protocol and form a serial bus signal, and to output the serial bus signal to a respective serial bus slave module.

Optionally, the serial bus slave module is adapted to parse the serial bus signal into address information and data information based on a corresponding serial bus protocol.

Optionally, the integrated circuit comprises: the register is respectively corresponding to each serial bus slave module and is suitable for latching the data information analyzed by the serial bus slave modules and outputting the data information to the corresponding analog circuit modules through the direct connection signal lines.

The digital circuit module comprises a first digital circuit sub-module, a second digital circuit sub-module, a circuit element at least partially occupying a wiring path between the first digital circuit sub-module and the second digital circuit sub-module, a serial bus main unit and a serial bus slave unit, wherein one of the first digital circuit sub-module and the second digital circuit sub-module is connected with the serial bus main unit, the other is connected with the serial bus slave unit, and the serial bus main unit is connected with the serial bus slave unit through a serial bus.

A chip for an image sensor provided by an embodiment of the present invention includes an integrated circuit and/or a digital circuit module provided by an embodiment of the present invention.

The embodiment of the invention provides a camera which comprises an integrated circuit and/or a digital circuit module.

An electronic information device provided by an embodiment of the present invention includes an integrated circuit and/or a digital circuit module provided by an embodiment of the present invention.

The technical scheme provided by the embodiment of the invention is suitable for any two or more circuit modules which need communication connection but have occupied wiring paths or hope to reduce wiring resources so as to save the chip area.

Compared with the prior art, the technical scheme of the embodiment of the invention has the beneficial effects. For example, a serial bus is used to connect the digital circuit module and the analog circuit module, so that the number of signal lines between the digital circuit module and the analog circuit module is greatly reduced.

For another example, since the number of signal lines between the digital circuit module and the analog circuit module is greatly reduced, the area resources of the chip can be effectively saved and the signal interference can be reduced.

For another example, using a serial bus to connect different ones of the digital circuit modules may enable a significant reduction in the number of signal lines between the different digital circuit sub-modules.

For another example, the number of signal lines between different digital circuit sub-modules is greatly reduced, so that the area resource of the chip can be effectively saved.

Drawings

FIG. 1 is a schematic diagram of an integrated circuit in an embodiment of the invention;

FIG. 2 is a partial schematic diagram of the integrated circuit shown in FIG. 1;

FIG. 3 is a schematic diagram of a digital circuit module in an embodiment of the invention;

Fig. 4 is a partial schematic diagram of a chip for an image sensor in an embodiment of the invention.

Detailed Description

In order to make the objects, features and advantages of the embodiments of the present invention more comprehensible, the following detailed description of specific embodiments of the present invention with reference to the accompanying drawings is provided.

Referring to fig. 1, an integrated circuit 100 provided by an embodiment of the present invention includes a digital circuit module 110, at least one analog circuit module 120, an I2C module 130, a serial bus master module 140, and at least one serial bus slave module 150.

Specifically, the I2C module 130 is disposed within the digital circuit module 110 and is adapted to receive an analog circuit configuration signal for configuring at least one analog circuit module 120. The serial bus master module 140 is also arranged within the digital circuit module 110 and is connected, on the one hand, to the I2C module 130 located within the digital circuit module 110 and, on the other hand, to at least one serial bus slave module 150 located outside the digital circuit module 110 via a serial bus 160. The at least one serial bus slave module 150 is connected to the at least one analog circuit module 120 in a one-to-one correspondence manner through a plurality of direct connection signal lines 170, respectively.

In some embodiments, the integrated circuit 100 may include three analog circuit modules 120, and the three analog circuit modules 120 may be located on the upper, left, and right sides of the digital circuit module 110, respectively. Accordingly, three serial bus slave modules 150 are also provided, and the three serial bus slave modules 150 may be respectively located between the digital circuit module 110 and the upper analog circuit module 120, between the digital circuit module 110 and the left analog circuit module 120, and between the digital circuit module 110 and the right analog circuit module 120. Meanwhile, each serial bus slave module 150 is correspondingly connected with one analog circuit module 120 through a plurality of direct connection signal lines 170.

The serial bus master module 140 is connected to the three serial bus slave modules 150 in a one-to-one correspondence through one serial bus 160. Specifically, three serial buses 160 may be provided, and the three serial buses 160 are located at the upper, left, and right sides of the digital circuit module 110, respectively. The serial bus 160 on the upper side is connected to the serial bus master module 140 and the serial bus slave module 150 on the upper side, the serial bus 160 on the left side is connected to the serial bus master module 140 and the serial bus slave module 150 on the left side, and the serial bus 160 on the right side is connected to the serial bus master module 140 and the serial bus slave module 150 on the right side.

In a specific implementation, the analog circuit configuration signal is a digital control signal that controls the operation of the corresponding analog circuit module 120, and its set value is not changed in a fixed application scenario.

In an embodiment of the present invention, the analog circuit configuration signal received by the I2C module 130 may be sequentially output from the module 150 to the corresponding analog circuit module 120 through the serial bus main module 140 and the corresponding serial bus, so as to control the operation of the analog circuit module 120.

In a specific implementation, the I2C module 130 is further adapted to parse the analog circuit configuration signals received by it into corresponding address information and data information based on the I2C protocol, and output the address information and data information to the serial bus master module 140.

The serial bus master module 140 is adapted to encode the received address information and data information based on a corresponding serial bus protocol to form a corresponding serial bus signal and output the serial bus signal to the corresponding serial bus slave module 150 via the serial bus 160.

The serial bus slave module 150 is adapted to parse the received serial bus signal into address information and data information based on the corresponding serial bus protocol.

In some embodiments, the serial bus 160 may be an I2C serial bus, a UART serial bus, or a USB serial bus.

In other preferred embodiments, serial bus 160 may also be an SPI serial bus, or a custom serial bus.

Referring to fig. 2, when the serial bus 160 employs an SPI serial bus, it may include four signal lines, namely an SPI-SCK signal line, an SPI-SDI signal line, an SPI-SDO signal line, and an SPI-SSN signal line, respectively. The SPI-SDI signal line is adapted to receive a signal output from the serial bus slave module 150 and output it to the serial bus master module 140. The SPI-SDO signal line is adapted to receive the signal output by the serial bus master module 140 and output it to the serial bus slave module 150. The SPI-SCK signal line is adapted to receive the clock signal generated by the serial bus master module 140 and output it to the serial bus slave module 150. The SPI-SSN signal lines are adapted to receive chip select signals generated by the serial bus master module 140 to select the corresponding serial bus slave module 150 to communicate with the serial bus master module 140.

Referring to fig. 1 and 2, in some embodiments, the integrated circuit 100 may further include a register 180 provided respectively corresponding to each of the serial bus slave modules 150.

In a specific implementation, the serial bus slave module 150 is adapted to parse the received serial bus signal into address information and data information based on a corresponding serial bus protocol. Wherein the address signals are used to point to the corresponding registers 180. The register 180 is adapted to latch data information associated with address information directed thereto parsed from the module 150 by the serial bus and output the data information to the corresponding analog circuit module 120 through the direct signal line 170.

In the embodiment of the present invention, the data information parsed from the serial bus slave module 150 is latched into the register 180, so that the stability and reliability in the data information transmission process can be ensured.

Specifically, a plurality of registers 180 for storing different data information, respectively, may be provided for each serial bus slave 150, respectively. For example, when the analog circuit configuration signal is rsell _r [4:0], its bit width is 5, requiring 5 registers 180 storing 1-bit wide data.

Referring to fig. 1 and 2, each serial bus slave module 150 is connected to one analog circuit module 120 through a plurality of direct signal lines 170.

In some embodiments, one serial bus slave module 150 may be connected to a corresponding analog circuit module 120 through i direct-connect signal lines 170. Wherein at least one of the direct-connect signal lines 170 is adapted to simultaneously transmit the same data information. That is, the same data information needs at least one direct signal line 170 to be transmitted. For example, when the analog circuit configuration signal is rsell _r4:0, the bit width is 5, and 5 direct signal lines 170 are required to transmit the data information together.

Referring to fig. 3, in an embodiment of the present invention, the digital circuit module 110 may further include a first digital circuit sub-module 111, a second digital circuit sub-module 112, and a circuit element 113.

In a specific implementation, a communication connection is required between the first digital circuit sub-module 111 and the second digital circuit sub-module 112, while the circuit element 113 is located between the first digital circuit sub-module 111 and the second digital circuit sub-module 112 and occupies at least partially a wiring path between the first digital circuit sub-module 111 and the second digital circuit sub-module 112.

Although such a layout is common in chip design. But if a direct signal line connection is adopted between the first digital circuit sub-module 111 and the second digital circuit sub-module 112, it is necessary to increase the height or width of the chip so as to have a sufficient area for wiring.

In this regard, in the embodiment of the present invention, the serial bus 160 is used to connect the first digital circuit sub-module 111 and the second digital circuit sub-module 112, so as to reduce the number of wires and save the wire resources, thereby saving the area resources of the chip.

Specifically, the digital circuit module 110 further includes a serial bus master 114 and a serial bus slave 115.

In an implementation, one of the first digital circuit sub-module 111 and the second digital circuit sub-module 112 is connected to the serial bus master unit 114 through a direct signal line 170, the other is connected to the serial bus slave unit 115 through a direct signal line 170, and the serial bus master unit 114 is connected to the serial bus slave unit 115 through a serial bus 160.

The serial bus master 114 is adapted to receive a direct signal output by one of the first digital circuit sub-module 111 and the second digital circuit sub-module 112 via the direct signal line 170 and to encode the received direct signal based on a respective serial bus protocol to form a respective serial bus signal, which is in turn output to the respective serial bus slave 115 via the serial bus 160.

The serial bus slave unit 115 is adapted to receive the serial bus signal output by the serial bus master unit 114 and to parse the received serial bus signal into a corresponding direct signal based on a corresponding serial bus protocol, and to output the direct signal to the other of the first digital circuit sub-module 111 and the second digital circuit sub-module 112 via the direct signal line 170.

In some embodiments, the serial bus 160 may be an I2C serial bus, a UART serial bus, or a USB serial bus.

In other preferred embodiments, serial bus 160 may also be an SPI serial bus, or a custom serial bus.

Referring to fig. 4, an embodiment of the present invention also provides a chip 10 for an image sensor. The chip 10 includes a pixel module 200 and an integrated circuit 100 and/or a digital circuit module 110 provided by embodiments of the present invention.

In some embodiments, the digital circuit block 110, the analog circuit block 120, and the serial bus slave block 150 in the integrated circuit 100 may be disposed along the periphery of the pixel block 200. In this way, the area resources of the chip 10 can be effectively utilized.

The embodiment of the invention also provides a camera. The camera includes an integrated circuit 100 and/or a digital circuit module 110 provided by embodiments of the present invention.

The embodiment of the invention also provides an electronic information device. The electronic information device includes integrated circuit 100 and/or digital circuit module 110 provided by embodiments of the present invention.

In some embodiments, the electronic information device may be a digital camera, an image input camera, a scanner, a facsimile machine, a Personal Digital Assistant (PDA), a camera-equipped communication device, or a video communication device.

Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the disclosure, even where only a single embodiment is described with respect to a particular feature. The characteristic examples provided in the present disclosure are intended to be illustrative, not limiting, unless stated differently. In practice, the features of one or more of the dependent claims may be combined with the features of the independent claims where technically possible, according to the actual needs, and the features from the respective independent claims may be combined in any appropriate way, not merely by the specific combinations enumerated in the claims.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.