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CN114695301A - Semiconductor package having thin substrate and method of manufacturing the same - Google Patents

  • ️Fri Jul 01 2022

CN114695301A - Semiconductor package having thin substrate and method of manufacturing the same - Google Patents

Semiconductor package having thin substrate and method of manufacturing the same Download PDF

Info

Publication number
CN114695301A
CN114695301A CN202111585362.8A CN202111585362A CN114695301A CN 114695301 A CN114695301 A CN 114695301A CN 202111585362 A CN202111585362 A CN 202111585362A CN 114695301 A CN114695301 A CN 114695301A Authority
CN
China
Prior art keywords
front surface
metal layer
layer
rigid support
semiconductor substrate
Prior art date
2020-12-30
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111585362.8A
Other languages
Chinese (zh)
Inventor
鲁军
王隆庆
马督儿·博德
陈波
周曙华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alpha and Omega Semiconductor Cayman Ltd
Original Assignee
Alpha and Omega Semiconductor Cayman Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
2020-12-30
Filing date
2021-12-22
Publication date
2022-07-01
2020-12-30 Priority claimed from US17/137,893 external-priority patent/US11495548B2/en
2021-12-22 Application filed by Alpha and Omega Semiconductor Cayman Ltd filed Critical Alpha and Omega Semiconductor Cayman Ltd
2022-07-01 Publication of CN114695301A publication Critical patent/CN114695301A/en
Status Pending legal-status Critical Current

Links

  • 239000004065 semiconductor Substances 0.000 title claims abstract description 113
  • 239000000758 substrate Substances 0.000 title claims abstract description 68
  • 238000004519 manufacturing process Methods 0.000 title description 5
  • 239000010410 layer Substances 0.000 claims abstract description 134
  • 229910052751 metal Inorganic materials 0.000 claims abstract description 80
  • 239000002184 metal Substances 0.000 claims abstract description 80
  • 239000012790 adhesive layer Substances 0.000 claims abstract description 30
  • 238000000034 method Methods 0.000 claims abstract description 23
  • 238000000926 separation method Methods 0.000 claims abstract description 4
  • 235000012431 wafers Nutrition 0.000 claims description 25
  • 239000000463 material Substances 0.000 claims description 22
  • PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
  • 239000002210 silicon-based material Substances 0.000 claims description 11
  • XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
  • 229910052710 silicon Inorganic materials 0.000 claims description 10
  • 239000010703 silicon Substances 0.000 claims description 10
  • 229910052759 nickel Inorganic materials 0.000 claims description 9
  • 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
  • RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
  • 230000005669 field effect Effects 0.000 claims description 5
  • 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
  • 229910052719 titanium Inorganic materials 0.000 claims description 5
  • 239000010936 titanium Substances 0.000 claims description 5
  • 239000000853 adhesive Substances 0.000 claims description 4
  • 230000001070 adhesive effect Effects 0.000 claims description 4
  • 229910052782 aluminium Inorganic materials 0.000 claims description 4
  • XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
  • 239000011521 glass Substances 0.000 claims description 4
  • 229910044991 metal oxide Inorganic materials 0.000 claims description 4
  • 150000004706 metal oxides Chemical class 0.000 claims description 4
  • BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
  • PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
  • 229910052737 gold Inorganic materials 0.000 claims description 3
  • 239000010931 gold Substances 0.000 claims description 3
  • 229910052709 silver Inorganic materials 0.000 claims description 3
  • 239000004332 silver Substances 0.000 claims description 3
  • 229920005591 polysilicon Polymers 0.000 claims description 2
  • 230000007423 decrease Effects 0.000 description 4
  • VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
  • 238000012986 modification Methods 0.000 description 3
  • 230000004048 modification Effects 0.000 description 3
  • RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
  • 229910000831 Steel Inorganic materials 0.000 description 2
  • 239000011248 coating agent Substances 0.000 description 2
  • 238000000576 coating method Methods 0.000 description 2
  • 229910052802 copper Inorganic materials 0.000 description 2
  • 239000010949 copper Substances 0.000 description 2
  • 230000001681 protective effect Effects 0.000 description 2
  • 229910000679 solder Inorganic materials 0.000 description 2
  • 239000010959 steel Substances 0.000 description 2
  • 239000004642 Polyimide Substances 0.000 description 1
  • 229910052681 coesite Inorganic materials 0.000 description 1
  • 229910052906 cristobalite Inorganic materials 0.000 description 1
  • 238000005520 cutting process Methods 0.000 description 1
  • 230000000694 effects Effects 0.000 description 1
  • 238000005530 etching Methods 0.000 description 1
  • 238000003698 laser cutting Methods 0.000 description 1
  • 238000002161 passivation Methods 0.000 description 1
  • 238000007517 polishing process Methods 0.000 description 1
  • 229920001721 polyimide Polymers 0.000 description 1
  • 239000002861 polymer material Substances 0.000 description 1
  • 239000000377 silicon dioxide Substances 0.000 description 1
  • 229910052682 stishovite Inorganic materials 0.000 description 1
  • 229910052905 tridymite Inorganic materials 0.000 description 1

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A semiconductor package includes a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid support layer, and a plurality of contact pads. The thickness of the semiconductor substrate is equal to or less than 50 micrometers. The thickness of the rigid support layer is greater than the thickness of the semiconductor substrate. The thickness of the second metal layer is greater than the thickness of the first metal layer. One method includes the steps of: preparing a device wafer; preparing a support wafer; connecting the support wafer to the device die through the adhesive layer; and applying a separation process to form a plurality of semiconductor packages.

Description

Semiconductor package having thin substrate and method of manufacturing the same

Technical Field

The present invention relates generally to semiconductor packages having thin semiconductor substrates and methods of manufacturing a plurality of semiconductor packages. More particularly, the present invention relates to a semiconductor package that operates with a sufficient margin of safety, having a substrate thickness in the range of 25 microns to 75 microns.

Background

Such as common drain Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Chip Scale Packages (CSPs) and semiconductor power packages for battery protection applications, which typically have a semiconductor substrate thickness of 100 microns or more. The semiconductor substrate provides a large amount of dc resistance. It is advantageous to reduce the thickness of the semiconductor substrate to less than 50 microns, thereby reducing the dc resistance and improving the electrical performance.

The semiconductor substrate provides a large amount of Direct Current (DC) resistance. It is highly advantageous to reduce the thickness of the semiconductor substrate to improve electrical performance. For example, when the thickness of the semiconductor substrate is reduced from 50 micrometers to 25 micrometers, the on-resistance may be reduced by 24%. As the semiconductor substrate thickness decreases, the mechanical strength of the semiconductor package decreases. In an example of the invention, a rigid support layer connected to a metal layer with a young's modulus of 150 gigapascals is added to increase the mechanical strength. Increasing the thickness of the attached metal layer may further slightly decrease the on-resistance (less sensitive than the effect of changing the thickness of the semiconductor substrate). For example, when the thickness of the attached metal layer is increased from 15 microns to 50 microns, the on-resistance may decrease by 5%.

Disclosure of Invention

A semiconductor package includes a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid support layer, and a plurality of contact pads. The thickness of the semiconductor substrate is equal to or less than 75 micrometers. The thickness of the rigid support layer is greater than the thickness of the semiconductor substrate. The thickness of the second metal layer is greater than the thickness of the first metal layer.

A method for manufacturing a plurality of semiconductor packages is disclosed. The method comprises the following steps: preparing a device wafer; providing a support wafer; connecting the support die to the device wafer through an adhesive layer; and applying a separation process.

Drawings

Fig. 1 illustrates a cross-sectional view of a conventional semiconductor package.

Fig. 2 illustrates a cross-sectional view of another conventional semiconductor package.

Fig. 3 shows a cross-sectional view of a semiconductor package having a thin substrate in an example of the invention.

Fig. 4 shows a flow chart for preparing a plurality of semiconductor packages in an example of the present invention.

Fig. 5A-5D illustrate cross-sectional views of corresponding steps of the process of fig. 4 in an example of the invention.

Detailed Description

Fig. 1 illustrates a cross-sectional view of a

conventional semiconductor package

100. The

conventional semiconductor package

100 includes a plurality of

contact pads

102, a

semiconductor substrate

120, a

metal layer

140, and a

coating

190. In one example,

substrate

120 is 100 microns thick. The

coating

190 does not provide sufficient mechanical strength support for the package. Warpage occurs during reflow of surface mount solder.

Fig. 2 shows a cross-sectional view of a

conventional semiconductor package

200. The

conventional semiconductor package

200 includes a plurality of

contact pads

202, a

semiconductor substrate

220, a

metal layer

240, and a

protective tape

294. In one example, the

semiconductor substrate

220 is 100 microns thick. The

protective tape

294 cannot provide sufficient mechanical strength support for the package. Warpage can occur during surface mount solder reflow.

Fig. 3A and 3B of U.S. patent application publication No. 2019/0189569 illustrate a semiconductor package that includes a semiconductor substrate, a metal layer, an adhesive layer, a rigid support layer, and a plurality of contact pads. Without the additional metal layer attached to the rigid support layer, the safety factor involved in the mechanical performance requirements of the semiconductor package is not high when the thickness of the semiconductor substrate is reduced to the 50 micron range.

Fig. 3 illustrates a cross-sectional view of a

semiconductor package

300 in an example of the invention. The

semiconductor package

300 includes a

semiconductor substrate

320, a

first metal layer

340, an

adhesive layer

360, a

second metal layer

370, a

rigid support layer

380, and a plurality of

contact pads

302.

The

semiconductor substrate

320 has a

front surface

322 and a

back surface

324. The

rear surface

324 is opposite the

front surface

322.

First metal layer

340 has a

front surface

342 and a

back surface

344. The

rear surface

344 is opposite the

front surface

342. The

adhesive layer

360 has a

front surface

362 and a

back surface

364. The

rear surface

364 is opposite the

front surface

362.

Second metal layer

370 has a

front surface

372 and a

back surface

374. The

rear surface

374 is opposite the

front surface

372. The

rigid support layer

380 has a

front surface

382 and a

rear surface

384. The

rear surface

384 opposes the

front surface

382.

In an example of the present invention,

front surface

342 of

first metal layer

340 is directly connected to

back surface

324 of

semiconductor substrate

320. The

front surface

362 of the

adhesive layer

360 is directly connected to the

back surface

344 of the

first metal layer

340. The

front surface

372 of the

second metal layer

370 is directly connected to the 364 of the back surface

adhesive layer

360. The

front surface

382 of the

rigid support layer

380 is directly connected to the

back surface

374 of the

second metal layer

370. In one example, a plurality of

contact pads

302 are connected to the

front surface

322 of the

semiconductor substrate

320. In another example, the plurality of

contact pads

302 are directly connected to the

front surface

322 of the

semiconductor substrate

320.

In one example, the thickness of the

semiconductor substrate

320 is equal to or less than 50 microns. In another example, the thickness of the

semiconductor substrate

320 is in a range of 25 microns to 35 microns. In an example of the present invention, the thickness of the

second metal layer

370 is in a range of 30 micrometers to 100 micrometers.

Second metal layer

370 provides an electrical path to reduce the on-resistance of the device. The thickness of the

first metal layer

340 is in the range of 1 to 5 micrometers. The thickness of

first metal layer

340 is less than the thickness of

semiconductor substrate

320 in order to reduce overall warpage of the semiconductor package during manufacturing. The thickness of

second metal layer

370 is greater than the thickness of

first metal layer

340. In one example, the edge surfaces of the

semiconductor substrate

320, the

second metal layer

370, and the

rigid support layer

380 are aligned and coplanar, respectively, on all sides. In another example, the edge surfaces of the

semiconductor substrate

320, the

first metal layer

340, the

second metal layer

370, and the

rigid support layer

380 are aligned and coplanar, respectively, on all sides. In another example, the edge surfaces of the

semiconductor substrate

320, the

first metal layer

340, the

adhesive layer

360, the

second metal layer

370, and the

rigid support layer

380 are aligned and coplanar, respectively, on all sides.

In an example of the present invention, the thickness of the support layer is 380 to 150 micrometers. The term "rigid" of the

rigid support layer

380 refers to a material (e.g., a polyimide material or a polymer material) of the

rigid support layer

380 that is stiffer than the tape material. The thinner the

semiconductor substrate

320, the better the electrical performance of each of the plurality of semiconductor packages. It is highly advantageous that the thickness of the

semiconductor substrate

320 is less than 50 microns. The strength requirements of the

rigid support layer

380 are higher if a safety factor is included in the mechanical performance requirements of the semiconductor package.

In an example of the present invention, the thickness is measured in a direction parallel to the Z-axis of fig. 3. In an example of the invention, the thickness of the

rigid support layer

380 is the shortest distance between the

front surface

382 and the

back surface

384. In an example of the present invention, the

semiconductor substrate

320 includes a silicon material. In the examples of the present invention, it is preferable that the semiconductor package (having a planar size of 3.05mm × 1.77 mm) can withstand 5 newtons or more without breaking.

In an example of the present invention, the

adhesive layer

360 includes a conductive adhesive.

Rigid support layer

380 is non-conductive. Current flows from a first contact pad of the plurality of

contact pads

302, through the

semiconductor substrate

320, the

first metal layer

340, the

adhesive layer

360, the

second metal layer

370, the

adhesive layer

360, the

first metal layer

340, and the

semiconductor substrate

320, to a second contact pad of the plurality of

contact pads

302.

In an example of the present invention, the

semiconductor package

300 is a common drain Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Chip Scale Package (CSP) for battery protection applications. Two gates and two sources are located on the front surface of the common drain MOSFET CSP. The common drain is located on the back side of the common drain MOSFET CSP.

In an example of the present invention, the entirety of

rigid support layer

380 is made of a material having a relatively high young's modulus, including a single crystal silicon material, a polysilicon material, or a glass material. In an example of the present invention, the entirety of

rigid support layer

380 is made of a material having a high Young's modulus, including a silicon material, a glass material, or a silica glass material(SiO2). The advantage is cost effective and lighter semiconductor package weight. In an example of the present invention, the Young's modulus of the entire

rigid support layer

380 is in the range of 50% to 150% of the Young's modulus of the

semiconductor substrate

320. The Coefficient of Thermal Expansion (CTE) of the entire

rigid support layer

380 is in the range of 50% to 250% of the CTE of the

semiconductor substrate

320.

In an example of the invention, the entirety of the rigid support layer is made of a single-crystal silicon material or a polycrystalline silicon material made from recycled silicon wafers. The advantage of using recycled silicon wafers is cost reduction. The recycled silicon wafer is a used silicon wafer or a regenerated silicon wafer. In one example, the silicon wafer used may have been previously used for testing purposes. The etching process and the polishing process are applied to the recycled silicon wafer. The entire

first metal layer

340 is made of a material selected from the group consisting of aluminum, nickel, and gold. The entire

second metal layer

370 is made of a material selected from the group consisting of titanium, nickel, and silver.

Fig. 4 shows a flow chart of a

process

400 for preparing a plurality of semiconductor packages in an example of the invention. Fig. 5A-5D show cross-sectional views of corresponding steps.

Process

400 may begin at

block

402.

In

block

402, referring now to fig. 5A, a

device wafer

502 is prepared. The

device wafer

502 may be a 4 inch, 6 inch, 8 inch, 12 inch, or 18 inch diameter wafer.

Device wafer

502 includes a

semiconductor substrate

520, a

first metal layer

540, and a plurality of

contact pads

512.

Device wafer

502 may also include passivation layer 514 (shown in phantom). Similar to fig. 3A of U.S. patent application publication No. 2019/0189569, each of the plurality of

contact pads

512 may include a layer of aluminum and a layer of nickel. In one example,

first metal layer

540 is deposited directly on

semiconductor substrate

520.

The

semiconductor substrate

520 has a

front surface

522 and a

back surface

524 opposite the

front surface

522 of the

semiconductor substrate

520.

First metal layer

540 has a

front surface

542 and a

back surface

544 opposite

front surface

542 of

first metal layer

540. The

front surface

542 of the

first metal layer

540 is in direct contact with the

back surface

524 of the

semiconductor substrate

520. A plurality of

contact pads

512 are connected to the

front surface

522 of the

semiconductor substrate

520.

In an example of the present invention, the thickness of the

semiconductor substrate

520 is equal to or less than 50 micrometers. The thickness of the

semiconductor substrate

520 is in the range of 25 microns to 35 microns.

Block

402 may be followed by

block

404.

In

block

404, referring now to fig. 5B, a

support wafer

504 is prepared. The

support wafer

504 includes a

second metal layer

570 and a

rigid support layer

580. The

second metal layer

570 has a

front face

572 opposite the

front face

572 of the

second metal layer

570 and a

back face

574. The

rigid support layer

580 has a

front surface

582 opposite the

front surface

582 of the

second metal layer

570 and a

back surface

584 opposite the

front surface

582 of the

second metal layer

570. The

front surface

582 of the

rigid support layer

580 is directly connected to the

back surface

574 of the

second metal layer

570.

In an example of the present invention, the thickness of the

rigid support layer

580 is greater than the thickness of the

semiconductor substrate

520. The

rigid support layer

580 is stiffer than the tape material. The thickness of the

second metal layer

570 is greater than the thickness of the

first metal layer

540. The

rigid support layer

580 is not electrically conductive. The entirety of the

rigid support layer

580 is made of a single crystal silicon material or a polycrystalline silicon material manufactured from a recycled silicon wafer. The entire

first metal layer

540 is made of a material selected from the group consisting of nickel, copper, titanium, and steel. The entire

second metal layer

570 is made of a material selected from the group consisting of nickel, copper, titanium, and steel.

Block

404 may be followed by

block

406.

In

block

406, referring now to fig. 5C, the support die 504 is attached to the

device wafer

502 by an

adhesive layer

560. The

adhesive layer

560 has a

front surface

562 and a

back surface

564 opposite the

front surface

562 of the

adhesive layer

560. The

front surface

562 of the

adhesive layer

560 is directly connected to the

back surface

544 of the

first metal layer

540. The

front surface

562 the

face

572 of the

second metal layer

570 is directly attached to the

back surface

564 of the

adhesive layer

560.

In an example of the present invention, the

adhesive layer

560 includes a conductive adhesive.

Block

406 may be followed by

block

408.

In

block

408, referring now to fig. 5D, a singulation process is provided to form a plurality of semiconductor packages 599. In one example, the singulation process is a laser cutting process. In another example, the separation process is a sawing process. The first and

second packages

581 and 583 are separated from the cutting process. Although only two packages are shown in fig. 5D for simplicity, the total number of packages manufactured from the wafer may vary. In an example of the invention, each of the plurality of

semiconductor packages

599 is a common drain Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Chip Scale Package (CSP) for battery protection applications.

One of ordinary skill in the art will recognize that modifications to the disclosed embodiments are possible. For example, the total number of the plurality of

contact pads

302 may vary. Other modifications may occur to those skilled in the art and all such modifications are considered to be within the scope of the present invention as defined by the claims.

Claims (20)

1. A semiconductor package, comprising:

a semiconductor substrate having a front surface and a back surface opposite the front surface of the semiconductor substrate;

a first metal layer having a front surface and a back surface opposite the front surface of the first metal layer, the front surface of the first metal layer being directly connected to the back surface of the semiconductor substrate;

an adhesive layer having a back surface with a front surface opposite the front surface of the adhesive layer, the front surface of the adhesive layer being directly attached to the back surface of the first metal layer;

a second metal layer having a front surface and a back surface opposite the front surface of the second metal layer, the front surface of the second metal layer being directly connected to the back surface of the adhesive layer;

a rigid support layer having a front surface and a back surface opposite the front surface of the rigid support layer, the front surface of the rigid support layer being directly attached to the back surface of the second metal layer; and

a plurality of contact pads connected to the front surface of the semiconductor substrate;

wherein the thickness of the semiconductor substrate is equal to or less than 75 microns;

wherein the thickness of the rigid support layer is greater than the thickness of the semiconductor substrate; and is

Wherein the rigid support layer is harder than the polymeric material.

2. The semiconductor package of claim 1, wherein the first metal layer has a thickness in a range from 1 micron to 5 microns.

3. The semiconductor package of claim 1, wherein the second metal layer has a thickness in a range from 30 microns to 100 microns.

4. The semiconductor package of claim 1, wherein the rigid support layer has a thickness in a range from 75 microns to 500 microns.

5. The semiconductor package of claim 1, wherein the adhesive layer is comprised of a conductive adhesive.

6. The semiconductor package of claim 1, wherein the semiconductor package is a common-drain metal-oxide-semiconductor field-effect transistor (MOSFET) Chip Scale Package (CSP) for battery protection applications;

wherein the two gates and the two sources are on the front surface of the common drain MOSFET CSP; and is

With the common drain on the back surface of the common drain MOSFET CSP.

7. The semiconductor package of claim 1, wherein the young's modulus of the entire rigid support layer is in the range of 50% to 150% of the young's modulus of the semiconductor substrate; and wherein the Coefficient of Thermal Expansion (CTE) of the entire rigid support layer is in the range of 50% to 250% of the CTE of the semiconductor substrate.

8. The semiconductor package of claim 1, wherein the entire rigid support layer is made of a single crystal silicon material or a polycrystalline silicon material made from recycled silicon wafers.

9. The semiconductor package of claim 1 wherein the entire rigid support layer is made of an amorphous glass material.

10. The semiconductor package of claim 1, wherein the entire first metal layer is made of a material selected from the group consisting of aluminum, nickel, and gold; wherein the entire second metal layer is made of a material selected from the group consisting of titanium, nickel and silver.

11. A method of preparing a plurality of semiconductor packages, the method comprising the steps of:

preparing a device wafer comprising:

a semiconductor substrate having a front surface and a back surface opposite the front surface of the semiconductor substrate; a first metal layer having a front surface and a back surface opposite the front surface of the first metal layer, the front surface of the first metal layer being directly connected to the back surface of the semiconductor substrate; and

a plurality of contact pads connected to the front surface of the semiconductor substrate;

preparing a support wafer comprising

A second metal layer having a front surface and a back surface opposite the front surface of the second metal layer; and

a rigid support layer having a front surface and a back surface opposite the front surface of the rigid support layer, the front surface of the rigid support layer being directly attached to the back surface of the second metal layer;

attaching a support die to the device wafer via an adhesive layer, the adhesive layer having a front surface and a back surface opposite the front surface of the adhesive layer, the front surface of the adhesive layer being directly attached to the back surface of the first metal layer and the front surface of the second metal layer being directly attached to the back surface of the adhesive layer; and is

Applying a separation process;

wherein the semiconductor substrate has a thickness of 75 microns or less;

wherein the thickness of the rigid support layer is greater than the thickness of the semiconductor substrate; and

wherein the rigid support layer is harder than the polysilicon material.

12. The method of claim 11, wherein the first metal layer has a thickness in a range from 1 micron to 5 microns.

13. The method of claim 11, wherein the second metal layer has a thickness in a range of 30 microns to 100 microns.

14. The method of claim 11, wherein the rigid support layer has a thickness in a range of 75 microns to 500 microns.

15. The method of claim 11, wherein the adhesive layer is made of a conductive adhesive.

16. The method of claim 11, wherein each of the plurality of semiconductor packages is a common drain Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Chip Scale Package (CSP) for battery protection applications;

wherein the two gates and the two sources are on a front surface of the common drain MOSFET CSP; and is

One of the common drains is on a rear surface of the common drain MOSFET CSP.

17. The method of claim 11, wherein the young's modulus of the entire rigid support layer is in the range of 50% to 150% of the young's modulus of the semiconductor substrate; wherein the Coefficient of Thermal Expansion (CTE) of the entire rigid support layer is in the range of 50% to 250% of the CTE of the semiconductor substrate.

18. The method of claim 11, wherein the entirety of the rigid support layer is made of a single crystal silicon material or a polycrystalline silicon material made from recycled silicon wafers.

19. The method of claim 11, wherein the entire rigid support layer is made of an amorphous glass material.

20. The method of claim 11, wherein the entire first metal layer is made of a material selected from the group consisting of aluminum, nickel, and gold; wherein

The entire second metal layer is made of a material selected from the group consisting of titanium, nickel and silver.

CN202111585362.8A 2020-12-30 2021-12-22 Semiconductor package having thin substrate and method of manufacturing the same Pending CN114695301A (en)

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US9831115B2 (en) * 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
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