CN115039227A - Imaging elements and semiconductor chips - Google Patents

具体实施方式Detailed ways

在下文中，将说明用于实施本技术的方式(以下称为“实施方案”)。Hereinafter, means for implementing the present technology (hereinafter referred to as "embodiments") will be described.

由于本技术能够应用于成像装置，因此这里将以本技术应用于成像装置的情况为例进行说明。另外，尽管在下文中将以成像装置为例进行说明，但是本技术不限于成像装置的应用，并且能够应用于使用成像装置作为摄像单元(光电转换单元)的所有电子设备，例如，诸如数码相机和摄像机等成像装置、诸如移动电话等具有成像功能的移动终端装置以及使用成像装置作为图像读取单元的复印机。此外，还存在安装在电子设备中的模块类型的形式，即相机模块用作成像装置的情况。Since the present technology can be applied to an imaging device, a case where the present technology is applied to an imaging device will be described here as an example. In addition, although an imaging device will be described below as an example, the present technology is not limited to the application of the imaging device, and can be applied to all electronic apparatuses using the imaging device as an imaging unit (photoelectric conversion unit), such as, for example, digital cameras and An imaging device such as a video camera, a mobile terminal device having an imaging function such as a mobile phone, and a copier using the imaging device as an image reading unit. In addition, there is also a form of a module type installed in an electronic device, that is, a case where a camera module is used as an imaging device.

图1是示出作为根据本公开的电子设备的示例的成像装置的构成例的框图。如图1所示，成像装置10具有包括透镜组11等的光学系统、成像元件12、作为相机信号处理单元的DSP电路13、帧存储器14、显示单元15、记录单元16、操作系统17和电源系统18等。FIG. 1 is a block diagram showing a configuration example of an imaging apparatus as an example of an electronic apparatus according to the present disclosure. As shown in FIG. 1, the imaging device 10 has an optical system including a lens group 11 and the like, an imaging element 12, a DSP circuit 13 as a camera signal processing unit, a frame memory 14, a display unit 15, a recording unit 16, an operating system 17, and a power supply System 18 et al.

另外，DSP电路13、帧存储器14、显示单元15、记录单元16、操作系统17和电源系统18被构造成经由总线19彼此连接。CPU 20控制成像装置10中的各单元。In addition, the DSP circuit 13 , the frame memory 14 , the display unit 15 , the recording unit 16 , the operating system 17 , and the power supply system 18 are configured to be connected to each other via the bus 19 . The CPU 20 controls each unit in the imaging apparatus 10 .

透镜组11捕获来自被摄体的入射光(图像光)，并且在成像元件12的成像面上形成图像。成像元件12针对各像素将通过透镜组11在成像面上成像的入射光的光量转换成电信号，并且将该电信号作为像素信号输出。作为成像元件12，能够使用包括下述像素的成像元件(图像传感器)。The lens group 11 captures incident light (image light) from a subject, and forms an image on the imaging surface of the imaging element 12 . The imaging element 12 converts the light amount of incident light imaged on the imaging plane by the lens group 11 into an electric signal for each pixel, and outputs the electric signal as a pixel signal. As the imaging element 12, an imaging element (image sensor) including the following pixels can be used.

显示单元15包括诸如液晶显示单元或有机电致发光(EL)显示单元等面板型显示单元，并且显示由成像元件12拍摄的视频或静止图像。记录单元16将由成像元件12拍摄的视频或静止图像记录在诸如录像带或数字多用盘(DVD)等记录介质上。The display unit 15 includes a panel-type display unit such as a liquid crystal display unit or an organic electroluminescence (EL) display unit, and displays video or still images captured by the imaging element 12 . The recording unit 16 records video or still images captured by the imaging element 12 on a recording medium such as a video tape or a digital versatile disc (DVD).

操作系统17基于用户的操作发出用于本成像装置的各种功能的操作命令。电源系统18适当地将用作DSP电路13、帧存储器14、显示单元15、记录单元16和操作系统17的操作电源的各种电源提供给这些供应对象。The operating system 17 issues operation commands for various functions of the present image forming apparatus based on user's operations. The power supply system 18 appropriately supplies various power supplies used as operating power supplies for the DSP circuit 13 , the frame memory 14 , the display unit 15 , the recording unit 16 , and the operating system 17 to these supply objects.

<成像元件的构成><Configuration of Imaging Element>

图2是示出成像元件12的构成例的框图。成像元件12能够使用互补金属氧化物半导体(CMOS)图像传感器构成。FIG. 2 is a block diagram showing a configuration example of the imaging element 12 . The imaging element 12 can be configured using a complementary metal oxide semiconductor (CMOS) image sensor.

成像元件12包括像素阵列单元41、垂直驱动单元42、列处理单元43、水平驱动单元44和系统控制单元45。像素阵列单元41、垂直驱动单元42、列处理单元43、水平驱动单元44和系统控制单元45形成在半导体基板(芯片)(未示出)上。The imaging element 12 includes a pixel array unit 41 , a vertical driving unit 42 , a column processing unit 43 , a horizontal driving unit 44 and a system control unit 45 . The pixel array unit 41, the vertical driving unit 42, the column processing unit 43, the horizontal driving unit 44, and the system control unit 45 are formed on a semiconductor substrate (chip) (not shown).

在像素阵列单元41中，各自具有光电转换元件的单位像素以矩阵状二维排列，光电转换元件产生与入射光量相对应的电荷量的光电荷，并且将光电荷累积在其中。另外，在下文中，具有与入射光量相对应的电荷量的光电荷可以被简称为“电荷”，并且单位像素可以被简称为“像素”。In the pixel array unit 41, unit pixels each having photoelectric conversion elements that generate and accumulate photocharges in a charge amount corresponding to the incident light amount are two-dimensionally arranged in a matrix. In addition, hereinafter, the photocharge having the charge amount corresponding to the incident light amount may be simply referred to as "charge", and the unit pixel may be simply referred to as "pixel".

此外，在像素阵列单元41中，对于像素阵列的矩阵，像素驱动线46在图中的横向方向(像素行中的像素的排列方向)上针对各行形成，并且垂直信号线47在图中的纵向方向(像素列中的像素的排列方向)上针对各列形成。各像素驱动线46的一端连接到垂直驱动单元42的与各行相对应的输出端。Further, in the pixel array unit 41, for the matrix of the pixel array, the pixel driving lines 46 are formed for each row in the lateral direction in the figure (the arrangement direction of the pixels in the pixel row), and the vertical signal lines 47 are formed in the longitudinal direction in the figure. It is formed for each column in the direction (the arrangement direction of the pixels in the pixel column). One end of each pixel driving line 46 is connected to the output terminal of the vertical driving unit 42 corresponding to each row.

成像元件12还包括信号处理单元48和数据存储单元49。信号处理单元48和数据存储单元49可以由设置在与成像元件12分离的基板上的外部信号处理单元(例如使用数字信号处理器(DSP)或软件的处理)来实现，并且可以与成像元件12一起安装在同一基板上。The imaging element 12 also includes a signal processing unit 48 and a data storage unit 49 . The signal processing unit 48 and the data storage unit 49 may be implemented by an external signal processing unit (eg, processing using a digital signal processor (DSP) or software) provided on a substrate separate from the imaging element 12 , and may be integrated with the imaging element 12 . mounted together on the same substrate.

垂直驱动单元42是如下的像素驱动单元：其被构造成具有移位寄存器或地址解码器等，并且同时或以行为单位驱动像素阵列单元41的所有像素。尽管图中未具体示出，但是垂直驱动单元42被构造成具有读取扫描系统、扫出扫描系统或批量扫出和批量传输。The vertical driving unit 42 is a pixel driving unit which is configured to have a shift register, an address decoder, or the like, and drives all the pixels of the pixel array unit 41 simultaneously or in units of rows. Although not specifically shown in the drawing, the vertical driving unit 42 is configured to have a read scanning system, a sweep-out scanning system, or a batch sweep-out and batch transfer.

读取扫描系统以行为单位依次选择性地扫描像素阵列单元41的单位像素，以从单位像素读取信号。在行驱动(卷帘快门操作)的情况下，对于扫出，在读取扫描之前与快门速度相对应的时间，对由读取扫描系统执行读取扫描的读取行执行扫出扫描。在全局曝光(全局快门操作)的情况下，在批量传输之前与快门速度相对应的的时间执行批量扫出。The read scanning system sequentially selectively scans the unit pixels of the pixel array unit 41 in units of rows to read signals from the unit pixels. In the case of line driving (rolling shutter operation), for sweeping out, sweeping out scanning is performed on the reading line where the reading scanning is performed by the reading scanning system at a time corresponding to the shutter speed before the reading scanning. In the case of global exposure (global shutter operation), batch sweeping is performed at a time corresponding to the shutter speed before batch transfer.

由于该扫出，不必要的电荷从读取行中的单位像素的光电转换元件扫出(复位)。然后，通过扫出(复位)不必要的电荷来执行所谓的电子快门操作。这里，电子快门操作是丢弃光电转换元件的光电荷并重新开始曝光(开始累积光电荷)的操作。Due to this sweeping out, unnecessary charges are swept out (reset) from the photoelectric conversion elements of the unit pixels in the read row. Then, a so-called electronic shutter operation is performed by sweeping out (resetting) unnecessary charges. Here, the electronic shutter operation is an operation of discarding photocharges of the photoelectric conversion element and restarting exposure (starting accumulation of photocharges).

通过使用读取扫描系统的读取操作读取的信号对应于紧接在前的读取操作或电子快门操作之后的入射光量。在行驱动的情况下，从紧接在前的读取操作的读取时刻或电子快门操作的扫出时刻到当前读取操作的读取时刻的时段是单位像素中的光电荷累积时段(曝光时段)。在全局曝光的情况下，从批量扫出到批量传输的时段是累积时段(曝光时段)。The signal read by the reading operation using the reading scanning system corresponds to the incident light amount immediately after the preceding reading operation or the electronic shutter operation. In the case of row driving, the period from the reading timing of the immediately preceding reading operation or the sweeping timing of the electronic shutter operation to the reading timing of the current reading operation is the photocharge accumulation period (exposure time) in the unit pixel. period). In the case of global exposure, the period from batch sweep out to batch transfer is the accumulation period (exposure period).

从由垂直驱动单元42选择性扫描的像素行中的各单位像素输出的像素信号通过各垂直信号线47提供给列处理单元43。列处理单元43针对像素阵列单元41的各像素列，对通过垂直信号线47从所选行中的各单位像素输出的像素信号执行预定的信号处理，并且暂时保持信号处理之后的像素信号。The pixel signal output from each unit pixel in the pixel row selectively scanned by the vertical driving unit 42 is supplied to the column processing unit 43 through each vertical signal line 47 . The column processing unit 43 performs predetermined signal processing on the pixel signal output from each unit pixel in the selected row through the vertical signal line 47 for each pixel column of the pixel array unit 41, and temporarily holds the pixel signal after the signal processing.

具体地，作为信号处理，列处理单元43至少执行噪声去除处理，例如相关双采样(CDS)处理。通过列处理单元43的相关双采样，去除复位噪声或像素特有的固定模式噪声，例如放大晶体管的阈值变化。除了噪声去除处理之外，列处理单元43还能够具有例如模数(AD)转换功能，并且将信号电平作为数字信号输出。Specifically, as signal processing, the column processing unit 43 performs at least noise removal processing such as correlated double sampling (CDS) processing. By correlated double sampling of the column processing unit 43, reset noise or pixel-specific fixed pattern noise, such as threshold variation of amplifying transistors, is removed. In addition to noise removal processing, the column processing unit 43 can have, for example, an analog-to-digital (AD) conversion function, and output the signal level as a digital signal.

水平驱动单元44由移位寄存器或地址解码器等构成，并且水平驱动单元44依次选择列处理单元43的与像素列相对应的单位电路。通过水平驱动单元44执行的这种选择性扫描，由列处理单元43处理的像素信号被依次输出到信号处理单元48。The horizontal driving unit 44 is constituted by a shift register, an address decoder, or the like, and the horizontal driving unit 44 sequentially selects unit circuits of the column processing unit 43 corresponding to the pixel columns. Through this selective scanning performed by the horizontal driving unit 44 , the pixel signals processed by the column processing unit 43 are sequentially output to the signal processing unit 48 .

系统控制单元45由生成各种时序信号的时序发生器等构成，并且系统控制单元45基于时序发生器生成的各种时序信号来执行垂直驱动单元42、列处理单元43和水平驱动单元44等的驱动控制。The system control unit 45 is constituted by a timing generator or the like that generates various timing signals, and the system control unit 45 performs the operations of the vertical driving unit 42 , the column processing unit 43 , the horizontal driving unit 44 and the like based on the various timing signals generated by the timing generator. drive control.

信号处理单元48至少具有加法处理功能，并且对从列处理单元43输出的像素信号执行诸如加法处理等各种信号处理。数据存储单元49暂时存储信号处理单元48中的信号处理所需的数据。The signal processing unit 48 has at least an addition processing function, and performs various signal processing such as addition processing on the pixel signals output from the column processing unit 43 . The data storage unit 49 temporarily stores data necessary for signal processing in the signal processing unit 48 .

<第一实施方案><First Embodiment>

图3示出了根据第一实施方案的成像元件12(称为成像元件12a)的断面的构成例。成像元件12a具有如下构成：其中CMOS图像传感器(CIS)芯片101、逻辑芯片102和支撑基底103从图中的上部依次层叠。在图中，上侧是光入射面侧，并且CIS芯片101层叠在光入射面侧。FIG. 3 shows a configuration example of a cross-section of the imaging element 12 (referred to as an imaging element 12a) according to the first embodiment. The imaging element 12a has a configuration in which a CMOS image sensor (CIS) chip 101, a logic chip 102, and a support substrate 103 are stacked in this order from the upper part in the figure. In the figure, the upper side is the light incident surface side, and the CIS chip 101 is stacked on the light incident surface side.

例如，CIS芯片101是其中包括图2所示的像素阵列单元41的芯片。CIS芯片101由光电二极管层116和配线层114构成，在光电二极管层116中形成有形成在硅基板上的多个光电二极管113。另外，在CIS芯片101的光入射面侧，层叠有芯片上透镜111和滤色器112。For example, the CIS chip 101 is a chip in which the pixel array unit 41 shown in FIG. 2 is included. The CIS chip 101 is composed of a photodiode layer 116 and a wiring layer 114 , and in the photodiode layer 116 a plurality of photodiodes 113 formed on a silicon substrate are formed. In addition, on the light incident surface side of the CIS chip 101 , on-chip lenses 111 and color filters 112 are stacked.

在逻辑芯片102中，形成有逻辑电路和存储器等。例如，逻辑电路是系统控制单元45和信号处理单元48(图2)。逻辑芯片102和CIS芯片101使用形成在芯片中的焊盘连接。例如，在逻辑芯片102中的层叠有CIS芯片101的一侧形成有焊盘121。另外，在CIS芯片101中的层叠有逻辑芯片102的一侧形成有焊盘115。In the logic chip 102, a logic circuit, a memory, and the like are formed. For example, the logic circuits are the system control unit 45 and the signal processing unit 48 (FIG. 2). The logic chip 102 and the CIS chip 101 are connected using pads formed in the chip. For example, pads 121 are formed on the side of the logic chip 102 on which the CIS chip 101 is stacked. In addition, pads 115 are formed on the side of the CIS chip 101 on which the logic chip 102 is stacked.

例如，焊盘115和焊盘121使用铜(Cu)等导体形成。焊盘115电连接到形成在CIS芯片101中的电路的预定部分，例如，用于从光电二极管113读取信号的配线等。焊盘121电连接到形成在逻辑芯片102中的逻辑电路。For example, the pads 115 and the pads 121 are formed using conductors such as copper (Cu). The pads 115 are electrically connected to predetermined portions of circuits formed in the CIS chip 101 , for example, wirings and the like for reading signals from the photodiodes 113 . The pads 121 are electrically connected to logic circuits formed in the logic chip 102 .

另外，如图3所示，在CIS芯片101和逻辑芯片102层叠的状态下，彼此对应的焊盘115和焊盘121形成在相互接触的位置。换句话说，形成在CIS芯片101中的电路和形成在逻辑芯片102中的电路通过焊盘115和焊盘121彼此电连接。In addition, as shown in FIG. 3 , in a state where the CIS chip 101 and the logic chip 102 are stacked, the pads 115 and the pads 121 corresponding to each other are formed at positions in contact with each other. In other words, the circuit formed in the CIS chip 101 and the circuit formed in the logic chip 102 are electrically connected to each other through the pad 115 and the pad 121 .

形成在成像元件12a中的焊盘115和焊盘121的数量是任意的。The numbers of the pads 115 and the pads 121 formed in the imaging element 12a are arbitrary.

如图3所示，在逻辑芯片102中形成有配线122和晶体管123等。例如，在逻辑芯片102中的由硅(Si)构成的硅基板105的上侧(CIS芯片101侧)，形成有多层配线层104。在该多层配线层104中，构造有图2所示的系统控制单元45和信号处理单元48等。在多层配线层104中，形成有多个配线层，并且在配线层之间形成有层间绝缘膜。As shown in FIG. 3 , wirings 122 , transistors 123 and the like are formed in the logic chip 102 . For example, the multilayer wiring layer 104 is formed on the upper side (the CIS chip 101 side) of the silicon substrate 105 made of silicon (Si) in the logic chip 102 . In this multilayer wiring layer 104, the system control unit 45, the signal processing unit 48, and the like shown in FIG. 2 are constructed. In the multilayer wiring layer 104, a plurality of wiring layers are formed, and an interlayer insulating film is formed between the wiring layers.

焊盘121连接到配线122。另外，形成在预定配线层中的焊盘121和配线122使用在垂直方向上形成的通孔连接。在图3中，尽管示出了一个晶体管123(的栅极)，但是形成有多个晶体管。The pads 121 are connected to the wirings 122 . In addition, the pads 121 and the wirings 122 formed in a predetermined wiring layer are connected using through holes formed in the vertical direction. In FIG. 3, although one transistor 123 (gate) is shown, a plurality of transistors are formed.

在逻辑芯片102中，在层叠有支撑基底103的一侧，即，在与层叠有CIS芯片101的面相反的一侧的面(硅基板105侧)上形成有带电膜130。In the logic chip 102 , the charging film 130 is formed on the side on which the support base 103 is stacked, that is, on the side opposite to the side on which the CIS chip 101 is stacked (the silicon substrate 105 side).

在第一实施方案中，尽管将继续说明带电膜130仅形成在逻辑芯片102的硅基板105中的示例，但是带电膜130也可以形成在逻辑芯片102的侧面上。In the first embodiment, although the example in which the charging film 130 is formed only in the silicon substrate 105 of the logic chip 102 will be continued, the charging film 130 may also be formed on the side surface of the logic chip 102 .

当制造逻辑芯片102时，带电膜130被设置成不会产生由于例如在逻辑芯片102被减薄的情况下形成的缺陷而引起的不利影响。这将参考图4进行说明。When the logic chip 102 is manufactured, the charging film 130 is set so as not to cause adverse effects due to, for example, defects formed when the logic chip 102 is thinned. This will be explained with reference to FIG. 4 .

图4是形成有晶体管123的区域被放大的图。在图4中，在逻辑芯片102中，形成有晶体管123的栅极部的区域将被称为栅极形成层104，形成有晶体管123的源极和漏极的区域将被称为源极/漏极形成层105。在图4和图5中，多层配线层104将被描述为栅极形成层104，硅基板105将被描述为源极/漏极形成层105。FIG. 4 is an enlarged view of a region where the transistor 123 is formed. In FIG. 4, in the logic chip 102, the region where the gate portion of the transistor 123 is formed will be referred to as a gate formation layer 104, and the region where the source and drain of the transistor 123 are formed will be referred to as source/ A drain formation layer 105 is formed. In FIGS. 4 and 5 , the multilayer wiring layer 104 will be described as the gate formation layer 104 , and the silicon substrate 105 will be described as the source/drain formation layer 105 .

在逻辑芯片102中，形成有N型晶体管123-1和P型晶体管123-2。在源极/漏极形成层105中，形成有P阱151和N阱152。在P阱151中形成有N型晶体管123-1，在N阱152中形成有P型晶体管123-2。In the logic chip 102, an N-type transistor 123-1 and a P-type transistor 123-2 are formed. In the source/drain formation layer 105, a P well 151 and an N well 152 are formed. An N-type transistor 123 - 1 is formed in the P-well 151 , and a P-type transistor 123 - 2 is formed in the N-well 152 .

在源极/漏极形成层105中，形成有N+扩散层153。N+扩散层153形成在N型晶体管123-1的(栅极的)左右两侧，其中一个用作源极，另一个用作漏极。另外，在源极/漏极形成层105中形成有P+扩散层154。P+扩散层154形成在P型晶体管123-2的(栅极的)左右两侧，其中一个用作源极，另一个用作漏极。In the source/drain formation layer 105, an N+ diffusion layer 153 is formed. The N+ diffusion layers 153 are formed on the left and right sides (of the gate) of the N-type transistor 123-1, one of which serves as a source and the other serves as a drain. In addition, a P+ diffusion layer 154 is formed in the source/drain formation layer 105 . P+ diffusion layers 154 are formed on the left and right sides (of the gate) of the P-type transistor 123-2, one of which serves as a source and the other serves as a drain.

另外，在源极/漏极形成层105中形成有元件分离区域155。如图4所示，元件分离区域155形成为贯穿作为形成有晶体管(例如，N型晶体管123-1和P型晶体管123-2)的半导体层的源极/漏极形成层105。元件分离区域155由任意绝缘体构成。In addition, element isolation regions 155 are formed in the source/drain formation layer 105 . As shown in FIG. 4 , the element isolation region 155 is formed so as to penetrate the source/drain formation layer 105 which is a semiconductor layer in which transistors (eg, the N-type transistor 123 - 1 and the P-type transistor 123 - 2 ) are formed. The element isolation region 155 is formed of any insulator.

在半导体的PN结部分中，形成有耗尽层。例如，在P阱151和N+扩散层153彼此接触的部分以及N阱152和P+扩散层154彼此接触的部分中，形成有耗尽层161。In the PN junction portion of the semiconductor, a depletion layer is formed. For example, in a portion where the P well 151 and the N+ diffusion layer 153 are in contact with each other and a portion where the N well 152 and the P+ diffusion layer 154 are in contact with each other, a depletion layer 161 is formed.

在耗尽层161扩展至在源极/漏极形成层105中形成的缺陷附近的位置或者扩展至与缺陷接触的位置的情况下，漏电流可能从耗尽层161流向缺陷并且从缺陷流向耗尽层161。这将参照图5进行说明。In the case where the depletion layer 161 extends to a position near a defect formed in the source/drain formation layer 105 or to a position in contact with the defect, leakage current may flow from the depletion layer 161 to the defect and from the defect to the depletion Complete layer 161. This will be explained with reference to FIG. 5 .

图5是源极/漏极形成层105的一部分的放大图。图5示出了逻辑芯片102的厚度彼此不同的情况，并且示出了图5的B所示的逻辑芯片102的厚度形成得比图5的A所示的逻辑芯片102的厚度薄的情况。FIG. 5 is an enlarged view of a part of the source/drain formation layer 105 . 5 shows a case where the thicknesses of the logic chips 102 are different from each other, and shows a case where the thickness of the logic chip 102 shown in B of FIG. 5 is formed thinner than that of the logic chip 102 shown in A of FIG. 5 .

将参考图5的A。图5的A所示的逻辑芯片102示出了进行减薄直到源极/漏极形成层105的厚度变为厚度d1的情况。例如，在厚度d1能够确保在源极/漏极形成层105中形成的N+扩散层153(耗尽层161)和缺陷162彼此充分分离的情况下，能够防止经由缺陷162在N+扩散层153和耗尽层161之间发生泄漏。Reference will be made to FIG. 5A. The logic chip 102 shown in A of FIG. 5 shows a case where thinning is performed until the thickness of the source/drain formation layer 105 becomes the thickness d1. For example, in the case where the thickness d1 can ensure that the N+ diffusion layer 153 (depletion layer 161 ) and the defect 162 formed in the source/drain forming layer 105 are sufficiently separated from each other, it is possible to prevent the N+ diffusion layer 153 and the defect 162 from being formed in the N+ diffusion layer 153 and the defect 162 via the defect 162. Leakage occurs between the depletion layers 161 .

图5的B所示的逻辑芯片102示出了进行减薄直到源极/漏极形成层105的厚度变为厚度d2的情况。厚度d2是满足厚度d1>厚度d2的厚度。例如，在厚度d2不能确保在源极/漏极形成层105中形成的N+扩散层153(耗尽层161)和缺陷162彼此充分分离的情况下，可能经由缺陷162在N+扩散层153和耗尽层161之间发生泄漏。The logic chip 102 shown in B of FIG. 5 shows a case where thinning is performed until the thickness of the source/drain formation layer 105 becomes the thickness d2. The thickness d2 is a thickness satisfying thickness d1>thickness d2. For example, in the case where the thickness d2 does not ensure sufficient separation of the N+ diffusion layer 153 (depletion layer 161 ) and the defect 162 formed in the source/drain formation layer 105 from each other, the N+ diffusion layer 153 and the depletion layer 153 may be separated from each other via the defect 162 . Leakage occurs between the layers 161.

例如，在制造逻辑芯片102时的减薄工艺中，可能会形成缺陷162。另外，在减薄逻辑芯片102直到厚度变为厚度d2的情况下，如上所述，经由缺陷162的泄漏有可能增加。当发生这种泄漏增加时，产品在制造时就会被作为次品处理。Defects 162 may be formed, for example, during a thinning process in fabricating logic chip 102 . In addition, in the case where the logic chip 102 is thinned until the thickness becomes the thickness d2, as described above, there is a possibility that leakage through the defect 162 may increase. When this increased leakage occurs, the product is treated as defective at the time of manufacture.

从这一点来看，逻辑芯片102的厚度需要是一定程度的厚度。然而，当逻辑芯片102能够形成得较薄时，能够实现成像元件12的低高度和小尺寸。From this point of view, the thickness of the logic chip 102 needs to be a certain thickness. However, when the logic chip 102 can be formed thin, a low height and a small size of the imaging element 12 can be achieved.

因此，如参考图3所述的，在逻辑芯片102中形成有带电膜130。带电膜130用作捕获所产生的电子的膜。带电膜130被构造为即使发生泄露也能够捕获泄露电子的膜。通过在源极/漏极形成层105中形成这种带电膜130，能够抑制经由缺陷162在阱之间增加泄漏。Therefore, as described with reference to FIG. 3 , the charging film 130 is formed in the logic chip 102 . The charged film 130 serves as a film that captures the generated electrons. The charged film 130 is configured as a film capable of capturing leaked electrons even if leakage occurs. By forming such a charged film 130 in the source/drain formation layer 105 , it is possible to suppress an increase in leakage between wells via the defects 162 .

通过设置带电膜130，即使在逻辑芯片102的厚度形成得较薄时，也能够抑制经由缺陷162在阱之间发生(增加)泄漏。因此，即使逻辑芯片102的厚度形成得较薄，也能够降低逻辑芯片102成为次品的可能性。因此，能够将逻辑芯片102形成得较薄，并且包括这种逻辑芯片102的成像元件12a能够降低高度并且减小尺寸。By providing the charging film 130 , even when the thickness of the logic chip 102 is formed to be thin, it is possible to suppress (increase) leakage between wells via the defects 162 . Therefore, even if the thickness of the logic chip 102 is formed to be thin, the possibility of the logic chip 102 becoming a defective product can be reduced. Therefore, the logic chip 102 can be formed thinner, and the imaging element 12a including such a logic chip 102 can be reduced in height and size.

例如，源极/漏极形成层105的厚度能够形成为等于或小于20um。根据本技术，即使源极/漏极形成层105的厚度形成为等于或小于20um，也能够防止泄漏的发生(增加)。For example, the thickness of the source/drain forming layer 105 can be formed to be equal to or less than 20 um. According to the present technology, even if the thickness of the source/drain formation layer 105 is formed to be equal to or less than 20 μm, the occurrence (increase) of leakage can be prevented.

源极/漏极形成层105的厚度能够形成为小于通过将存在于源极/漏极形成层105中的杂质层(例如，N+扩散层153)的深度和从该杂质层扩展的耗尽层161的宽度相加而获得的深度。The thickness of the source/drain formation layer 105 can be formed to be smaller than the depth of the impurity layer (for example, the N+ diffusion layer 153 ) to be present in the source/drain formation layer 105 and the depletion layer extending from the impurity layer The depth obtained by adding the widths of 161.

在逻辑芯片102的研磨侧基板是P型基板的情况下，带电膜130能够形成为具有负电荷的膜或产生负电荷的膜。换句话说，带电膜130能够被构造为具有负固定电荷的膜。通过在研磨后的逻辑芯片102中形成这样的带电膜130，能够在逻辑芯片102的研磨后的界面附近形成霍尔累积层。然后，使用该霍尔累积层，能够使电子再结合，并且能够抑制经由在界面附近形成的缺陷162在阱之间增加泄漏。In the case where the polishing-side substrate of the logic chip 102 is a P-type substrate, the charging film 130 can be formed as a film having a negative charge or a film generating a negative charge. In other words, the charged film 130 can be configured as a film having a negative fixed charge. By forming such a charged film 130 in the polished logic chip 102 , a Hall accumulation layer can be formed in the vicinity of the polished interface of the logic chip 102 . Then, using this Hall accumulation layer, electrons can be recombined, and leakage can be suppressed from increasing between wells via defects 162 formed in the vicinity of the interface.

在逻辑芯片102的研磨侧基板是N型基板的情况下，带电膜130能够形成为具有正电荷的膜或产生正电荷的膜。换句话说，带电膜130能够被构造为具有正固定电荷的膜。通过在研磨后的逻辑芯片102中形成这样的带电膜130，能够在逻辑芯片102的研磨后的界面附近形成电子累积层。然后，使用该电子累积层，能够使质子再结合，并且能够抑制经由在界面附近形成的缺陷162在阱之间增加泄漏。In the case where the polishing-side substrate of the logic chip 102 is an N-type substrate, the charging film 130 can be formed as a film having a positive charge or a film generating a positive charge. In other words, the charged film 130 can be configured as a film having a positive fixed charge. By forming such a charged film 130 in the polished logic chip 102 , an electron accumulation layer can be formed in the vicinity of the polished interface of the logic chip 102 . Then, using this electron accumulation layer, the protons can be recombined, and the increase of leakage between the wells via the defects 162 formed in the vicinity of the interface can be suppressed.

例如，如图4所示，在逻辑芯片102的研磨侧基板是P阱151的情况下，形成具有负固定电荷的带电膜130。另外，例如，如图4所示，在逻辑芯片102的研磨侧基板是N阱152的情况下，形成具有正固定电荷的带电膜130。For example, as shown in FIG. 4 , in the case where the polishing-side substrate of the logic chip 102 is the P well 151 , the charged film 130 having a negative fixed charge is formed. In addition, for example, as shown in FIG. 4 , in the case where the polishing-side substrate of the logic chip 102 is the N well 152 , the charged film 130 having a positive fixed charge is formed.

尽管下面参考图13进行了说明，但是作为形成在逻辑芯片102中的带电膜，可以形成具有不同特性的膜。例如，如上所述，在逻辑芯片102的研磨侧基板上，可以形成具有负固定电荷的带电膜130和具有正固定电荷的带电膜130。Although described below with reference to FIG. 13, as the charged film formed in the logic chip 102, films having different characteristics may be formed. For example, as described above, on the grinding-side substrate of the logic chip 102, the charged film 130 having a negative fixed charge and the charged film 130 having a positive fixed charge may be formed.

带电膜130可以由能够具有固定电荷的材料形成。例如，能够使用氧化铪、氧化铝、氧化锆、氧化钽、氧化钛、氧化镧或氧化钇等。The charged film 130 may be formed of a material capable of having a fixed charge. For example, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, titanium oxide, lanthanum oxide, yttrium oxide, or the like can be used.

带电膜130的一部分可以被氮化。A portion of the charging film 130 may be nitrided.

另外，带电膜130可以是使用铁电物质形成的铁电膜，所述铁电物质通过自发极化或压电极化在薄膜中引起电解。例如，能够使用极化为负极或正极的氮化镓(GaN)、钛酸钡(BaTi₃O)、氧化锌(ZnO)或氮化铝(ALN)等。In addition, the charged film 130 may be a ferroelectric film formed using a ferroelectric substance that induces electrolysis in the thin film through spontaneous polarization or piezoelectric polarization. For example, gallium nitride (GaN), barium titanate (BaTi ₃ O), zinc oxide (ZnO), aluminum nitride (ALN), or the like polarized as a negative electrode or a positive electrode can be used.

另外，带电膜130可以如图3所示由单层构成，或者可以如图6所示由多层构成。在图6所示的成像元件12a的逻辑芯片102中，层叠有带电膜130-1和带电膜130-2。带电膜130-1和带电膜130-2能够使用上述材料形成。In addition, the charging film 130 may be composed of a single layer as shown in FIG. 3 , or may be composed of a plurality of layers as shown in FIG. 6 . In the logic chip 102 of the imaging element 12a shown in FIG. 6, a charging film 130-1 and a charging film 130-2 are laminated. The charging film 130-1 and the charging film 130-2 can be formed using the above-described materials.

尽管在图6中示出了带电膜130由两层构成的示例，但是带电膜也可以由诸如三层或四层等多层构成。另外，在带电膜由多层构成的情况下，带电膜可以由组合了上述材料的层构成。在带电膜由多层构成的情况下，与带电膜由单层构成的情况相比，带电膜能够被构造为捕获更多的电子或质子，并且能够进一步抑制泄漏的发生。Although the example in which the charging film 130 is composed of two layers is shown in FIG. 6 , the charging film may be composed of multiple layers such as three layers or four layers. In addition, when the charging film is composed of a plurality of layers, the charging film may be composed of a layer in which the above-mentioned materials are combined. In the case where the charged film is composed of a plurality of layers, the charged film can be configured to capture more electrons or protons than in the case where the charged film is composed of a single layer, and the occurrence of leakage can be further suppressed.

这里，用于形成带电膜130的材料和层数等也能够类似地适用于以下实施方案。Here, the material and the number of layers and the like for forming the charging film 130 can also be similarly applied to the following embodiments.

<第二实施方案><Second Embodiment>

图7是示出根据第二实施方案的成像元件12(称为成像元件12b)的断面的构成例的图。FIG. 7 is a diagram showing a configuration example of a cross-section of an imaging element 12 (referred to as an imaging element 12 b ) according to the second embodiment.

根据第二实施方案的成像元件12b与根据第一实施方案的成像元件12a的不同之处在于，层叠(设置)有两个逻辑芯片102，并且成像元件12b的其他方面与成像元件12a基本相似。在下文中，将适当地省略对相似方面的说明。The imaging element 12b according to the second embodiment differs from the imaging element 12a according to the first embodiment in that two logic chips 102 are stacked (disposed), and the imaging element 12b is otherwise substantially similar to the imaging element 12a. Hereinafter, descriptions of similar aspects will be omitted as appropriate.

在根据第二实施方案的成像元件12b中，在一个CIS芯片101中层叠(设置)有逻辑芯片102-1和逻辑芯片102-2。这里，尽管说明了逻辑芯片102-1和逻辑芯片102-2，但是它们中的任何一个都可以是形成有诸如存储器等逻辑电路以外的电路的芯片。In the imaging element 12 b according to the second embodiment, a logic chip 102 - 1 and a logic chip 102 - 2 are stacked (disposed) in one CIS chip 101 . Here, although the logic chip 102-1 and the logic chip 102-2 are described, any of them may be a chip formed with circuits other than logic circuits such as a memory.

在图7中，尽管示出了在一个CIS芯片101中层叠有包括逻辑芯片102-1和逻辑芯片102-2的两个芯片的示例，但是也可以层叠有两个以上的逻辑芯片102。In FIG. 7, although the example in which two chips including the logic chip 102-1 and the logic chip 102-2 are stacked in one CIS chip 101 is shown, more than two logic chips 102 may be stacked.

像图7所示的成像元件12一样，当在一个CIS芯片101中设置两个逻辑芯片102-1和102-2的情况下，在逻辑芯片102-1和逻辑芯片102-2之间产生间隙。在该间隙中，形成有氧化膜201。Like the imaging element 12 shown in FIG. 7, when two logic chips 102-1 and 102-2 are provided in one CIS chip 101, a gap is generated between the logic chip 102-1 and the logic chip 102-2 . In this gap, an oxide film 201 is formed.

在逻辑芯片102-1和逻辑芯片102-2的周边部分的空间中，形成填充有氧化膜201的状态。据此，逻辑芯片102-1和逻辑芯片102-2处于嵌入氧化膜201中的状态。In the space of the logic chip 102-1 and the peripheral portion of the logic chip 102-2, a state of being filled with the oxide film 201 is formed. According to this, the logic chip 102 - 1 and the logic chip 102 - 2 are in a state of being embedded in the oxide film 201 .

另外，在逻辑芯片102-1和逻辑芯片102-2中还形成(层叠)有带电膜130b。带电膜130b也形成在逻辑芯片102-1和逻辑芯片102-2之间的间隙部分中。像根据第一实施方案的成像元件12a一样，带电膜130b形成在逻辑芯片102-1和逻辑芯片102-2各者的除层叠有CIS芯片101的面以外的面(以下适当地称为背面)上，并且形成在逻辑芯片102-1和逻辑芯片102-2各者的侧面上。In addition, a charging film 130b is also formed (laminated) in the logic chip 102-1 and the logic chip 102-2. The charging film 130b is also formed in the gap portion between the logic chip 102-1 and the logic chip 102-2. Like the imaging element 12a according to the first embodiment, the charging film 130b is formed on the surfaces of each of the logic chip 102-1 and the logic chip 102-2 other than the surface on which the CIS chip 101 is stacked (hereinafter referred to as the back surface as appropriate) and formed on the side surfaces of each of the logic chip 102-1 and the logic chip 102-2.

如图7所示，在逻辑芯片102-1的侧面和背面上，形成有带电膜130b，并且在带电膜130b上层叠有氧化膜201。以相同的方式，在逻辑芯片102-2的侧面和背面上，形成有带电膜130b，并且在带电膜130b上层叠有氧化膜201。As shown in FIG. 7 , on the side surface and the back surface of the logic chip 102-1, a charging film 130b is formed, and an oxide film 201 is laminated on the charging film 130b. In the same manner, on the side surface and the back surface of the logic chip 102-2, the charging film 130b is formed, and the oxide film 201 is laminated on the charging film 130b.

以这种方式，带电膜130b也可以形成在逻辑芯片102的侧面上。In this way, the charging film 130b can also be formed on the side surface of the logic chip 102 .

此外，在根据第二实施方案的成像元件12b中，通过形成带电膜130b，即使逻辑芯片102的厚度形成得较薄，也能够抑制经由在界面附近形成的缺陷在阱之间增加泄漏。Further, in the imaging element 12b according to the second embodiment, by forming the charging film 130b, even if the thickness of the logic chip 102 is formed thin, it is possible to suppress increase of leakage between wells via defects formed near the interface.

另外，在逻辑芯片102能够形成得较薄的情况下，逻辑芯片102-1和逻辑芯片102-2之间的间隙的深度能够形成得较浅。由于间隙具有与逻辑芯片102的厚度相同的深度，因此在逻辑芯片102形成得越薄的情况下，间隙变得越浅。In addition, in the case where the logic chip 102 can be formed thinner, the depth of the gap between the logic chip 102-1 and the logic chip 102-2 can be formed shallower. Since the gap has the same depth as the thickness of the logic chip 102, the gap becomes shallower as the logic chip 102 is formed thinner.

在逻辑芯片102之间的间隙较大的情况下，很难完全填充氧化膜201，并且可能在氧化膜201中形成包括空气的间隙。当在氧化膜201中存在间隙时，层叠的支撑基底103可能弯曲或热膨胀。In the case where the gap between the logic chips 102 is large, it is difficult to completely fill the oxide film 201 , and a gap including air may be formed in the oxide film 201 . When there is a gap in the oxide film 201, the laminated support substrate 103 may be bent or thermally expanded.

然而，根据本技术，通过减薄逻辑芯片102，逻辑芯片102之间的间隙能够形成得较浅，因此该间隙能够被氧化膜201充分填充。因此，能够防止支撑基底103弯曲，并且能够防止在逻辑芯片102之间形成包括空气的间隙。However, according to the present technology, by thinning the logic chips 102 , the gaps between the logic chips 102 can be formed shallower, and thus the gaps can be sufficiently filled with the oxide film 201 . Therefore, the support substrate 103 can be prevented from being bent, and the formation of gaps including air between the logic chips 102 can be prevented.

<第三实施方案><Third Embodiment>

图8示出了根据第三实施方案的成像元件12(称为成像元件12c)的断面的构成例。FIG. 8 shows a configuration example of a cross-section of an imaging element 12 (referred to as an imaging element 12 c ) according to the third embodiment.

根据第三实施方案的成像元件12c与根据第一实施方案的成像元件12a的不同之处在于，还层叠有芯片251，并且成像元件12c的其他方面与成像元件12a基本相似。The imaging element 12c according to the third embodiment is different from the imaging element 12a according to the first embodiment in that a chip 251 is further laminated, and the imaging element 12c is substantially similar to the imaging element 12a in other aspects.

芯片251可以是形成有逻辑电路的芯片或形成有存储器的芯片。另外，芯片251可以是具有人工智能(AI)功能的信号处理芯片。The chip 251 may be a chip formed with a logic circuit or a chip formed with a memory. In addition, the chip 251 may be a signal processing chip with an artificial intelligence (AI) function.

这里，尽管示出了在第三层中仅层叠芯片251的情况，但是例如，如图7所示的成像元件12b那样，也可以层叠(设置)两个以上的芯片。另外，当在第三层中层叠两个或更多个芯片时，可以层叠(设置)具有存储功能的芯片和具有AI功能的芯片。Here, although the case where only the chip 251 is stacked in the third layer is shown, for example, like the imaging element 12b shown in FIG. 7 , two or more chips may be stacked (arranged). In addition, when two or more chips are stacked in the third layer, a chip with a memory function and a chip with an AI function can be stacked (arranged).

芯片251经由带电膜130层叠在逻辑芯片102上。与逻辑芯片102类似，芯片251由多层配线层254和硅基板255构成。在多层配线层254中，形成有配线262。The chip 251 is stacked on the logic chip 102 via the charging film 130 . Similar to the logic chip 102 , the chip 251 is composed of a multilayer wiring layer 254 and a silicon substrate 255 . In the multilayer wiring layer 254, wirings 262 are formed.

与CIS芯片101和逻辑芯片102类似，逻辑芯片102和芯片251使用焊盘连接。在芯片251中的层叠有逻辑芯片102的一侧形成有焊盘261。形成在芯片251内部的配线层中的配线262连接到该焊盘261。Similar to the CIS chip 101 and the logic chip 102, the logic chip 102 and the chip 251 are connected using pads. A pad 261 is formed on the side of the chip 251 on which the logic chip 102 is stacked. The wiring 262 formed in the wiring layer inside the chip 251 is connected to this pad 261 .

形成在芯片251中的焊盘261与形成在氧化膜253中的焊盘263连接，并且该焊盘263经由通孔125与逻辑芯片102的多层配线层104内部的配线124连接。这里，以这种方式，尽管示出了逻辑芯片102和芯片251使用焊盘261和焊盘263彼此电连接的情况，但是逻辑芯片102和芯片251也可以使用其他连接方法连接。The pad 261 formed in the chip 251 is connected to the pad 263 formed in the oxide film 253 , and the pad 263 is connected to the wiring 124 inside the multilayer wiring layer 104 of the logic chip 102 via the through hole 125 . Here, in this manner, although the case where the logic chip 102 and the chip 251 are electrically connected to each other using the pads 261 and 263 is shown, the logic chip 102 and the chip 251 may be connected using other connection methods.

在芯片251的与层叠有逻辑芯片102的面相反的一侧的面(背面)上，即硅基板255侧，形成有带电膜252。该带电膜252仅形成在背面的一部分中。在图8所示的断面图中，带电膜252没有形成在芯片251的端部侧。另外，包括带电膜252的芯片251处于嵌入氧化膜253中的状态。A charging film 252 is formed on the surface (back surface) of the chip 251 opposite to the surface on which the logic chip 102 is stacked, that is, on the side of the silicon substrate 255 . This charging film 252 is formed only in a part of the back surface. In the cross-sectional view shown in FIG. 8 , the charging film 252 is not formed on the end portion side of the chip 251 . In addition, the chip 251 including the charged film 252 is in a state of being embedded in the oxide film 253 .

带电膜130c以覆盖逻辑芯片102的整个背面的方式形成，而带电膜252以覆盖芯片251的背面的一部分的方式形成。带电膜可以形成为覆盖芯片的预定面的整个面，或者可以形成为覆盖芯片的预定面的一部分。另外，在带电膜形成为覆盖芯片的预定面的一部分的情况下，例如，带电膜可以形成为条状。带电膜可以形成在由于出现缺陷而可能发生泄漏的区域中。The charging film 130 c is formed so as to cover the entire back surface of the logic chip 102 , and the charging film 252 is formed so as to cover a part of the back surface of the chip 251 . The charging film may be formed to cover the entire surface of the predetermined surface of the chip, or may be formed to cover a part of the predetermined surface of the chip. In addition, in the case where the charging film is formed to cover a part of the predetermined surface of the chip, for example, the charging film may be formed in a stripe shape. The charged film may be formed in a region where leakage may occur due to the occurrence of defects.

如在第三实施方案中，在层叠多个芯片的情况下，可以在它们中的一个芯片或多个芯片中形成带电膜。另外，如逻辑芯片102和芯片251那样，本技术也能够适用于层叠不同尺寸的芯片的情况。As in the third embodiment, in the case of stacking a plurality of chips, a charged film may be formed in one chip or a plurality of chips among them. In addition, like the logic chip 102 and the chip 251, the present technology can also be applied to the case where chips of different sizes are stacked.

同样在根据第三实施方案的成像元件12c中，通过形成带电膜130c和带电膜252，即使当逻辑芯片102和芯片251的厚度形成得较薄时，也能够抑制经由在界面附近形成的缺陷在阱之间增加泄漏。Also in the imaging element 12c according to the third embodiment, by forming the charging film 130c and the charging film 252, even when the thicknesses of the logic chip 102 and the chip 251 are formed to be thin, it is possible to suppress the occurrence of defects in the vicinity of the interface via defects formed in the interface. Increased leakage between traps.

<第四实施方案><Fourth Embodiment>

将说明第四实施方案。在第一至第三实施方案中，尽管以包括带电膜的成像元件12为例进行了说明，但是带电膜也可以形成在构成成像元件的芯片以外的部分中。The fourth embodiment will be explained. In the first to third embodiments, although the imaging element 12 including the charging film has been described as an example, the charging film may be formed in a portion other than the chip constituting the imaging element.

图9是示出根据第四实施方案的层叠芯片的构成例的图。在图9所示的层叠芯片301a中，从图中的上侧依次层叠有存储器芯片311、逻辑芯片102和支撑基底103。图9所示的层叠芯片301a的不同之处在于，设置存储器芯片311代替图7所示的成像元件12b的CIS芯片101，而其他方面相似。FIG. 9 is a diagram showing a configuration example of a stacked chip according to a fourth embodiment. In the stacked chip 301 a shown in FIG. 9 , the memory chip 311 , the logic chip 102 , and the support substrate 103 are stacked in this order from the upper side in the drawing. The laminated chip 301a shown in FIG. 9 is different in that a memory chip 311 is provided in place of the CIS chip 101 of the imaging element 12b shown in FIG. 7, but is otherwise similar.

在图9所示的层叠芯片301a中，在一个存储器芯片311中层叠(设置)有逻辑芯片102-1和逻辑芯片102-2。根据层叠芯片301a，例如，由逻辑芯片102-1处理的数据存储在存储器芯片311中，并且逻辑芯片102-2能够使用所存储的数据执行预定处理。In the stacked chip 301 a shown in FIG. 9 , a logic chip 102 - 1 and a logic chip 102 - 2 are stacked (disposed) in one memory chip 311 . According to the stacked chip 301a, for example, data processed by the logic chip 102-1 is stored in the memory chip 311, and the logic chip 102-2 can perform predetermined processing using the stored data.

在层叠芯片301a的逻辑芯片102-1和逻辑芯片102-2各者的背面上形成有带电膜330。例如，该带电膜330是与根据第二实施方案的成像元件12b的带电膜130b相对应的膜，并且该带电膜330能够被构造为具有与根据第一实施方案的带电膜130a相同的构成(材料等)。因此，即使当逻辑芯片102-1和逻辑芯片102-2形成得较薄时，也能够防止由于存在于背面侧的缺陷而发生(增加)泄漏。A charging film 330 is formed on the back surface of each of the logic chip 102-1 and the logic chip 102-2 of the stacked chip 301a. For example, the charging film 330 is a film corresponding to the charging film 130b of the imaging element 12b according to the second embodiment, and the charging film 330 can be configured to have the same constitution as the charging film 130a according to the first embodiment ( materials, etc.). Therefore, even when the logic chip 102-1 and the logic chip 102-2 are formed thin, occurrence of (increase) leakage due to defects existing on the back surface side can be prevented.

通过减薄逻辑芯片102-1和逻辑芯片102-2的厚度，能够减薄其中层叠有逻辑芯片102-1和逻辑芯片102-2的层叠芯片301a的厚度。因此，可以实现层叠芯片301a的低高度和小尺寸。By thinning the thicknesses of the logic chip 102-1 and the logic chip 102-2, the thickness of the stacked chip 301a in which the logic chip 102-1 and the logic chip 102-2 are stacked can be thinned. Therefore, a low height and a small size of the stacked chip 301a can be achieved.

<第五实施方案><Fifth Embodiment>

图10是示出根据第五实施方案的层叠芯片301b的构成例的图。FIG. 10 is a diagram showing a configuration example of a stacked chip 301b according to the fifth embodiment.

在根据第五实施方案的层叠芯片301b中，与根据第四实施方案的层叠芯片301a(图9)类似，层叠有存储器芯片311、逻辑芯片102和支撑基底103。在根据第五实施方案的层叠芯片301b中，在存储器芯片311中形成有带电膜330b。In the stacked chip 301 b according to the fifth embodiment, similarly to the stacked chip 301 a according to the fourth embodiment ( FIG. 9 ), a memory chip 311 , a logic chip 102 , and a support substrate 103 are stacked. In the stacked chip 301b according to the fifth embodiment, a charging film 330b is formed in the memory chip 311 .

带电膜330可以如图9所示的层叠芯片301a中那样形成在逻辑芯片102中，或者可以如图10所示的层叠芯片301b中那样形成在存储器芯片311中。The charging film 330 may be formed in the logic chip 102 as in the stacked chip 301 a shown in FIG. 9 , or may be formed in the memory chip 311 as in the stacked chip 301 b shown in FIG. 10 .

另外，带电膜330可以形成在层叠有支撑基底103的一侧的面上，或者可以形成在没有层叠支撑基底103的一侧的面上。此外，与图10所示的示例类似，带电膜330可以形成在没有与其他芯片层叠的一侧，换句话说，处于暴露状态。In addition, the charging film 330 may be formed on the face on the side where the support base 103 is stacked, or may be formed on the face on the side where the support base 103 is not stacked. Furthermore, similar to the example shown in FIG. 10 , the charging film 330 may be formed on the side not laminated with other chips, in other words, in an exposed state.

另外，层叠(设置)在存储器芯片311上的逻辑芯片102可以如同根据第四实施方案的层叠芯片301a中一样是多个逻辑芯片102，或者可以如同根据第五实施方案的层叠芯片301b中一样是一个逻辑芯片102。In addition, the logic chip 102 stacked (disposed) on the memory chip 311 may be a plurality of logic chips 102 as in the stacked chip 301a according to the fourth embodiment, or may be a plurality of logic chips 102 as in the stacked chip 301b according to the fifth embodiment A logic chip 102 .

通过组合第四实施方案和第五实施方案，可以采用在存储器芯片311和逻辑芯片102两者上都形成带电膜的构造。By combining the fourth embodiment and the fifth embodiment, a configuration in which a charged film is formed on both the memory chip 311 and the logic chip 102 can be adopted.

带电膜形成在构成层叠芯片301的多个芯片中的一个芯片或多个芯片的预定面上。层叠(设置)的芯片可以具有一对一的关系或一对多的关系。The charging film is formed on a predetermined surface of one chip or a plurality of chips among the plurality of chips constituting the stacked chip 301 . The stacked (disposed) chips may have a one-to-one relationship or a one-to-many relationship.

通过将期望形成得较薄的芯片薄薄地形成并在薄薄地形成的芯片中形成带电膜，即使有在减薄工艺时形成的缺陷，也能够防止经由该缺陷发生泄漏。因此，能够层叠能够抑制泄漏的薄型化的芯片，并且能够实现层叠芯片301的低高度和小尺寸。Even if there is a defect formed during the thinning process, leakage through the defect can be prevented by thinly forming a chip that is desired to be thinned and forming a charging film in the thinly formed chip. Therefore, a thinned chip capable of suppressing leakage can be stacked, and a low height and a small size of the stacked chip 301 can be realized.

<第六实施方案><Sixth Embodiment>

图11是示出根据第六实施方案的层叠芯片301c的构成例的图。FIG. 11 is a diagram showing a configuration example of a stacked chip 301c according to the sixth embodiment.

根据第六实施方案的层叠芯片301c具有通过从根据第四实施方案的层叠芯片301a中去除支撑基底103而获得的不同构成。可以采用在层叠芯片301中不设置支撑基底103的构成。The laminated chip 301c according to the sixth embodiment has a different constitution obtained by removing the support base 103 from the laminated chip 301a according to the fourth embodiment. A configuration in which the support base 103 is not provided in the laminated chip 301 can be adopted.

另外，根据第六实施方案的层叠芯片301c与根据第四实施方案的层叠芯片301a的不同之处在于，在逻辑芯片102-1和逻辑芯片102-2之间的间隙部分中仅填充氧化膜201c。换句话说，在逻辑芯片102-1和逻辑芯片102-2各者的侧面上没有形成带电膜330c。In addition, the stacked chip 301c according to the sixth embodiment is different from the stacked chip 301a according to the fourth embodiment in that only the oxide film 201c is filled in the gap portion between the logic chip 102-1 and the logic chip 102-2 . In other words, the charging film 330c is not formed on the side surfaces of each of the logic chip 102-1 and the logic chip 102-2.

带电膜可以被构造为形成在芯片的侧面上，或者可以被构造为不形成在芯片的侧面上。The charging film may be configured to be formed on the side of the chip, or may be configured not to be formed on the side of the chip.

带电膜是否形成在芯片的侧面上取决于制造时执行的工艺的差异。如图11所示，当在逻辑芯片102-1和逻辑芯片102-2的侧面上没有形成带电膜330c的情况下，在将逻辑芯片102-1和逻辑芯片102-1设置在存储器芯片311中之后，在逻辑芯片102-1和逻辑芯片102-2之间(的间隙中)填充氧化膜201c。Whether or not the charged film is formed on the side of the chip depends on the difference in processes performed at the time of manufacture. As shown in FIG. 11, in the case where the charging film 330c is not formed on the side surfaces of the logic chip 102-1 and the logic chip 102-2, the logic chip 102-1 and the logic chip 102-1 are provided in the memory chip 311 After that, the oxide film 201c is filled between (the gap between) the logic chip 102-1 and the logic chip 102-2.

当在间隙中填充氧化膜201c时，氧化膜201c也形成在逻辑芯片102-1和逻辑芯片102-2的背面上，并且例如使用化学机械抛光(CMP)去除形成在背面侧的氧化膜201c。此后，当形成带电膜330c时，制造出如图11所示的层叠芯片301c。When the oxide film 201c is filled in the gap, the oxide film 201c is also formed on the back surfaces of the logic chip 102-1 and the logic chip 102-2, and the oxide film 201c formed on the back surface side is removed, for example, using chemical mechanical polishing (CMP). After that, when the charging film 330c is formed, a laminated chip 301c as shown in FIG. 11 is manufactured.

将再次参考图9。如同图9所示的层叠芯片301a中那样，当在逻辑芯片102-1和逻辑芯片102-2的侧面上形成带电膜330的情况下，在将逻辑芯片102-1和逻辑芯片102-1设置在存储器芯片311中之后，在逻辑芯片102-1和逻辑芯片102-2各者的侧面和背面上形成带电膜330。Figure 9 will be referenced again. As in the laminated chip 301a shown in FIG. 9, when the charging film 330 is formed on the side surfaces of the logic chip 102-1 and the logic chip 102-2, the logic chip 102-1 and the logic chip 102-1 are disposed After the memory chip 311, a charging film 330 is formed on the side and back surfaces of each of the logic chip 102-1 and the logic chip 102-2.

此后，在逻辑芯片102-1和逻辑芯片102-2之间的间隙中填充氧化膜201，并且氧化膜201形成在每个逻辑芯片的背面上。以这种方式，在形成带电膜330之后，当形成氧化膜201时，制造出如图9所示的层叠芯片301a。After that, the oxide film 201 is filled in the gap between the logic chip 102-1 and the logic chip 102-2, and the oxide film 201 is formed on the back surface of each logic chip. In this way, after the charging film 330 is formed, when the oxide film 201 is formed, the laminated chip 301a as shown in FIG. 9 is manufactured.

同样在图11所示的根据第六实施方案的层叠芯片301c中，与上述实施方案一样，通过形成带电膜330c，能够抑制经由缺陷发生(增加)泄漏。因此，层叠芯片301c能够形成得较薄。另外，层叠芯片301c通过采用不具有支撑基底103的构造能够形成在较薄的一侧。Also in the laminated chip 301 c according to the sixth embodiment shown in FIG. 11 , by forming the charging film 330 c as in the above-described embodiments, it is possible to suppress the occurrence (increase) of leakage via defects. Therefore, the laminated chip 301c can be formed thin. In addition, the laminated chip 301 c can be formed on the thinner side by adopting a configuration without the support base 103 .

这种不具有支撑基底103的层叠芯片301c能够以小的间隙安装。Such a stacked chip 301c without the support base 103 can be mounted with a small gap.

<第七实施方案><Seventh Embodiment>

图12是示出根据第七实施方案的层叠芯片301d的构成例的图。FIG. 12 is a diagram showing a configuration example of a laminated chip 301d according to the seventh embodiment.

根据第七实施方案的层叠芯片301d被构造为层叠有多个芯片。在上述实施方案中，尽管以芯片是CIS芯片、存储器芯片和逻辑芯片等的情况为例进行了说明，但是层叠芯片可以是这种芯片，或者可以是本文未示出的其他芯片。The stacked chip 301d according to the seventh embodiment is configured to have a plurality of chips stacked. In the above-described embodiments, although the case where the chip is a CIS chip, a memory chip, a logic chip, or the like has been described as an example, the stacked chip may be such a chip, or may be other chips not shown herein.

图12所示的层叠芯片301d示出了如下示例：其中从图中的上部起层叠有芯片401、芯片402和芯片403，并且还层叠有支撑基底404。芯片401、芯片402和芯片403可以是诸如CIS芯片、存储器芯片和逻辑芯片等芯片。The laminated chip 301 d shown in FIG. 12 shows an example in which the chip 401 , the chip 402 , and the chip 403 are laminated from the upper part in the figure, and the supporting base 404 is also laminated. Chip 401, chip 402, and chip 403 may be chips such as CIS chips, memory chips, and logic chips.

在芯片401的背面上形成有带电膜330d-1，在芯片402的背面上形成有带电膜330d-2，在芯片403的背面上形成有带电膜330d-3。芯片401至403分别包括带电膜330d-1至330d-3，因此具有能够抑制泄漏发生的构造。The charging film 330d-1 is formed on the back surface of the chip 401, the charging film 330d-2 is formed on the back surface of the chip 402, and the charging film 330d-3 is formed on the back surface of the chip 403. The chips 401 to 403 include the charging films 330d-1 to 330d-3, respectively, and thus have a configuration capable of suppressing the occurrence of leakage.

芯片401至403能够形成在薄侧。通过将芯片401至403形成得较薄，层叠芯片301d能够实现为具有低高度和小尺寸。Chips 401 to 403 can be formed on the thin side. By forming the chips 401 to 403 thin, the stacked chip 301d can be realized to have a low height and a small size.

尽管图12所示的层叠芯片301d被构造成层叠有三个芯片401至403，但是本技术也能够适用于层叠有四个或更多个芯片的情况。另外，根据本技术，能够减小各芯片的高度，因此，在层叠有多个芯片的情况下，高度能够比传统情况下减小得更多。Although the stacked chip 301 d shown in FIG. 12 is configured to be stacked with three chips 401 to 403 , the present technology can also be applied to a case where four or more chips are stacked. In addition, according to the present technology, the height of each chip can be reduced, and therefore, in the case where a plurality of chips are stacked, the height can be reduced more than in the conventional case.

对于芯片401至403的连接，能够应用硅通孔(TSV)、凸块或CuCu连接等。例如，芯片401和支撑基底404使用TSV 411连接。另外，TSV 411和支撑基底404使用凸块412连接。For the connection of the chips 401 to 403, through-silicon vias (TSVs), bumps or CuCu connections or the like can be applied. For example, the chip 401 and the support substrate 404 are connected using the TSV 411 . In addition, the TSV 411 and the support substrate 404 are connected using bumps 412 .

类似地，芯片403和支撑基底404使用TSV 413连接，并且TSV 413和支撑基底404使用凸块414连接。Similarly, the chip 403 and the support substrate 404 are connected using TSVs 413 , and the TSVs 413 and the support substrate 404 are connected using bumps 414 .

通过应用本技术，能够将TSV 411和TSV 413形成得较细。例如，TSV 411从芯片401通过贯穿芯片402和芯片403形成到凸块412。通常，TSV形成为所谓的锥形形状，其中开口部分加宽并且从开口部分逐渐变窄。By applying this technique, the TSV 411 and the TSV 413 can be formed thin. For example, TSV 411 is formed from chip 401 through chip 402 and chip 403 to bump 412 . Generally, the TSV is formed in a so-called tapered shape in which an opening portion widens and gradually narrows from the opening portion.

通常，当TSV 411的形成深度变大时，锥形形状的开口部分变大，并且必须形成得较粗。根据本技术，能够将芯片401至403分别形成得较薄。Generally, as the formation depth of the TSV 411 becomes larger, the opening portion of the tapered shape becomes larger and must be formed thicker. According to the present technology, the chips 401 to 403 can be formed thinner, respectively.

因此，能够缩短TSV 411的形成深度，并且能够将TSV 411形成得较细。通过将TSV411形成得较细，能够减小平面上TSV 411的形成面积，并且能够减小层叠芯片301d的尺寸。Therefore, the formation depth of the TSV 411 can be shortened, and the TSV 411 can be formed thin. By forming the TSV 411 thin, the formation area of the TSV 411 on the plane can be reduced, and the size of the stacked chip 301 d can be reduced.

同样在图12所示的根据第七实施方案的层叠芯片301d中，通过如上述实施方案那样形成带电膜330d，能够抑制经由缺陷发生(增加)泄漏。因此，能够将层叠芯片301d形成得较薄，并且能够实现低高度和小尺寸。Also in the laminated chip 301 d according to the seventh embodiment shown in FIG. 12 , by forming the charging film 330 d as in the above-described embodiment, the occurrence (increase) of leakage through defects can be suppressed. Therefore, the laminated chip 301d can be formed thin, and a low height and a small size can be realized.

<第八实施方案><Eighth Embodiment>

图13是示出根据第八实施方案的层叠芯片301e的构成例的图。FIG. 13 is a diagram showing a configuration example of a laminated chip 301e according to the eighth embodiment.

与根据第五实施方案的层叠芯片301b(图10)相比，根据第八实施方案的层叠芯片301e的不同之处在于，其构造成使得逻辑芯片102包括单片(monolithic)器件。单片器件是在一个基板上或基板内形成晶体管、二极管、电阻器和电容器等并进行布线的集成电路。The stacked chip 301e according to the eighth embodiment is different from the stacked chip 301b according to the fifth embodiment (FIG. 10) in that it is configured such that the logic chip 102 includes a monolithic device. A monolithic device is an integrated circuit in which transistors, diodes, resistors, capacitors, etc. are formed and wired on or within a substrate.

在图13所示的示例中，在逻辑芯片102的内部存在单片器件351。通过采用逻辑芯片102包括单片器件351的构造，能够增加安装面积。In the example shown in FIG. 13 , a monolithic device 351 exists inside the logic chip 102 . By adopting the configuration in which the logic chip 102 includes the monolithic device 351, the mounting area can be increased.

在图13所示的示例中，在逻辑芯片102的背面上形成有带电膜330e-1和带电膜330e-2。例如，作为负固定电荷膜和正固定电荷膜，带电膜330e-1和带电膜330e-2可以是具有不同特性的膜。另外，带电膜330e-1和带电膜330e-2可以被构造为具有适于芯片的特性的膜，这取决于所形成区域的芯片的特性，例如，芯片是P型芯片还是N型芯片。In the example shown in FIG. 13 , a charging film 330e-1 and a charging film 330e-2 are formed on the back surface of the logic chip 102. For example, as the negative fixed charge film and the positive fixed charge film, the charged film 330e-1 and the charged film 330e-2 may be films having different characteristics. In addition, the charging film 330e-1 and the charging film 330e-2 may be configured as films having characteristics suitable for the chip depending on the characteristics of the chip in the formed region, eg, whether the chip is a P-type chip or an N-type chip.

这样，不管芯片的类型如何，都能够形成带电膜。同样在图13所示的根据第八实施方案的层叠芯片301e中，如同上述实施方案，通过形成带电膜330e，能够抑制经由缺陷发生(增加)泄漏。因此，能够将层叠芯片301e形成得较薄，并且能够实现层叠芯片301e的低高度和小尺寸。In this way, regardless of the type of chip, the charged film can be formed. Also in the laminated chip 301 e according to the eighth embodiment shown in FIG. 13 , as in the above-described embodiment, by forming the charging film 330 e, it is possible to suppress the occurrence (increase) of leakage via defects. Therefore, the laminated chip 301e can be formed thin, and the low height and small size of the laminated chip 301e can be realized.

<第九实施方案><Ninth Embodiment>

图14是示出根据第九实施方案的单层芯片501的构成例的图。FIG. 14 is a diagram showing a configuration example of a single-layer chip 501 according to the ninth embodiment.

在第一至第八实施方案中，尽管以层叠多个芯片的情况为例进行了说明，但是如图14所示，也可以构造一个芯片(单层)。图14所示的单层芯片501被构造为单层，并且在其背面上形成有带电膜330f。In the first to eighth embodiments, although the case where a plurality of chips are stacked has been described as an example, as shown in FIG. 14 , one chip (single layer) may also be constructed. The single-layer chip 501 shown in FIG. 14 is structured as a single layer, and a charging film 330f is formed on the back surface thereof.

同样在图14所示的根据第九实施方案的单层芯片501中，如同上述实施方案，通过形成带电膜330f，能够抑制经由缺陷发生(增加)泄漏。因此，能够将单层芯片501形成得较薄，并且能够实现单层芯片501的低高度和小尺寸。Also in the single-layer chip 501 according to the ninth embodiment shown in FIG. 14 , as in the above-described embodiments, by forming the charging film 330f, it is possible to suppress the occurrence (increase) of leakage through defects. Therefore, the single-layer chip 501 can be formed thin, and the low height and small size of the single-layer chip 501 can be realized.

单层芯片501形成为单层并且形成得较薄，例如20um或更小，因此例如单层芯片501能够用作诸如可穿戴设备等可弯曲设备。The single-layer chip 501 is formed as a single layer and is formed thin, eg, 20 um or less, so that, for example, the single-layer chip 501 can be used as a bendable device such as a wearable device.

根据本技术，即使在芯片(器件)中产生缺陷的情况下，也能够防止由于该缺陷引起的泄漏发生(增加)。因此，芯片(器件)形成得较薄，并且能够实现芯片的低高度和小尺寸。另外，即使在芯片(器件)中形成带电膜，该芯片(器件)的特性也不会变化，因此能够在维持芯片(器件)的特性的情况下获得上述效果。According to the present technology, even when a defect occurs in a chip (device), occurrence (increase) of leakage due to the defect can be prevented. Therefore, the chip (device) is formed thin, and the low height and small size of the chip can be realized. In addition, even if a charged film is formed in a chip (device), the characteristics of the chip (device) do not change, so the above-described effects can be obtained while maintaining the characteristics of the chip (device).

此外，通过在芯片(器件)的背面上形成带电膜，能够形成对芯片(器件)的较深位置没有影响的带电膜。虽然在芯片(器件)的较深位置处，例如形成有与晶体管的源极和漏极相对应的区域，但是在对这些区域有影响的位置处没有形成带电膜，因此不会降低芯片(器件)的可靠性。Furthermore, by forming the charged film on the back surface of the chip (device), it is possible to form a charged film that has no influence on the deep position of the chip (device). Although regions corresponding to the source and drain electrodes of transistors are formed at deep positions of the chip (device), for example, a charged film is not formed at positions affecting these regions, so the chip (device) is not degraded ) reliability.

<第十实施方案><Tenth Embodiment>

在上述第一至第九实施方案中，设置在配线层中的配线使用金属形成。为了防止设置在该配线层中的配线(金属)的扩散，可以包括金属扩散防止膜。In the above-described first to ninth embodiments, the wiring provided in the wiring layer is formed using metal. In order to prevent diffusion of the wiring (metal) provided in the wiring layer, a metal diffusion preventing film may be included.

以下所述的第10实施方案和第11实施方案可以与上述第一至第九实施方案中的任何一个组合。The tenth and eleventh embodiments described below may be combined with any one of the first to ninth embodiments described above.

图15的A至C是示出了在设置有金属扩散防止膜的情况下获得的层叠芯片600a的构成例的图。图15所示的层叠芯片600a将被适当地描述为根据第(10-1)实施方案的层叠芯片600。图15的A示出了层叠芯片600a的断面的构成例，图15的B示出了层叠芯片600a的平面图中的带电膜612a的构成例，图15的C示出了层叠芯片600a的平面图中的金属扩散防止膜622a的构成例。A to C of FIG. 15 are diagrams showing a configuration example of a laminated chip 600 a obtained in a case where a metal diffusion preventing film is provided. The stacked chip 600a shown in FIG. 15 will be appropriately described as the stacked chip 600 according to the (10-1)th embodiment. 15A shows a configuration example of a cross section of the laminated chip 600a, FIG. 15B shows a configuration example of the charging film 612a in a plan view of the laminated chip 600a, and FIG. 15C shows a plan view of the laminated chip 600a An example of the structure of the metal diffusion prevention film 622a.

如图15的A所示，层叠芯片600a形成为具有其中芯片601a和芯片602a层叠的构造。在以下说明中，尽管将以芯片601a的底面和芯片602a的底面以相同程度的尺寸形成的情况为例继续进行说明，但是本技术也能够适用于底面形成为不同尺寸的情况。As shown in A of FIG. 15 , the stacked chip 600a is formed to have a configuration in which a chip 601a and a chip 602a are stacked. In the following description, although the case where the bottom surface of the chip 601a and the bottom surface of the chip 602a are formed with the same size will be continued as an example, the present technology can also be applied to the case where the bottom surfaces are formed with different sizes.

芯片601a具有其中硅基板611和带电膜612a层叠的构造。图15示出了描述所需的芯片601a的构造的一部分，并且将继续描述。说明将与所示出的说明所需的其他部分一起呈现。The chip 601a has a configuration in which a silicon substrate 611 and a charging film 612a are stacked. FIG. 15 shows a portion of the configuration of the chip 601a required for the description, and the description will continue. Instructions will be presented with other parts required for the instructions shown.

芯片602b具有其中配线层621和金属扩散防止膜622a层叠的构造。配线层621包括配线623-1至623-3。例如，金属扩散防止膜622a使用SiN、SiC或SiN等构成。The chip 602b has a configuration in which the wiring layer 621 and the metal diffusion preventing film 622a are laminated. The wiring layer 621 includes wirings 623-1 to 623-3. For example, the metal diffusion preventing film 622a is formed of SiN, SiC, SiN, or the like.

如同上述实施方案，由于在芯片601a的底面上形成有带电膜612a，因此形成其中抑制了经由缺陷的漏电流流动的构造。如图15的B所示，带电膜612a形成在芯片601a的整个底面中。As in the above-described embodiment, since the charging film 612a is formed on the bottom surface of the chip 601a, a configuration is formed in which the flow of leakage current through the defect is suppressed. As shown in B of FIG. 15 , a charging film 612a is formed in the entire bottom surface of the chip 601a.

类似地，如图15的C所示，金属扩散防止膜622a也形成在芯片601a的整个底面上。在图15所示的示例中，带电膜612a和金属扩散防止膜622a以与芯片601a的底面相同程度的尺寸形成。以这种方式，带电膜612a和金属扩散防止膜622a能够形成为相同程度的面积。Similarly, as shown in C of FIG. 15 , a metal diffusion preventing film 622a is also formed on the entire bottom surface of the chip 601a. In the example shown in FIG. 15 , the charging film 612a and the metal diffusion preventing film 622a are formed in the same size as the bottom surface of the chip 601a. In this way, the charging film 612a and the metal diffusion preventing film 622a can be formed in the same degree of area.

在带电膜612a和金属扩散防止膜622a以相同程度的面积形成并且例如，担心金属扩散防止膜622a对带电膜612a的应力、热和氢等的影响的情况下，可以采用图16所示的构造。In the case where the charging film 612a and the metal diffusion preventing film 622a are formed in the same degree of area and, for example, there is concern about the influence of stress, heat, hydrogen, etc. of the metal diffusion preventing film 622a on the charging film 612a, the configuration shown in FIG. 16 can be adopted .

<第(10-2)实施方案><(10-2) Embodiment>

图16示出了根据第(10-2)实施方案的层叠芯片600b的构成。图16的A示出了层叠芯片600b的断面的构成例，图16的B示出了层叠芯片600b的平面图中的带电膜612b的构成例，图16的C示出了层叠芯片600a的平面图中的金属扩散防止膜622b的构成例。FIG. 16 shows the constitution of a stacked chip 600b according to the (10-2) embodiment. A of FIG. 16 shows a configuration example of a cross section of the laminated chip 600b, B of FIG. 16 shows a configuration example of the charging film 612b in a plan view of the laminated chip 600b, and C of FIG. 16 shows a plan view of the laminated chip 600a A configuration example of the metal diffusion prevention film 622b.

根据第(10-2)实施方案的层叠芯片600b的带电膜612b与根据第(10-1)实施方案的层叠芯片600a(图15)的带电膜612a的不同之处在于，其形成面积与金属扩散防止膜622b不同，而其他方面与带电膜612a相似。The charging film 612b of the laminated chip 600b according to the (10-2) embodiment is different from the charging film 612a of the laminated chip 600a ( FIG. 15 ) according to the (10-1) embodiment in that its formation area is the same as that of the metal The diffusion preventing film 622b is different, and is otherwise similar to the charging film 612a.

图16所示的层叠芯片600b的带电膜612b形成在芯片601b的底面的一部分中。在图16所示的示例中，在芯片601b的底面上形成有带电膜612b-1、带电膜612b-2、带电膜612b-3和带电膜612b-4。通过将带电膜612-1、带电膜612b-2、带电膜612b-3和带电膜612b-4的面积相加获得的总面积小于芯片601b的底面的面积，并且小于金属扩散防止膜622b的面积。The charging film 612b of the laminated chip 600b shown in FIG. 16 is formed in a part of the bottom surface of the chip 601b. In the example shown in FIG. 16, a charging film 612b-1, a charging film 612b-2, a charging film 612b-3, and a charging film 612b-4 are formed on the bottom surface of the chip 601b. The total area obtained by adding the areas of the charging film 612-1, the charging film 612b-2, the charging film 612b-3, and the charging film 612b-4 is smaller than the area of the bottom surface of the chip 601b and smaller than the area of the metal diffusion preventing film 622b .

配线623-1位于带电膜612b-1和带电膜612b-2之间，配线623-2位于带电膜612b-2和带电膜612b-3之间，配线623-3位于带电膜612b-3和带电膜612b-4之间。图16所示的带电膜612b在具有其中带电膜612b的一部分在平面图中与配线623重叠的区域的状态下，或者在不具有其中带电膜612b和配线623重叠的区域的状态下形成。The wiring 623-1 is located between the charging film 612b-1 and the charging film 612b-2, the wiring 623-2 is located between the charging film 612b-2 and the charging film 612b-3, and the wiring 623-3 is located between the charging film 612b- 3 and the charged film 612b-4. The charging film 612b shown in FIG. 16 is formed in a state having a region in which a part of the charging film 612b overlaps the wiring 623 in plan view, or a state not having a region in which the charging film 612b and the wiring 623 overlap.

在图16所示的示例中，示出了如下示例：其中通过调整带电膜612b的在图中水平方向上的宽度，使得带电膜612b的面积小于金属扩散防止膜622b的面积。通过调整图中的垂直方向上的宽度，带电膜612b的面积可以小于金属扩散防止膜622b的面积。In the example shown in FIG. 16, an example is shown in which the area of the charging film 612b is made smaller than the area of the metal diffusion preventing film 622b by adjusting the width of the charging film 612b in the horizontal direction in the figure. By adjusting the width in the vertical direction in the drawing, the area of the charging film 612b can be smaller than that of the metal diffusion preventing film 622b.

另外，同样在以下实施方案中，尽管将以通过调整图中的水平方向上的宽度来调整面积的情况为例进行说明，但是也可以通过调整图中的垂直方向上的宽度来调整面积。此外，可以通过调整水平方向和垂直方向上的宽度来调整面积。In addition, also in the following embodiments, although the case where the area is adjusted by adjusting the width in the horizontal direction in the drawing will be described as an example, the area may be adjusted by adjusting the width in the vertical direction in the drawing. In addition, the area can be adjusted by adjusting the width in the horizontal and vertical directions.

以这种方式，通过将带电膜612b的面积和金属扩散防止膜622的面积构造为不同的大小，能够减小金属扩散防止膜622b对带电膜612b的应力等的影响。In this way, by configuring the area of the charging film 612b and the area of the metal diffusion preventing film 622 to have different sizes, the influence of the metal diffusion preventing film 622b on the stress and the like of the charging film 612b can be reduced.

<第(10-3)实施方案><Embodiment (10-3)>

图17是示出根据第(10-3)实施方案的层叠芯片600c的构成例的图。图17的A示出了层叠芯片600c的断面的构成例，图17的B示出了层叠芯片600c的平面图中的带电膜612c的构成例，图17的C示出了层叠芯片600c的平面图中的金属扩散防止膜622c的构成例。FIG. 17 is a diagram showing a configuration example of a laminated chip 600c according to the (10-3) embodiment. A of FIG. 17 shows a configuration example of a cross section of the laminated chip 600c, B of FIG. 17 shows a configuration example of the charging film 612c in a plan view of the laminated chip 600c, and C of FIG. 17 shows a plan view of the laminated chip 600c An example of the structure of the metal diffusion prevention film 622c.

尽管示出了其中上述图16所示的带电膜612b基本上形成在不与形成有配线623的区域重叠的区域中的示例，但是如图17所示，带电膜612c可以形成在与配线623重叠的区域中。Although an example is shown in which the above-described charging film 612b shown in FIG. 16 is formed substantially in a region that does not overlap with the region where the wiring 623 is formed, as shown in FIG. 17 , the charging film 612c may be formed in a region with the wiring 623 in the overlapping area.

图17所示的层叠芯片600c的带电膜612c形成在芯片601c的底面的一部分中。在图17所示的示例中，在芯片601c的底面上形成有带电膜612c-1、带电膜612c-2和带电膜612c-3。通过将带电膜612-1、带电膜612c-2和带电膜612c-3的面积相加获得的总面积小于芯片601c的底面的面积，并且小于金属扩散防止膜622c的面积。The charging film 612c of the laminated chip 600c shown in FIG. 17 is formed in a part of the bottom surface of the chip 601c. In the example shown in FIG. 17, a charging film 612c-1, a charging film 612c-2, and a charging film 612c-3 are formed on the bottom surface of the chip 601c. The total area obtained by adding the areas of the charging film 612-1, the charging film 612c-2, and the charging film 612c-3 is smaller than that of the bottom surface of the chip 601c and smaller than that of the metal diffusion preventing film 622c.

图17所示的带电膜612c形成为其中在平面图中带电膜612c和配线623之间存在重叠区域的状态。在断面中，带电膜612c-1位于配线623-1上，带电膜612c-2位于配线623-2上，带电膜612c-3位于配线623-3上。The charging film 612c shown in FIG. 17 is formed in a state in which an overlapping region exists between the charging film 612c and the wiring 623 in plan view. In the cross section, the charging film 612c-1 is located on the wiring 623-1, the charging film 612c-2 is located on the wiring 623-2, and the charging film 612c-3 is located on the wiring 623-3.

以这种方式，通过将带电膜612c的面积和金属扩散防止膜622c的面积构造为不同的大小，能够减小金属扩散防止膜622c对带电膜612c的应力等的影响。In this way, by configuring the area of the charging film 612c and the area of the metal diffusion preventing film 622c to have different sizes, the influence of the metal diffusion preventing film 622c on the stress and the like of the charging film 612c can be reduced.

像根据第(10-2)实施方案的带电膜612b和根据第(10-3)实施方案的带电膜612c一样，当在芯片601的底面的一部分中设置带电膜612的情况下，作为设置带电膜612的区域，可能形成容易发生泄漏的区域。Like the charging film 612b according to the (10-2) embodiment and the charging film 612c according to the (10-3) embodiment, in the case where the charging film 612 is provided in a part of the bottom surface of the chip 601, as a set charging The region of the film 612 may form a region prone to leakage.

如参照图5所述，可能经由缺陷162在N+扩散层153和耗尽层161之间发生泄漏，并且通过设置带电膜612来抑制这种泄漏。例如，通过在其中可能容易产生缺陷162的区域或耗尽层161等中形成带电膜612，即使带电膜612被构造为仅设置在芯片601的底面的一部分中，也能够不降低抑制泄漏的能力。As described with reference to FIG. 5 , leakage may occur between the N+ diffusion layer 153 and the depletion layer 161 via the defect 162 , and such leakage is suppressed by providing the charging film 612 . For example, by forming the charging film 612 in a region where the defect 162 is likely to be easily generated or the depletion layer 161 or the like, even if the charging film 612 is configured to be provided only in a part of the bottom surface of the chip 601, the ability to suppress leakage can not be reduced .

<第(10-4)实施方案><Embodiment (10-4)>

图18是示出根据第(10-4)实施方案的层叠芯片600d的构成的图。图18的A示出了层叠芯片600d的断面的构成例，图18的B示出了层叠芯片600d的平面图中的带电膜612d的构成例，图18的C示出了层叠芯片600d的平面图中的金属扩散防止膜622d的构成例。FIG. 18 is a diagram showing the configuration of a stacked chip 600d according to the (10-4)th embodiment. A of FIG. 18 shows a configuration example of the cross section of the laminated chip 600d, B of FIG. 18 shows a configuration example of the charging film 612d in the plan view of the laminated chip 600d, and C of FIG. 18 shows the plan view of the laminated chip 600d A configuration example of the metal diffusion preventing film 622d.

在第(10-1)至第(10-3)实施方案中，以通过将带电膜612的面积形成为小于金属扩散防止膜622的面积来形成具有不同面积的带电膜612和金属扩散防止膜622的情况为例进行了说明。在第(10-4)实施方案中，将以通过将金属扩散防止膜622的面积形成为小于带电膜612的面积来形成具有不同面积的带电膜612和金属扩散防止膜622的情况为例进行说明。In the (10-1)th to (10-3)th embodiments, the charging film 612 and the metal diffusion preventing film having different areas are formed by forming the area of the charging film 612 to be smaller than that of the metal diffusion preventing film 622 The case of 622 is described as an example. In the (10-4) embodiment, the case where the charging film 612 and the metal diffusion preventing film 622 having different areas are formed by forming the area of the metal diffusion preventing film 622 to be smaller than that of the charging film 612 will be taken as an example. illustrate.

图18所示的层叠芯片600d的金属扩散防止膜622d形成在芯片602d的底面的一部分中。在图18所示的示例中，在芯片602d的底面上形成有金属扩散防止膜622d-1、金属扩散防止膜622d-2和金属扩散防止膜622d-3。通过将金属扩散防止膜622d-1、金属扩散防止膜622d-2和金属扩散防止膜622d-3的面积相加获得的总面积小于芯片602d的底面的面积，并且小于带电膜612d的面积。The metal diffusion preventing film 622d of the laminated chip 600d shown in FIG. 18 is formed in a part of the bottom surface of the chip 602d. In the example shown in FIG. 18, a metal diffusion prevention film 622d-1, a metal diffusion prevention film 622d-2, and a metal diffusion prevention film 622d-3 are formed on the bottom surface of the chip 602d. The total area obtained by adding the areas of the metal diffusion prevention film 622d-1, the metal diffusion prevention film 622d-2, and the metal diffusion prevention film 622d-3 is smaller than that of the bottom surface of the chip 602d and smaller than that of the charging film 612d.

图18所示的金属扩散防止膜622d形成为其中在平面图中金属扩散防止膜622d和配线623之间存在重叠区域的状态。金属扩散防止膜622d是设置成使得构成配线623的金属不扩散的膜，因此形成在与配线623重叠的位置处。在断面中，金属扩散防止膜622d-1位于配线623-1的下方，金属扩散防止膜622d-2位于配线623-2的下方，金属扩散防止膜622d-3位于配线623-3的下方。The metal diffusion prevention film 622d shown in FIG. 18 is formed in a state in which an overlapping region exists between the metal diffusion prevention film 622d and the wiring 623 in plan view. The metal diffusion preventing film 622 d is a film provided so that the metal constituting the wiring 623 is not diffused, and thus is formed at a position overlapping the wiring 623 . In the cross section, the metal diffusion prevention film 622d-1 is located under the wiring 623-1, the metal diffusion prevention film 622d-2 is located under the wiring 623-2, and the metal diffusion prevention film 622d-3 is located under the wiring 623-3. below.

以这种方式，通过将金属扩散防止膜622d的面积和带电膜612d的面积构造为不同的大小，能够减小金属扩散防止膜622d对带电膜612d的应力等的影响。In this way, by configuring the area of the metal anti-diffusion film 622d and the area of the charging film 612d to have different sizes, the influence of the metal anti-diffusion film 622d on the stress and the like of the charging film 612d can be reduced.

<第(10-5)实施方案><Embodiment (10-5)>

图19是示出根据第(10-5)实施方案的层叠芯片600e的构成的图。图19的A示出了层叠芯片600e的断面的构成例，图19的B示出了层叠芯片600e的平面图中的带电膜612e的构成例，图19的C示出了层叠芯片600e的平面图中的金属扩散防止膜622e的构成例，图19的D示出了层叠芯片600e的平面图中的钝化膜631的构成例。FIG. 19 is a diagram showing the configuration of a stacked chip 600e according to the (10-5)th embodiment. A of FIG. 19 shows a configuration example of a cross section of the laminated chip 600e, B of FIG. 19 shows a configuration example of the charging film 612e in a plan view of the laminated chip 600e, and C of FIG. 19 shows a plan view of the laminated chip 600e A configuration example of the metal diffusion preventing film 622e shown in FIG. 19D shows a configuration example of the passivation film 631 in the plan view of the laminated chip 600e.

层叠芯片600e与根据第(10-1)实施方案至第(10-4)实施方案的层叠芯片600a至600d的不同之处在于，其包括钝化膜631。尽管图19示出了在根据第(10-4)实施方案的层叠芯片600d中设置钝化膜631的示例，但是也可以采用其中在根据第(10-1)实施方案至第(10-3)实施方案的层叠芯片600a至600c中设置钝化膜631的构造。The laminated chip 600 e is different from the laminated chips 600 a to 600 d according to the (10-1) embodiment to the (10-4) embodiment in that it includes a passivation film 631 . Although FIG. 19 shows an example in which the passivation film 631 is provided in the laminated chip 600d according to the (10-4) embodiment, it is also possible to adopt the example in which the passivation film 631 is provided in the laminated chip 600d according to the (10-1) embodiment to the (10-3) embodiment. ) configuration in which the passivation film 631 is provided in the stacked chips 600a to 600c of the embodiment.

钝化膜631层叠在金属扩散防止膜622e上。钝化膜631是为了防止外部空气的影响、污染物的附着等而设置的膜，并且钝化膜631例如能够使用氮化硅(SiN)、氧化硅(SiO₂)或氮氧化硅(SiON)等的单层膜或它们的层叠膜构成。The passivation film 631 is laminated on the metal diffusion preventing film 622e. The passivation film 631 is a film provided to prevent the influence of outside air, the adhesion of contaminants, and the like, and the passivation film 631 can use, for example, silicon nitride (SiN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiON) etc. single-layer films or their laminated films.

钝化膜631以相同尺寸形成在与金属扩散防止膜622e相同的位置处。在图19所示的示例中，钝化膜631-1层叠在金属扩散防止膜622e-1上，钝化膜631-2层叠在金属扩散防止膜622e-2上，钝化膜631-3层叠在金属扩散防止膜622e-3上。The passivation film 631 is formed in the same size at the same position as the metal diffusion preventing film 622e. In the example shown in FIG. 19, the passivation film 631-1 is laminated on the metal diffusion prevention film 622e-1, the passivation film 631-2 is laminated on the metal diffusion prevention film 622e-2, and the passivation film 631-3 is laminated On the metal diffusion preventing film 622e-3.

尽管未示出，但是例如，如同图17所示的层叠芯片600c的金属扩散防止膜622c的情况，在金属扩散防止膜622c形成在芯片602c的整个底面上的构造中设置钝化膜631的情况下，钝化膜631也形成在芯片602c的整个底面上。Although not shown, for example, as in the case of the metal diffusion preventing film 622c of the laminated chip 600c shown in FIG. 17 , in the case where the passivation film 631 is provided in a configuration in which the metal diffusion preventing film 622c is formed on the entire bottom surface of the chip 602c Next, a passivation film 631 is also formed on the entire bottom surface of the chip 602c.

以这种方式，通过将金属扩散防止膜622e和钝化膜631的面积形成为彼此相等并且将金属扩散防止膜622e和钝化膜631各自的面积与带电膜612e的面积构造为不同的尺寸，能够减小金属扩散防止膜622e和钝化膜631对带电膜612e的应力等的影响。In this way, by forming the areas of the metal diffusion preventing film 622e and the passivation film 631 to be equal to each other and configuring the respective areas of the metal diffusion preventing film 622e and the passivation film 631 and the area of the charging film 612e to be different in size, The influence of the metal diffusion preventing film 622e and the passivation film 631 on the stress and the like of the charging film 612e can be reduced.

<第11实施方案><11th Embodiment>

图20是示出根据第(11-1)实施方案的芯片701a的构成例的图。图20的A示出了芯片701a的断面的构成例，图20的B示出了芯片701a的平面图中的带电膜713a的构成例，图20的C示出了芯片701a的平面图中的金属扩散防止膜714a的构成例。图20示出了芯片701a的一部分，并且层叠芯片可以通过层叠图中未示出的芯片来构成。FIG. 20 is a diagram showing a configuration example of a chip 701 a according to the (11-1) embodiment. 20A shows a configuration example of a cross section of the chip 701a, FIG. 20B shows a configuration example of a charging film 713a in a plan view of the chip 701a, and FIG. 20C shows a metal diffusion in a plan view of the chip 701a A configuration example of the prevention film 714a. FIG. 20 shows a part of the chip 701a, and the stacked chip may be constituted by stacking chips not shown in the figure.

在图20所示的芯片701a中，层叠有配线层711、硅基板712、带电膜713a和金属扩散防止膜714a。金属扩散防止膜714a是为了使构成形成在配线层711中的配线715-1和配线715-2的金属不扩散而设置的膜，并且金属扩散防止膜714a形成在图20所示的芯片701a中的底面和侧面上。In the chip 701a shown in FIG. 20, a wiring layer 711, a silicon substrate 712, a charging film 713a, and a metal diffusion preventing film 714a are laminated. The metal diffusion preventing film 714a is a film provided to prevent the metal constituting the wiring 715-1 and the wiring 715-2 formed in the wiring layer 711 from diffusing, and the metal diffusion preventing film 714a is formed as shown in FIG. 20 . on the bottom and sides of the chip 701a.

通过层叠配线层711和硅基板712，在层叠的基板上层叠带电膜713a，并且在层叠带电膜713a之后在底面和侧面上形成金属扩散防止膜714a，来制造芯片701a。因此，如图20所示，形成了其中带电膜713a和金属扩散防止膜714a层叠的构造。The chip 701a is manufactured by stacking the wiring layer 711 and the silicon substrate 712, stacking the charging film 713a on the stacked substrate, and forming the metal diffusion preventing film 714a on the bottom and side surfaces after stacking the charging film 713a. Therefore, as shown in FIG. 20, a configuration in which the charging film 713a and the metal diffusion preventing film 714a are stacked is formed.

在图20所示的示例中，带电膜713a的面积和形成在芯片701a(硅基板712)的底面上的金属扩散防止膜714a的面积以与芯片701a的底面相同程度的尺寸形成。这样，带电膜713a和金属扩散防止膜714a能够形成为相同程度的面积。In the example shown in FIG. 20 , the area of the charging film 713a and the area of the metal diffusion preventing film 714a formed on the bottom surface of the chip 701a (silicon substrate 712) are formed with approximately the same size as the bottom surface of the chip 701a. In this way, the charging film 713a and the metal diffusion preventing film 714a can be formed to have the same area.

在带电膜713a和金属扩散防止膜714a形成为相同程度的面积，并且例如担心金属扩散防止膜714a对带电膜713a的应力、热和氢等的影响的情况下，可以采用如图21所示的构造。In the case where the charging film 713a and the metal diffusion preventing film 714a are formed to have the same area and, for example, there is concern about the influence of stress, heat, hydrogen, etc. on the charging film 713a by the metal diffusion preventing film 714a, the method shown in FIG. 21 can be used. structure.

<第(11-2)实施方案><(11-2) Embodiment>

图21示出了根据第(11-2)实施方案的芯片701b的构成。图21的A示出了芯片701b的断面的构成例，图21的B示出了芯片701b的平面图中的带电膜713b的构成例，图21的C示出了芯片701b的平面图中的金属扩散防止膜714b的构成例。FIG. 21 shows the configuration of a chip 701b according to the (11-2) embodiment. 21A shows a configuration example of a cross section of the chip 701b, FIG. 21B shows a configuration example of a charging film 713b in a plan view of the chip 701b, and FIG. 21C shows a metal diffusion in a plan view of the chip 701b A configuration example of the prevention film 714b.

根据第(11-2)实施方案的芯片701b的带电膜713b与根据第(11-1)实施方案的芯片701a(图20)的带电膜713b的不同之处在于，其形成面积与金属扩散防止膜714b不同，并且其他方面相似。The charging film 713b of the chip 701b according to the (11-2) embodiment is different from the charging film 713b of the chip 701a ( FIG. 20 ) according to the (11-1) embodiment in that its formation area and metal diffusion prevention Membrane 714b is different and otherwise similar.

图21所示的芯片701b的金属扩散防止膜714b形成在芯片701b(硅基板712)的底面的整个面上。带电膜713b形成在芯片701b的底面的一部分中。在图21所示的示例中，带电膜713b形成在芯片701b的底面上。该带电膜713b的面积小于芯片701b的底面的面积，并且小于金属扩散防止膜714b的面积。The metal diffusion preventing film 714b of the chip 701b shown in FIG. 21 is formed on the entire bottom surface of the chip 701b (silicon substrate 712). The charging film 713b is formed in a part of the bottom surface of the chip 701b. In the example shown in FIG. 21, the charging film 713b is formed on the bottom surface of the chip 701b. The area of the charging film 713b is smaller than the area of the bottom surface of the chip 701b and smaller than the area of the metal diffusion preventing film 714b.

这样，通过将带电膜713b的面积和金属扩散防止膜714的面积构造为不同的尺寸，能够减小金属扩散防止膜714a对带电膜713a的应力等的影响。In this way, by configuring the area of the charging film 713b and the area of the metal diffusion preventing film 714 to have different sizes, the influence of the metal diffusion preventing film 714a on the stress and the like of the charging film 713a can be reduced.

尽管图21示出了在芯片701b的中心形成带电膜713b的示例，但是例如，如同图16所示的带电膜612b，带电膜713b可以设置成使得在平面图中没有与配线715重叠的区域，或者，如同图17所示的带电膜612c，带电膜713b可以设置成使得在平面图中存在与配线715重叠的区域。Although FIG. 21 shows an example in which the charging film 713b is formed at the center of the chip 701b, for example, like the charging film 612b shown in FIG. 16, the charging film 713b may be provided such that there is no area overlapping the wiring 715 in plan view, Alternatively, like the charging film 612c shown in FIG. 17, the charging film 713b may be provided such that there is a region overlapping the wiring 715 in plan view.

<第(11-3)实施方案><Embodiment (11-3)>

在图22中示出了根据第(11-3)实施方案的芯片701c的构成。图22的A示出了芯片701c的断面的构成例，图22的B示出了芯片701c的平面图中的带电膜713c的构成例，图22的C示出了芯片701c的平面图中的金属扩散防止膜714c的构成例。The constitution of the chip 701c according to the (11-3)th embodiment is shown in FIG. 22 . 22A shows a configuration example of a cross section of the chip 701c, FIG. 22B shows a configuration example of a charging film 713c in a plan view of the chip 701c, and FIG. 22C shows a metal diffusion in a plan view of the chip 701c A configuration example of the prevention film 714c.

根据第(11-3)实施方案的芯片701c的金属扩散防止膜714c与根据第(11-1)实施方案的芯片701a(图20)的金属扩散防止膜714a的不同之处在于，其形成面积与带电膜713c不同，并且其他方面相同。The metal diffusion preventing film 714c of the chip 701c according to the (11-3) embodiment is different from the metal diffusion preventing film 714a of the chip 701a ( FIG. 20 ) according to the (11-1) embodiment in that its formation area Different from the charged film 713c, and otherwise the same.

图22所示的芯片701c的带电膜713c形成在芯片701c的底面的整个面上。金属扩散防止膜714c形成在芯片701c的底面的一部分中。在图22所示的示例中，金属扩散防止膜714a形成在芯片701c的底面的中心处。该金属扩散防止膜714a的面积小于芯片701c的底面的面积，并且小于带电膜713c的面积。The charging film 713c of the chip 701c shown in FIG. 22 is formed on the entire bottom surface of the chip 701c. A metal diffusion preventing film 714c is formed in a part of the bottom surface of the chip 701c. In the example shown in FIG. 22, the metal diffusion preventing film 714a is formed at the center of the bottom surface of the chip 701c. The area of the metal diffusion preventing film 714a is smaller than the area of the bottom surface of the chip 701c and smaller than the area of the charging film 713c.

这样，通过将带电膜713c的面积和金属扩散防止膜714c的面积构造为不同的尺寸，能够减小金属扩散防止膜714c对带电膜713c的应力等的影响。In this way, by configuring the area of the charging film 713c and the area of the metal diffusion preventing film 714c to have different sizes, the influence of the metal diffusion preventing film 714c on the stress and the like of the charging film 713c can be reduced.

<内窥镜手术系统的应用><Application of endoscopic surgical system>

根据本公开的技术(本技术)可以应用于各种产品。例如，根据本公开的技术可以应用于内窥镜手术系统。The technology according to the present disclosure (the present technology) can be applied to various products. For example, techniques according to the present disclosure may be applied to endoscopic surgical systems.

图23是示出了应用根据本公开的技术(本技术)的内窥镜手术系统的示意性构成的示例的图。23 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology according to the present disclosure (the present technology) is applied.

图23示出了其中手术者(医生)11131通过使用内窥镜手术系统11000对病床11133上的患者11132进行手术的状态。如图所示，内窥镜手术系统11000包括内窥镜11100、诸如气腹管11111或能量治疗工具11112等其他手术工具11110、支撑内窥镜11100的支撑臂装置11120和安装有用于内窥镜手术的各种装置的推车11200。FIG. 23 shows a state in which an operator (doctor) 11131 performs surgery on a patient 11132 on a hospital bed 11133 by using the endoscopic surgery system 11000. As shown, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 or an energy therapy tool 11112, a support arm arrangement 11120 that supports the endoscope 11100, and a support arm device 11120 that is mounted for the endoscope Cart 11200 for various devices for surgery.

内窥镜11100包括透镜镜筒11101和摄像机头11102，该透镜镜筒的从远端起的预定长度的区域插入患者11132的体腔内，该摄像机头连接到透镜镜筒11101的近端。在示出的示例中，示出了配置为具有刚性透镜镜筒11101的所谓的刚性内窥镜的内窥镜11100，但是内窥镜11100也可以配置为具有柔性透镜镜筒的所谓的柔性内窥镜。The endoscope 11100 includes a lens barrel 11101 whose region of a predetermined length from the distal end is inserted into a body cavity of a patient 11132 and a camera head 11102 connected to the proximal end of the lens barrel 11101 . In the illustrated example, the endoscope 11100 is shown configured as a so-called rigid endoscope with a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope with a flexible lens barrel looking glass.

在透镜镜筒11101的远端设置有插入有物镜的开口。光源装置11203连接到内窥镜11100，并且由光源装置11203生成的光通过延伸到透镜镜筒11101内部的光导引导到透镜镜筒的远端，并经由物镜将光照射到患者11132的体腔内的观察对象上。内窥镜11100可以是直视内窥镜、斜视内窥镜或侧视内窥镜。An opening into which an objective lens is inserted is provided at the distal end of the lens barrel 11101 . The light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the distal end of the lens barrel through a light guide extending inside the lens barrel 11101, and irradiates the light into the body cavity of the patient 11132 via the objective lens. on the observation object. The endoscope 11100 may be a direct-viewing endoscope, a squint-viewing endoscope, or a side-viewing endoscope.

光学系统和成像元件设置在摄像机头11102的内部，并且来自观察对象的反射光(观察光)通过光学系统会聚在成像元件上。通过成像元件对观察光进行光电转换，并且生成与观察光相对应的电信号，即，与观察图像相对应的图像信号。图像信号作为原始(RAW)数据传输到相机控制单元(CCU)11201。An optical system and an imaging element are provided inside the camera head 11102, and reflected light (observation light) from an observation object is condensed on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element, and an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image is generated. The image signal is transmitted to the camera control unit (CCU) 11201 as raw (RAW) data.

CCU 11201由中央处理器(CPU)、图形处理器(GPU)等构成，并且集中控制内窥镜11100和显示装置11202的操作。此外，例如，CCU 11201接收来自摄像机头11102的图像信号，并且对图像信号执行诸如显影处理(去马赛克处理)等各种图像处理，以显示基于图像信号的图像。The CCU 11201 is constituted by a central processing unit (CPU), a graphics processing unit (GPU), and the like, and centrally controls the operations of the endoscope 11100 and the display device 11202 . Further, for example, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing such as development processing (demosaic processing) on the image signal to display an image based on the image signal.

显示装置11202在CCU 11201的控制下显示基于经过CCU 11201的图像处理的图像信号的图像。The display device 11202 displays an image based on an image signal subjected to image processing by the CCU 11201 under the control of the CCU 11201 .

例如，光源装置11203由诸如发光二极管(LED)等光源构成，并且在对手术部位等进行成像时将照射光提供给内窥镜11100。For example, the light source device 11203 is constituted by a light source such as a light emitting diode (LED), and supplies irradiation light to the endoscope 11100 when imaging a surgical site or the like.

输入装置11204是内窥镜手术系统11000的输入接口。使用者可以经由输入装置11204向内窥镜手术系统11000输入各种类型的信息或指令。例如，使用者输入改变内窥镜11100的成像条件(照射光的类型、放大率、焦距等)的指令等。The input device 11204 is an input interface of the endoscopic surgery system 11000 . The user may input various types of information or instructions to the endoscopic surgery system 11000 via the input device 11204 . For example, the user inputs an instruction or the like to change the imaging conditions of the endoscope 11100 (type of irradiation light, magnification, focal length, etc.).

治疗工具控制装置11205控制能量治疗工具11112的驱动以烧灼或切开组织、封闭血管等。气腹装置11206通过气腹管11111将气体供给到患者11132的体腔内以使体腔膨胀，以便确保内窥镜11100的视野并确保手术者的工作空间。记录器11207是能够记录与手术相关的各种信息的装置。打印机11208是能够以如文本、图像或图形等各种形式打印与手术相关的各种信息的装置。The treatment tool control device 11205 controls the actuation of the energy treatment tool 11112 to cauterize or cut tissue, seal blood vessels, and the like. The pneumoperitoneum device 11206 supplies gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity so as to secure the field of view of the endoscope 11100 and secure the working space of the operator. The recorder 11207 is a device capable of recording various information related to surgery. The printer 11208 is a device capable of printing various information related to surgery in various forms such as text, images, or graphics.

例如，将照射光提供到内窥镜11100以对手术部位进行成像的光源装置11203可以由LED、激光光源或通过组合它们获得的白光光源构成。在白光光源由RGB激光光源的组合构成的情况下，可以高精度地控制每种颜色(每个波长)的输出强度和输出时序。因此，光源装置11203可以调整所拍摄的图像的白平衡。在这种情况下，通过以时分的方式利用来自RGB激光光源的激光照射观察对象，并与照射时序同步地控制摄像机头11102的成像元件的驱动，也能够以时分的方式拍摄与RGB相对应的图像。根据这种方法，即使在成像元件中没有设置滤色器的情况下，也可以获得彩色图像。For example, the light source device 11203 that supplies the irradiation light to the endoscope 11100 to image the surgical site may be constituted by an LED, a laser light source, or a white light source obtained by combining them. In the case where the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision. Therefore, the light source device 11203 can adjust the white balance of the captured image. In this case, by irradiating the observation object with laser light from the RGB laser light source in a time-division manner, and controlling the driving of the imaging element of the camera head 11102 in synchronization with the irradiation timing, it is also possible to photograph images corresponding to RGB in a time-division manner. image. According to this method, a color image can be obtained even in the case where no color filter is provided in the imaging element.

可以控制光源装置11203的驱动以便每隔预定的时间改变将要输出的光的强度。通过与光强度的改变时序同步地控制摄像机头11102的成像元件的驱动、以时分的方式获取图像并合成图像，可以产生没有所谓的黑点(black spots)和白点(white spots)的高动态范围的图像。The driving of the light source device 11203 can be controlled so as to change the intensity of light to be output every predetermined time. By controlling the driving of the imaging element of the camera head 11102 in synchronization with the change timing of the light intensity, acquiring images in a time-division manner, and synthesizing the images, it is possible to generate high dynamics without so-called black spots and white spots range of images.

光源装置11203可以配置成能够提供对应于特殊光观察的预定波长带的光。例如，在特殊光观察中，通过利用身体组织的光吸收的波长依赖性，照射与普通观察时的照射光(换句话说，白光)的波长带的相比更窄的波长带的光，以高对比度对诸如黏膜表层的血管等预定组织执行所谓的窄带光观察(窄带光成像)。可替代地，在特殊光观察中，可以执行用于通过照射激发光生成的荧光获得图像的荧光观察。在荧光观察中，例如，可以将激发光照射在身体组织上以观察来自身体组织的荧光(自发荧光观察)，或将诸如吲哚菁绿(ICG)等试剂局部注射到身体组织并将与试剂的荧光波长相对应的激发光照射在身体组织，从而获得荧光图像。光源装置11203可以配置成能够提供与这种特殊光观察相对应的窄带光和/或激发光。The light source device 11203 may be configured to be able to provide light of a predetermined wavelength band corresponding to special light observation. For example, in special light observation, by utilizing the wavelength dependence of light absorption by body tissue, light of a narrower wavelength band than that of irradiation light (in other words, white light) in ordinary observation is irradiated to High contrast performs so-called narrow-band light observation (narrow-band light imaging) on predetermined tissues such as blood vessels of the mucosal surface. Alternatively, in special light observation, fluorescence observation for obtaining an image by irradiating fluorescence generated by excitation light may be performed. In fluorescence observation, for example, excitation light may be irradiated on body tissue to observe fluorescence from body tissue (autofluorescence observation), or an agent such as indocyanine green (ICG) may be locally injected into body tissue and will interact with the agent The excitation light corresponding to the fluorescence wavelength is irradiated on the body tissue, thereby obtaining a fluorescence image. The light source device 11203 may be configured to be able to provide narrow-band light and/or excitation light corresponding to this particular light observation.

图24是示出了图23中示出的摄像机头11102和CCU 11201的功能配置构成的框图。FIG. 24 is a block diagram showing the functional configuration constitution of the camera head 11102 and the CCU 11201 shown in FIG. 23 .

摄像机头11102具有透镜单元11401、成像单元11402、驱动单元11403、通信单元11404和摄像机头控制单元11405。CCU 11201具有通信单元11411、图像处理单元11412和控制单元11413。摄像机头11102和CCU 11201通过传输电缆11400彼此可通信地连接。The camera head 11102 has a lens unit 11401 , an imaging unit 11402 , a driving unit 11403 , a communication unit 11404 , and a camera head control unit 11405 . The CCU 11201 has a communication unit 11411 , an image processing unit 11412 and a control unit 11413 . The camera head 11102 and the CCU 11201 are communicably connected to each other through a transmission cable 11400 .

透镜单元11401是设置在与透镜镜筒11101的连接部处的光学系统。从透镜镜筒11101的远端接收的观察光被引导到摄像机头11102并入射到透镜单元11401上。透镜单元11401通过组合包括变焦透镜和聚焦透镜的多个透镜来构成。The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101 . The observation light received from the distal end of the lens barrel 11101 is guided to the camera head 11102 and incident on the lens unit 11401 . The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

构成成像单元11402的成像元件的数量可以是一个(所谓的单板型)或多个(所谓的多板型)。例如，当成像单元11402配置为多板型的情况下，各成像元件可以生成与各个RGB相对应的图像信号，并且可以通过合成这些图像信号来获得彩色图像。可选择地，成像单元11402可以包括用于获取与三维(3D)显示相对应的右眼图像信号和左眼图像信号的一对成像元件。通过执行3D显示，手术者11131能够更精确地掌握手术部位中活体组织的深度。当成像单元11402配置为多板型的情况下，对应于各个成像元件可以设置多个透镜单元11401的系统。The number of imaging elements constituting the imaging unit 11402 may be one (so-called single-plate type) or plural (so-called multi-plate type). For example, when the imaging unit 11402 is configured as a multi-plate type, each imaging element can generate an image signal corresponding to each RGB, and a color image can be obtained by synthesizing these image signals. Alternatively, the imaging unit 11402 may include a pair of imaging elements for acquiring a right-eye image signal and a left-eye image signal corresponding to a three-dimensional (3D) display. By performing 3D display, the operator 11131 can more accurately grasp the depth of the living tissue in the surgical site. When the imaging unit 11402 is configured as a multi-plate type, a system of a plurality of lens units 11401 may be provided corresponding to each imaging element.

成像单元11402不一定设置在摄像机头11102中。例如，成像单元11402可以设置在透镜镜筒11101内部物镜的正后方。The imaging unit 11402 is not necessarily provided in the camera head 11102. For example, the imaging unit 11402 may be disposed right behind the objective lens inside the lens barrel 11101.

驱动单元11403由致动器构成，并且在摄像机头控制单元11405的控制下使透镜单元11401的变焦透镜和聚焦透镜沿光轴移动预定的距离。以这种方式，可以适当地调整由成像单元11402拍摄的图像的放大率和焦点。The driving unit 11403 is constituted by an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405 . In this way, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

通信单元11404由用于与CCU 11201之间发送或接收各种信息的通信装置构成。通信单元11404经由传输电缆11400将从成像单元11402获取的图像信号作为RAW数据传输到CCU 11201。The communication unit 11404 is composed of communication means for transmitting or receiving various kinds of information with the CCU 11201 . The communication unit 11404 transmits the image signal acquired from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

通信单元11404从CCU 11201接收用于控制摄像机头11102的驱动的控制信号，并将控制信号提供给摄像机头控制单元11405。例如，控制信号包括与成像条件有关的信息，诸如指定所拍摄的图像的帧速率的信息、指定拍摄图像时的曝光值的信息和/或指定所拍摄的图像的放大率和焦点的信息。The communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 , and supplies the control signal to the camera head control unit 11405 . For example, the control signal includes information related to imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at which the image was captured, and/or information specifying the magnification and focus of the captured image.

诸如帧速率、曝光值、放大率或焦点等成像条件可以由使用者适当指定或可以由CCU 11201的控制单元11413基于获取的图像信号自动设定。在后一种情况下，所谓的自动曝光(AE)功能、自动聚焦(AF)功能和自动白平衡(AWB)功能安装在内窥镜11100中。Imaging conditions such as frame rate, exposure value, magnification, or focus may be appropriately designated by the user or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, a so-called automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are installed in the endoscope 11100 .

摄像机头控制单元11405基于经由通信单元11404从CCU 11201接收的控制信号控制摄像机头11102的驱动。The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404 .

通信单元11411由用于与摄像机头11102之间发送和接收各种类型的信息的通信装置构成。通信单元11411接收经由传输电缆11400从摄像机头11102传输的图像信号。The communication unit 11411 is constituted by communication means for transmitting and receiving various types of information to and from the camera head 11102 . The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400 .

此外，通信单元11411将用于控制摄像机头11102的驱动的控制信号传输到摄像机头11102。可以通过电通信、光学通信等传输图像信号和控制信号。Further, the communication unit 11411 transmits a control signal for controlling the driving of the camera head 11102 to the camera head 11102 . The image signal and the control signal may be transmitted by electrical communication, optical communication, or the like.

图像处理单元11412对从摄像机头11102传输的作为RAW数据的图像信号执行各种图像处理。The image processing unit 11412 performs various image processing on the image signal transmitted from the camera head 11102 as RAW data.

控制单元11413执行与通过内窥镜11100对手术部位等进行成像和通过对手术部位等进行成像所获得的拍摄图像的显示相关的各种控制。例如，控制单元11413生成用于控制摄像机头11102的驱动的控制信号。The control unit 11413 performs various controls related to imaging of the surgical site and the like by the endoscope 11100 and display of captured images obtained by imaging the surgical site and the like. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

控制单元11413使显示装置11202基于经过图像处理单元11412的图像处理的图像信号显示其中示出了手术部位等的拍摄的图像。此时，控制单元11413可以通过使用各种图像识别技术来识别拍摄的图像中的各种物体。例如，控制单元11413可以通过检测拍摄的图像中所包含的物体的边缘的形状、颜色等来识别诸如手术钳等手术工具、特定的活体部位、出血、使用能量治疗工具11112时的雾等。当使显示装置11202显示拍摄的图像时，控制单元11413可以使用识别结果在手术部位的图像上叠加显示各种手术支持信息。通过叠加显示手术支持信息并且呈现给手术者11131，可以减轻手术者11131的负担并且使手术者11131可以可靠地进行手术。The control unit 11413 causes the display device 11202 to display, based on the image signal subjected to the image processing by the image processing unit 11412, the captured image in which the surgical site and the like are shown. At this time, the control unit 11413 can recognize various objects in the captured image by using various image recognition techniques. For example, the control unit 11413 can identify a surgical tool such as forceps, a specific living body part, bleeding, fog when the energy therapy tool 11112 is used, and the like by detecting the shape, color, etc. of the edge of the object contained in the captured image. When causing the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to superimpose and display various surgical support information on the image of the surgical site. By superimposing and displaying the surgical support information and presenting it to the operator 11131, the burden on the operator 11131 can be reduced and the operator 11131 can perform surgery reliably.

将摄像机头11102和CCU 11201彼此连接的传输电缆11400是支持电信号通信的电信号电缆、支持光学通信的光纤或其复合电缆。The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electrical signal cable supporting electrical signal communication, an optical fiber supporting optical communication, or a composite cable thereof.

这里，在附图所示的示例中，尽管使用传输线缆11400以有线的方式执行通信，但是也可以以无线的方式执行摄像机头11102与CCU 11201之间的通信。Here, in the example shown in the drawing, although the communication is performed in a wired manner using the transmission cable 11400, the communication between the camera head 11102 and the CCU 11201 may be performed in a wireless manner.

<移动体的应用><Applications for moving objects>

根据本公开的技术(本技术)可以应用于各种产品。例如，根据本公开的技术可以实现为安装在如汽车、电动汽车、混合动力电动汽车、摩托车、自行车、个人移动装置、飞机、无人机、船、机器人等任何类型的移动体上的装置。The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be implemented as a device mounted on any type of moving body such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobile device, airplane, drone, boat, robot, etc. .

图25是示出了作为可以应用根据本公开的技术的移动体控制系统的示例的车辆控制系统的示意性构成示例的框图。25 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

车辆控制系统12000包括通过通信网络12001彼此连接的多个电子控制单元。在图72示出的示例中，车辆控制系统12000包括驱动系统控制单元12010、车身系统控制单元12020、车外信息检测单元12030、车内信息检测单元12040和综合控制单元12050。此外，作为综合控制单元12050的功能配置，示出了微型计算机12051、声音/图像输出单元12052和车载网络接口(I/F)12053。The vehicle control system 12000 includes a plurality of electronic control units connected to each other through a communication network 12001 . In the example shown in FIG. 72 , the vehicle control system 12000 includes a drive system control unit 12010 , a body system control unit 12020 , an exterior information detection unit 12030 , an interior information detection unit 12040 , and an integrated control unit 12050 . Further, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound/image output unit 12052, and an in-vehicle network interface (I/F) 12053 are shown.

驱动系统控制单元12010根据各种程序控制与车辆的驱动系统相关的装置的操作。例如，驱动系统控制单元12010充当以下装置的控制装置：如内燃机或驱动马达等用于产生车辆的驱动力的驱动力产生装置、用于将驱动力传递至车轮的驱动力传递机构、用于调整车辆的转向角的转向机构、用于产生车辆的制动力的制动装置等。The drive system control unit 12010 controls operations of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a driving force generating device such as an internal combustion engine or a drive motor for generating a driving force of the vehicle, a driving force transmitting mechanism for transmitting the driving force to the wheels, a driving force transmitting mechanism for adjusting A steering mechanism for the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

车身系统控制单元12020根据各种程序控制装备在车身上的各种装置的操作。例如，车身系统控制单元12020充当以下装置的控制装置：无钥匙进入系统、智能钥匙系统、电动车窗装置或如前照灯、后照灯、刹车灯、转向灯或雾灯等各种灯。在这种情况下，可以将从替代钥匙的便携式装置发送的无线电波或各种开关的信号输入到车身系统控制单元12020。车身系统控制单元12020接收无线电波或信号的输入，并且控制车辆的门锁装置、电动车窗装置、灯等。The vehicle body system control unit 12020 controls operations of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 12020 acts as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as headlights, rear lights, brake lights, turn lights, or fog lights. In this case, radio waves transmitted from the portable device in place of the key or signals of various switches may be input to the body system control unit 12020 . The body system control unit 12020 receives an input of radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.

车外信息检测单元12030检测关于安装了车辆控制系统12000的车辆的外部的信息。例如，成像单元12031连接到车外信息检测单元12030。车外信息检测单元12030使成像单元12031拍摄车辆外部的图像，并且接收拍摄到的图像。车外信息检测单元12030可以基于接收到的图像对人、车辆、障碍物、标志或路表面上的字符等物体执行检测处理或距离检测处理。The outside vehicle information detection unit 12030 detects information on the outside of the vehicle on which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the outside-vehicle information detection unit 12030 . The outside vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle, and receives the captured image. The outside vehicle information detection unit 12030 may perform detection processing or distance detection processing on objects such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

成像单元12031是接收光并且输出与接收到的光的量相对应的电信号的光学传感器。成像单元12031也可以将电信号作为图像和测距信息输出。此外，由成像单元12031接收到的光可以是可见光或如红外光等不可见光。The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of the received light. The imaging unit 12031 can also output electrical signals as images and ranging information. Also, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

车内信息检测单元12040检测车辆中的信息。例如，车内信息检测单元12040连接到用于检测驾驶员的状态的驾驶员状态检测单元12041。例如，驾驶员状态检测单元12041包括拍摄驾驶员的相机，并且车内信息检测单元12040可以基于从驾驶员状态检测单元12041输入的检测信息计算驾驶员的疲劳水平或集中水平，或可以判定驾驶员是否打瞌睡。The in-vehicle information detection unit 12040 detects information in the vehicle. For example, the in-vehicle information detection unit 12040 is connected to the driver state detection unit 12041 for detecting the state of the driver. For example, the driver state detection unit 12041 includes a camera that photographs the driver, and the in-vehicle information detection unit 12040 may calculate the driver's fatigue level or concentration level based on the detection information input from the driver state detection unit 12041, or may determine the driver Doze off.

微型计算机12051可以基于车外信息检测单元12030或车内信息检测单元12040获得的车辆外部和内部的信息计算驱动力产生装置、转向机构或制动装置的控制目标值，并且向驱动系统控制单元12010输出控制指令。例如，微型计算机12051可以执行协同控制以实现高级驾驶员辅助系统(ADAS)的功能，该功能包括车辆的碰撞避免或撞击减轻、基于车辆之间的距离的跟车行驶、保持车速行驶、车辆碰撞警告、车道偏离警告等。The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism, or the braking device based on the information outside and inside the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and report it to the drive system control unit 12010. Output control commands. For example, the microcomputer 12051 may perform cooperative control to realize the functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation of a vehicle, following based on the distance between vehicles, keeping the vehicle speed, vehicle collision warning, lane departure warning, etc.

此外，微型计算机12051通过基于车外信息检测单元12030或车内信息检测单元12040获得的车辆周围的信息控制驱动力产生装置、转向机构或制动装置等，可以执行协同控制以实现独立于驾驶员的操作自主行驶的自动驾驶等。In addition, the microcomputer 12051 can perform cooperative control to achieve independence from the driver by controlling the driving force generating device, the steering mechanism, or the braking device, etc. based on the information around the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040 The operation of autonomous driving, autonomous driving, etc.

此外，微型计算机12051可以基于由车外信息检测单元12030获得的车辆外部的信息向车身系统控制单元12030输出控制指令。例如，微型计算机12051可以根据车外信息检测单元12030检测到的前方车辆或对向车辆的位置控制前照灯并且执行协同控制以实现眩光保护，如将远光灯切换为近光灯。Furthermore, the microcomputer 12051 can output a control instruction to the body system control unit 12030 based on the information outside the vehicle obtained by the outside vehicle information detection unit 12030 . For example, the microcomputer 12051 may control the headlights according to the position of the preceding vehicle or the opposite vehicle detected by the outside information detection unit 12030 and perform cooperative control to realize glare protection, such as switching from high beam to low beam.

声音/图像输出单元12052将声音和图像中的至少一种输出信号传输到能够视觉上或听觉上向车辆的乘员或车辆的外部通知信息的输出装置。在图25的示例中，作为输出装置，示出了音频扬声器12061、显示单元12062和仪表面板12063。例如，显示单元12062可以包括车载显示器和平视显示器中的至少一者。The sound/image output unit 12052 transmits at least one of a sound and an image output signal to an output device capable of visually or audibly informing an occupant of the vehicle or the outside of the vehicle of information. In the example of FIG. 25, as output devices, an audio speaker 12061, a display unit 12062, and a meter panel 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

图26是示出了成像单元12031的安装位置的示例的图。FIG. 26 is a diagram showing an example of the installation position of the imaging unit 12031.

在图26中，作为成像单元12031，包括成像单元12101、12102、12103、12104和12105。In FIG. 26, as the imaging unit 12031, imaging units 12101, 12102, 12103, 12104, and 12105 are included.

例如，成像单元12101、12102、12103、12104和12105设置在车辆12100的前鼻、侧视镜、后保险杠、后门以及车辆内部前挡风玻璃的上部等位置上。设置在前鼻上的成像单元12101和设置在车辆内部前挡风玻璃的上部的成像单元12105主要获得车辆12100前方的图像。设置在侧视镜上的成像单元12102和12103主要获得车辆12100的侧面的图像。设置在后保险杠或后门上的成像单元12104主要获得车辆12100后面的图像。设置在车辆内部前挡风玻璃的上部的成像单元12105获得的前方图像主要用于检测前方车辆、行人、障碍物、交通信号、交通标志、车道等。For example, the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, rear doors, and upper part of the front windshield inside the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the front windshield inside the vehicle mainly obtain an image of the front of the vehicle 12100 . The imaging units 12102 and 12103 provided on the side mirrors mainly obtain images of the side of the vehicle 12100 . The imaging unit 12104 provided on the rear bumper or the rear door mainly obtains an image of the rear of the vehicle 12100 . The front image obtained by the imaging unit 12105 provided at the upper part of the front windshield inside the vehicle is mainly used to detect the preceding vehicle, pedestrian, obstacle, traffic signal, traffic sign, lane, and the like.

另一方面，图26示出了成像单元12101到12104的成像范围的示例。成像范围12111表示设置在前鼻上的成像单元12101的成像范围，成像范围12112和12113分别表示设置在侧视镜上的成像单元12102和12103的成像范围，以及成像范围12114表示设置在后保险杠或后门上的成像单元12104的成像范围。例如，通过将由成像单元12101到12104拍摄的图像数据叠加，可以获得从上方观察时车辆12100的俯瞰图像。On the other hand, FIG. 26 shows an example of the imaging range of the imaging units 12101 to 12104. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 represent the imaging range of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 represents the imaging range provided on the rear bumper Or the imaging range of the imaging unit 12104 on the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 when viewed from above can be obtained.

成像单元12101到12104中的至少一个可以具有获得距离信息的功能。例如，成像单元12101到12104中的至少一个可以是由多个成像元件构成的立体相机，或可以是包括用于相位差检测的像素的成像元件。At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element including pixels for phase difference detection.

例如，微型计算机12051可以基于从成像单元12101到12104获得的距离信息通过获得到成像范围12111到12114内的每一个三维物体的距离以及距离的时间变化(相对于车辆12100的相对速度)，特别地将车辆12100的行驶路径上最近的三维物体提取为前方车辆，该三维物体在与车辆12100的方向基本上相同的方向上以预定的速度(例如，0km/h或更高)行驶。此外，微型计算机12051可以在前方车辆前方预先设定要确保的车辆间的距离，并且可以执行自动制动控制(包括跟车停止控制)、自动加速控制(包括跟车启动控制)等。以这种方式，可以执行协同控制以实现独立于驾驶员的操作的自主行驶的自动驾驶等。For example, the microcomputer 12051 can obtain the distance to each of the three-dimensional objects within the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed with respect to the vehicle 12100 ), specifically, based on the distance information obtained from the imaging units 12101 to 12104 . The closest three-dimensional object on the travel path of the vehicle 12100 traveling at a predetermined speed (eg, 0 km/h or higher) in substantially the same direction as the vehicle 12100 is extracted as the preceding vehicle. In addition, the microcomputer 12051 can preset a distance between vehicles to be secured ahead of the preceding vehicle, and can execute automatic braking control (including follow stop control), automatic acceleration control (including follow start control), and the like. In this way, cooperative control can be performed to realize autonomous driving of autonomous driving and the like independent of the driver's operation.

例如，微型计算机12051可以基于从成像单元12101到12104获得的距离信息将与三维物体相关的三维物体数据分类并提取为二轮车辆、普通车辆、大型车辆、行人和电线杆等其他三维物体并将其用于自动避开障碍物。例如，微型计算机12051将车辆12100周围的障碍物区分为车辆12100的驾驶员可以看见的障碍物和难以看见的障碍物。然后，微型计算机12051判定表示与每一个障碍物碰撞的风险的碰撞风险，并且当碰撞风险等于或高于设定值并且存在碰撞可能时，这可以通过由音频扬声器12061或显示单元12062向驾驶员输出警告或通过驱动系统控制单元12010执行强制减速或避让转向来执行用于避免碰撞的驾驶辅助。For example, the microcomputer 12051 can classify and extract three-dimensional object data related to three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104 as other three-dimensional objects such as two-wheeled vehicles, general vehicles, large vehicles, pedestrians, and utility poles, and It is used to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk representing the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, this can be communicated to the driver by the audio speaker 12061 or the display unit 12062 A warning is output or driving assistance for collision avoidance is performed by the drive system control unit 12010 performing forced deceleration or evasive steering.

成像单元12101到12104中的至少一个可以是用于检测红外线的红外相机。例如，微型计算机12051可以通过判定由成像单元12101到12104的拍摄的图像中是否存在行人来识别行人。例如，通过提取由作为红外相机的成像单元12101到12104拍摄的图像中的特征点的过程和对表示物体轮廓的一系列特征点进行图案匹配处理以区分是否是行人的过程执行这种行人识别。当微型计算机12051判定在由成像单元12101到12104拍摄的图像中存在行人并且识别出行人时，声音/图像输出单元12052控制显示单元12062叠加显示矩形轮廓以强调所识别出的行人。此外，声音/图像输出单元12052可以控制显示单元12062在期望的位置显示表示行人的图标等。At least one of the imaging units 12101 to 12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian exists in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a process of extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras and a process of subjecting a series of feature points representing object contours to pattern matching processing to distinguish whether it is a pedestrian or not. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the sound/image output unit 12052 controls the display unit 12062 to display a rectangular outline superimposed to emphasize the recognized pedestrian. In addition, the sound/image output unit 12052 can control the display unit 12062 to display an icon or the like representing a pedestrian at a desired position.

这里所使用的系统是指由多个装置构成的整个装置。A system as used here refers to an entire device composed of a plurality of devices.

本说明书中描述的有利效果仅仅是示例性的并且不受限制，并且可以实现其他有利效果。The advantageous effects described in this specification are merely exemplary and not restrictive, and other advantageous effects can be achieved.

本技术的实施方案不限于上述实施方案，并且在不脱离本技术的主旨的情况下，能够在本技术的范围内进行各种修改。Embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made within the scope of the present technology without departing from the gist of the present technology.

本技术还能够如下构造。The present technology can also be configured as follows.

(1)一种成像元件，其中：(1) An imaging element, wherein:

第一芯片和第二芯片层叠，所述第一芯片包括光电二极管；所述第二芯片包括处理从所述光电二极管传送的信号的电路，并且A first chip and a second chip are stacked, the first chip including a photodiode; the second chip including circuitry to process signals transmitted from the photodiode, and

在所述第二芯片的位于与层叠有所述第一芯片的第一面相反的一侧的第二面上设置有带电膜。A charging film is provided on the second surface of the second chip on the opposite side to the first surface on which the first chip is stacked.

(2)上述(1)中所述的成像元件，其中，所述带电膜设置在所述第二面的一部分或整个面中。(2) The imaging element described in (1) above, wherein the charging film is provided in a part or the entire surface of the second surface.

(3)上述(1)或(2)中所述的成像元件，其中，所述带电膜还设置在所述第二芯片的侧面上。(3) The imaging element described in (1) or (2) above, wherein the charging film is further provided on the side surface of the second chip.

(4)上述(1)至(3)中任一项所述的成像元件，其中，所述带电膜是具有负固定电荷或正固定电荷的膜。(4) The imaging element according to any one of (1) to (3) above, wherein the charged film is a film having a negative fixed charge or a positive fixed charge.

(5)上述(4)中所述的成像元件，其中，所述带电膜由氧化铪、氧化铝、氧化锆、氧化钽、氧化钛、氧化镧或氧化钇形成。(5) The imaging element described in (4) above, wherein the charged film is formed of hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, titanium oxide, lanthanum oxide, or yttrium oxide.

(6)上述(5)中所述的成像元件，其中，所述带电膜的一部分被氮化。(6) The imaging element described in (5) above, wherein a part of the charging film is nitrided.

(7)上述(1)至(3)中任一项所述的成像元件，其中，所述带电膜使用铁电物质形成。(7) The imaging element according to any one of (1) to (3) above, wherein the charged film is formed using a ferroelectric substance.

(8)上述(7)中所述的成像元件，其中，所述带电膜由氮化镓、钛酸钡、氧化锌或氮化铝形成。(8) The imaging element described in (7) above, wherein the charging film is formed of gallium nitride, barium titanate, zinc oxide, or aluminum nitride.

(9)上述(1)至(8)中任一项所述的成像元件，其中，所述带电膜形成单层或多层。(9) The imaging element according to any one of (1) to (8) above, wherein the charging film forms a single layer or a multilayer.

(10)上述(1)至(9)中任一项所述的成像元件，其中，在所述第二面上设置有具有不同特性的带电膜。(10) The imaging element according to any one of (1) to (9) above, wherein charging films having different characteristics are provided on the second surface.

(11)上述(1)至(10)中任一项所述的成像元件，其中，所述第二芯片的厚度等于或小于20um。(11) The imaging element according to any one of (1) to (10) above, wherein the thickness of the second chip is equal to or less than 20 μm.

(12)上述(1)至(11)中任一项所述的成像元件，其中，在所述第二芯片上还层叠有第三芯片。(12) The imaging element according to any one of (1) to (11) above, wherein a third chip is further stacked on the second chip.

(13)上述(1)至(12)中任一项所述的成像元件，其中，在所述第一芯片中设置有两个或更多个所述第二芯片。(13) The imaging element according to any one of (1) to (12) above, wherein two or more of the second chips are provided in the first chip.

(14)上述(1)至(13)中任一项所述的成像元件，还包括金属扩散防止膜，(14) The imaging element described in any one of (1) to (13) above, further comprising a metal diffusion preventing film,

其中，所述金属扩散防止膜的形成面积和所述带电膜的形成面积具有不同的大小。Here, the formation area of the metal diffusion preventing film and the formation area of the charging film have different sizes.

(15)一种半导体芯片，其是厚度等于或小于20um的芯片，(15) A semiconductor chip, which is a chip having a thickness of 20 um or less,

其中，在所述芯片的预定面上设置有带电膜。Wherein, a charged film is arranged on a predetermined surface of the chip.

(16)上述(15)中所述的半导体芯片，其中，包括所述半导体芯片的多个芯片层叠，并且(16) The semiconductor chip described in (15) above, wherein a plurality of chips including the semiconductor chip are stacked, and

在所述多个芯片中的至少一个芯片中设置有带电膜。A charged film is provided in at least one of the plurality of chips.

(17)上述(15)或(16)中所述的半导体芯片，其中，所述半导体芯片是安装有存储器或逻辑电路的芯片。(17) The semiconductor chip described in (15) or (16) above, wherein the semiconductor chip is a chip on which a memory or a logic circuit is mounted.

(18)一种成像元件，其中：(18) An imaging element, wherein:

第一芯片、第二芯片和第三芯片层叠，The first chip, the second chip and the third chip are stacked,

所述第一芯片包括光电二极管；所述第二芯片包括处理从所述光电二极管传送的信号的电路；所述第三芯片具有存储功能或AI功能，The first chip includes a photodiode; the second chip includes a circuit for processing signals transmitted from the photodiode; the third chip has a memory function or an AI function,

其中，在所述第三芯片的位于与层叠有所述第二芯片的第一面相反的一侧的第二面上设置有带电膜。Here, a charging film is provided on the second surface of the third chip, which is located on the opposite side to the first surface on which the second chip is stacked.

(19)上述(18)中所述的成像元件，其中，在所述第二芯片的位于与层叠有所述第一芯片的第三面相反的一侧的第四面上设置有带电膜。(19) The imaging element described in (18) above, wherein a charging film is provided on the fourth surface of the second chip, which is located on the opposite side to the third surface on which the first chip is stacked.

[附图标记列表][List of reference numerals]

10 成像装置10 Imaging unit

11 透镜组11 lens group

12 成像元件12 Imaging elements

13 DSP电路13 DSP circuits

14 帧存储器14 frame memory

15 显示单元15 Display unit

16 记录单元16 recording units

17 操作系统17 Operating System

18 电源系统18 Power System

19 总线19 bus

20 CPU20 CPU

41 像素阵列单元41 pixel array unit

42 垂直驱动单元42 vertical drive unit

43 列处理单元43-column processing unit

44 水平驱动单元44 Horizontal drive unit

45 系统控制单元45 System Control Unit

46 像素驱动线46 pixel drive lines

47 垂直信号线47 Vertical signal line

48 信号处理单元48 Signal Processing Unit

49 数据存储单元49 Data storage unit

101 CIS芯片101 CIS chip

102 逻辑芯片102 logic chip

103 支撑基底103 Support base

104 栅极形成层104 Gate formation layer

105 源极/漏极形成层105 Source/drain forming layer

111 芯片上透镜111 On-chip lens

112 滤色器112 color filters

113 光电二极管113 Photodiode

114 配线层114 Wiring layer

115 焊盘115 pads

121 焊盘121 pads

122 配线122 Wiring

123 晶体管123 transistors

130 带电膜130 Charged film

151 P阱151 P well

152 N阱152 N well

153 扩散层153 Diffusion layer

154 扩散层154 Diffusion Layer

155 元件分离区域155 Component separation area

161 耗尽层161 Depletion layer

162 缺陷162 Defects

201 氧化膜201 oxide film

251 芯片251 chips

252 带电膜252 Charged film

253 氧化膜253 oxide film

301 层叠芯片301 Stacked Chips

311 存储芯片311 memory chip

330 带电膜330 charged film

351 单片器件351 Monolithic Devices

401 芯片401 chip

402 芯片402 chip

403 芯片403 chip

404 支撑基底404 Support base

412 凸块412 bump

414 凸块414 bump

501 单层芯片。501 single-layer chip.