CN115202246A - Circuit capable of automatically entering debugging mode and vehicle control unit - Google Patents

The invention discloses a circuit capable of automatically entering a debugging mode and a vehicle control unit, and relates to the technical field of controller debugging. The circuit comprises: the debugging mode wake-up source, the debugging voltage control module, the filtering current-limiting module and the debugged module; the debugging awakening source is connected with the debugged module through the filtering current-limiting module, and the filtering current-limiting module enables the power-on time of the debugging mode awakening signal to be later than the power-on time of the debugging voltage generated by the debugging voltage control module; the debugging voltage control module is respectively connected with the debugging awakening source and the debugged module to generate debugging voltage and control the power supply time of the debugging voltage; and the debugged module automatically enters a debugging mode when meeting the preset condition. The invention enables the debugged equipment to automatically enter a debugging mode. Therefore, a Debug mode does not need to be entered manually, and the problems of production and test efficiency influence, chip damage and the like caused by manual operation are avoided naturally.

Circuit capable of automatically entering debugging mode and vehicle control unit

Technical Field

The invention relates to the technical field of controller debugging, in particular to a circuit capable of automatically entering a debugging mode and a vehicle control unit.

Background

At present, when some system basic chips in automobile electronic products are debugged, the chips need to enter a debugging mode, that is, the chips enter a Debug mode. This can be done manually by a professional worker.

At present, the operation steps of entering the Debug mode by manual operation are complex, and workers need to remember the power-on sequence of each signal, and manual switching of the states of each signal not only affects the production and test efficiency, but also may cause the chip to be damaged if the workers are unfamiliar with the operation or have any one of the operation errors. Therefore, it is desirable to provide a method for automatically entering the Debug mode of the chip.

Disclosure of Invention

In view of the above problems, the present invention provides a circuit for automatically entering a Debug mode and a vehicle control unit, which can enable a chip to automatically enter a Debug mode.

A first aspect of an embodiment of the present invention provides a circuit for automatically entering a debug mode, where the circuit includes: the debugging mode wake-up source, the debugging voltage control module, the filtering current-limiting module and the debugged module;

the debugging awakening source is connected with the debugged module through the filtering current-limiting module and used for generating a debugging mode awakening signal;

the filtering current-limiting module filters and limits current of the debugging mode wake-up signal, and meanwhile, the power-on time of the debugging mode wake-up signal is later than the power-on time of the debugging voltage generated by the debugging voltage control module;

the debugging voltage control module is respectively connected with the debugging awakening source and the debugged module and is used for generating the debugging voltage and controlling the power supply time of the debugging voltage according to the debugging mode awakening signal;

and the debugged module automatically enters a debugging mode when the power supply time of the debugging voltage and the power-on time sequences of the debugging mode wake-up signal and the debugging voltage meet preset conditions.

Optionally, the debug voltage control module includes: the transistor comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a Schottky diode and a PMOS (P-channel metal oxide semiconductor) tube;

the first end of the first resistor is connected with the debugging mode wake-up source;

the second end of the first resistor is connected with the first end of the second resistor and the first end of the third resistor respectively;

a second end of the second resistor is connected with a second end of the Schottky diode, a second end of the first capacitor and a second end of the second capacitor, and is grounded;

the second end of the third resistor is connected with the first end of the first capacitor and the first end of the fourth resistor respectively;

the second end of the fourth resistor is connected with the grid electrode of the PMOS tube;

the first end of the second capacitor is respectively connected with the drain electrode of the PMOS tube and the debugged module;

and the first end of the Schottky diode is connected with the source electrode of the PMOS tube.

Optionally, the circuit further comprises: at least one operation wake-up source for generating at least one operation mode wake-up signal;

each work awakening source in the at least one work awakening source is connected with a diode in series;

the debugging wake-up source is connected with a diode in series;

and each work awakening source is connected with the diode in series and then forms an OR gate logic circuit with the debugging awakening source connected with the diode in series, and then is connected with the filtering current-limiting module.

Optionally, the debug mode wake-up source and the working wake-up source do not generate signals at the same time.

Optionally, the debuggee module includes: a debugged chip; the debugged chip comprises: the device comprises a working power supply interface, a wake-up signal interface and a debugging voltage interface;

the working power supply interface is connected with an external working power supply, and the external working power supply provides a working power supply for the debugged chip through the working power supply interface;

the wake-up signal interface is connected with the filtering current-limiting module, and the at least one working mode wake-up signal or the debugging mode wake-up signal passes through the filtering current-limiting module and is transmitted to the debugged chip through the wake-up signal interface;

the debugging voltage interface is connected with the drain electrode of the PMOS tube and the first end of the second capacitor respectively, and the debugging voltage is transmitted to the debugged chip through the debugging voltage interface.

Optionally, when the debug wake-up source generates a debug mode wake-up signal, the schottky diode clamps a voltage value of the debug mode wake-up signal to a voltage value required by the debug voltage, so that the PMOS transistor is turned on, and a drain of the PMOS transistor generates the debug voltage and is powered on through the debug voltage interface to be provided to the debugged chip;

the first capacitor is charged through the first resistor and the third resistor while the voltage value of the debugging mode wake-up signal is clamped to the voltage value required by the debugging voltage through the Schottky diode, and the voltage value of the first capacitor gradually increases along with the time;

the voltage value of the first capacitor is gradually increased, so that the grid voltage of the PMOS tube is gradually increased until the PMOS tube is disconnected, and the debugging voltage generated by the drain electrode of the PMOS tube is changed into 0.

Optionally, the power supply time of the debug voltage is the time from the conduction to the disconnection of the PMOS transistor;

the time from the conduction to the disconnection of the PMOS tube is determined by the sizes of the first capacitor, the first resistor and the third resistor.

Optionally, the preset condition includes: the voltage value of the working power supply is larger than a preset voltage value, the power-on time of the debugging mode wake-up signal is later than the power-on time of the debugging voltage, and the power supply time of the debugging voltage is larger than a preset time threshold.

A second aspect of an embodiment of the present invention provides a vehicle control unit, where the controller includes: SBC module, the control module includes: circuitry for automatically entering a debug mode as defined in any one of the first aspects;

the circuit is used for enabling the debugged module to automatically enter a debugging mode when the debugging mode wake-up source generates a signal;

the circuit is further configured to cause the debuggee module to enter a working mode when the working wake-up source generates a signal.

According to the circuit capable of automatically entering the debugging mode, the debugging awakening source is used for generating the debugging mode awakening signal; the filtering current-limiting module filters and limits current of the debugging mode wake-up signal, and meanwhile, the power-on time of the debugging mode wake-up signal is later than the power-on time of the debugging voltage generated by the debugging voltage control module; the debugging voltage control module is used for generating debugging voltage and controlling the power supply time of the debugging voltage according to the debugging mode wake-up signal; and the debugged module can automatically enter a debugging mode when the power supply time of the debugging voltage, the power-on time sequence of the debugging mode wake-up signal and the debugging voltage meet preset conditions. Therefore, a Debug mode does not need to be entered manually, and the problems of production and test efficiency influence, chip damage and the like caused by manual operation are avoided naturally.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a modular schematic diagram of an automatic enter debug mode circuit of an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a circuit for automatically entering a debug mode according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.

The inventor finds that the operation step of the chip entering the Debug mode is complicated due to the manual operation at present, and a worker needs to remember the power-on sequence of each signal.

For example: for the automobile-level system base chip FS8510, the following conditions are required to be met when the automobile-level system base chip FS8510 enters the Debug mode:

1. vsup (chip operating voltage) > preset voltage value;

2、V _Debug (chip debug voltage) =5V;

3. wake (debug mode Wake up signal) > 4V;

4、V _Debug after the 5V power supply time is maintained for more than 7 mus, the voltage becomes 0V.

In the above scheme, entering the Debug mode is generally realized by using a jumper wire. Firstly, the input of the Wake signal is cut off, then the jumper terminal is used for short-circuiting two terminals, and the V of 5V is obtained _Debug Then the input of the Wake signal is switched on again, and V of 5V is maintained _Debug After the power supply time of more than 7 mus, the jumper terminal is removed so that V _Debug Becomes 0V, thereby satisfying the condition that the FS8510 enters the Debug mode, so that the FS8510 enters the Debug mode.

However, the above manual operation process is complicated, the worker needs to keep the power-on sequence of each signal in mind, and manually switching the states of each signal not only affects the production and testing efficiency, but also may damage the FS8510 chip if the worker is not familiar with the operation or has any misoperation.

In view of the above problems, the inventors propose the circuit for automatically entering the debug mode of the present invention, and the present invention will be described in detail below.

Referring to fig. 1, a schematic diagram of an auto-entry debug mode circuitry according to an embodiment of the present invention is shown, the auto-entry debug mode circuitry including: the debugging mode comprises a debugging mode awakening source 10, a debugging voltage control module 20, a filtering current limiting module 30 and a debugged module 40; the debugging awakening source 10 is connected with the debugged module 40 through the filtering current-limiting module 30, and the debugging awakening source 10 is used for generating a debugging mode awakening signal; the filtering current-limiting module 30 filters and limits current of the debugging mode wake-up signal, and simultaneously, the power-on time of the debugging mode wake-up signal is later than the power-on time of the debugging voltage generated by the debugging voltage control module 20; the debug voltage control module 20 is connected to the debugged wake-up source 10 and the debugged module 40, respectively, and is configured to generate a debug voltage and control a power supply time of the debug voltage according to the debug mode wake-up signal; the debugged module 40 automatically enters the debugging mode when the power supply time of the debugging voltage and the power-on time sequence of the debugging mode wake-up signal and the debugging voltage meet the preset conditions.

Along with the lapse of time, the WAKE-up signal interface WAKE charges the first capacitor C1 through the first resistor R1 and the third resistor R3, so that the voltage of the first capacitor C1 gradually increases, and the voltage value of the first capacitor C1 gradually increases, so that the voltage on the gate G of the PMOS transistor Q gradually increases until the PMOS transistor Q1 is disconnected without meeting the conduction condition, and at this time, the debug voltage generated on the drain D of the PMOS transistor Q1 becomes 0V. And as the power supply time of the debugging voltage is required to be more than 7 mus when the chip FS8510 enters the Debug mode, the conduction time of the PMOS tube Q1 is required to be kept to be more than 7 mus. That is, the power supply time of the debug voltage is the time from the on state to the off state of the PMOS transistor Q1. In the embodiment of the present invention, the time from the on state to the off state of the PMOS transistor Q1 is determined by the sizes of the first capacitor C1, the first resistor R1 and the third resistor R3, and the first capacitor C1, the first resistor R1 and the third resistor R3 with different sizes can be selected as required, so that the time from the on state to the off state of the PMOS transistor Q1 is greater than 7 μ s.

For example: for the FS8510 chip, the preset conditions include: the voltage value of the working power supply Vsup is larger than the preset voltage value, the power-on time of the debugging mode Wake-DB is later than that of the debugging voltage, and the power supply time of the debugging voltage is larger than the preset time threshold value by 7 mu s. The circuit for automatically entering the debugging mode meets the conditions when the Wake-DB signal in the debugging mode is effective, so that the FS8150 can automatically enter the debugging mode without manual operation.

In summary, in the circuit automatically entering the debug mode according to the embodiment of the present invention, when the debug mode wake-up signal generated by the debug wake-up source is valid, the debug mode wake-up signal passes through the diode, the or gate, and the filtering current-limiting module, so that the power-on time of the debug mode wake-up signal is later than the power-on time of the debug voltage generated by the debug voltage control module according to the debug mode wake-up signal; meanwhile, the power supply time of the debugging voltage is controlled by the sizes of the resistor and the capacitor; by the circuit structure of the embodiment of the invention, the debugged module can automatically enter the debugging mode when the power supply time of the debugging voltage and the power-on time sequence of the debugging mode wake-up signal and the debugging voltage meet the preset conditions. Therefore, the Debug mode does not need to be entered manually, and the problems that the production and testing efficiency are affected due to manual operation, the chip is damaged and the like can be avoided naturally.

In addition, the circuit capable of automatically entering the debugging mode has higher universality, circuits with strict requirements on the sequence of power-on time (namely power-on time sequence) can be realized on the basis of the circuit capable of automatically entering the debugging mode, and even if the power-on time sequence has more complicated requirements, the circuit capable of automatically entering the debugging mode can achieve the aim only by adding a delay element on the basis of the circuit capable of automatically entering the debugging mode, so that the circuit capable of automatically entering the debugging mode also has better expansibility.

Based on the above circuit for automatically entering the debugging mode, an embodiment of the present invention further provides a vehicle control unit, where the controller includes: an SBC module, the SBC module including: circuitry for automatically entering a debug mode as described in any of the above; the circuit is used for enabling the debugged module to automatically enter a debugging mode when the debugging mode wake-up source generates a signal; the circuit is further configured to cause the debuggee module to enter a working mode when the working wake-up source generates a signal.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or article that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, or article.

The embodiments of the present invention have been described in connection with the accompanying drawings, and the principles and embodiments of the present invention are described herein using specific examples, which are provided only to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.