CN115441874A - Fourteen-bit resolution two-stage cyclic analog-to-digital converter - Google Patents

A fourteen-bit resolution two-stage cyclic analog-to-digital converter comprises a first-stage multiplication digital-to-analog converter unit with 6-bit resolution, a second-stage multiplication digital-to-analog converter unit with 9-bit resolution, a redundancy addition module and a clock phase high-precision adjustable module. According to the invention, through the structural design of two-stage circulation of 6 bits +9 bits, the power consumption is greatly reduced compared with a single-stage 14-bit circulation type analog-to-digital converter, and the application of low-power consumption analog-to-digital conversion is met.

一种十四位分辨率两级循环型模数转换器A Fourteen-bit Resolution Two-Stage Circular Analog-to-Digital Converter

技术领域technical field

本发明涉及模数转换器，特别涉及一种十四位分辨率两级循环型模数转换器。The invention relates to an analog-to-digital converter, in particular to a fourteen-bit resolution two-stage circulation analog-to-digital converter.

背景技术Background technique

模数转换器作为数字信号与模拟信号之间通信的重要模块，常被应用于图像处理、数字基站等领域。模数转换器把输入的模拟信号按规定的时间间隔采样，并与一系列标准的数字信号相比较，数字信号逐次收敛，直至两种信号相等，最终得到代表此信号的二进制数。循环型模数转换器属于模数转换器中的一种循环式结构，具有功耗低、面积小的特点，被广泛应用于图像传感器。As an important module for communication between digital signals and analog signals, analog-to-digital converters are often used in image processing, digital base stations and other fields. The analog-to-digital converter samples the input analog signal at a specified time interval and compares it with a series of standard digital signals. The digital signal converges successively until the two signals are equal, and finally a binary number representing the signal is obtained. The cyclic analog-to-digital converter belongs to a cyclic structure in the analog-to-digital converter, which has the characteristics of low power consumption and small area, and is widely used in image sensors.

目前的模数转换器由于对精度的要求较高，功耗大的问题一直难以解决，低功耗的实现一直是模数转换器设计的难点。The current analog-to-digital converter has high requirements on precision, and the problem of high power consumption has been difficult to solve. The realization of low power consumption has always been a difficult point in the design of analog-to-digital converters.

发明内容Contents of the invention

本发明解决的问题是：克服现有技术上的不足，提出一种十四位分辨率两级循环型模数转换器，通过6位分辨率、9位分辨率的两级设计，可以大幅度降低功耗，满足高速模数转换应用。The problem solved by the present invention is: to overcome the deficiencies in the prior art, and to propose a fourteen-bit resolution two-stage circulation analog-to-digital converter, through the two-stage design of 6-bit resolution and 9-bit resolution, it can greatly Reduce power consumption to meet high-speed analog-to-digital conversion applications.

本发明解决上述技术问题是通过如下技术方案予以实现的：The present invention solves the problems of the technologies described above and is achieved through the following technical solutions:

一种十四位分辨率两级循环型模数转换器，包括6位分辨率的第一级乘法数模转换器单元MDAC1、9位分辨率的第二级乘法数模转换器单元MDAC2，第一级乘法数模转换器单元MDAC1、第二级乘法数模转换器单元MDAC2均为循环式结构；A fourteen-bit resolution two-stage circular analog-to-digital converter, including a first-stage multiplication digital-to-analog converter unit MDAC1 with a 6-bit resolution, and a second-stage multiplication digital-to-analog converter unit MDAC2 with a 9-bit resolution. The first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 are both circular structures;

第一级乘法数模转换器单元MDAC1和第二级乘法数模转换器单元MDAC2以流水线操作的形式工作；The first-stage multiplying digital-to-analog converter unit MDAC1 and the second-stage multiplying digital-to-analog converter unit MDAC2 work in the form of pipeline operation;

第一级乘法数模转换器单元MDAC1接收输入信号，经过5次循环处理得到高6位转换结果，将高6位转换结果传至第二级乘法数模转换器单元MDAC2；The first-stage multiplication digital-to-analog converter unit MDAC1 receives the input signal, and after 5 cycles of processing, the upper 6-bit conversion result is obtained, and the upper 6-bit conversion result is transmitted to the second-stage multiplication digital-to-analog converter unit MDAC2;

第二级乘法数模转换器单元MDAC2接收高6位转换结果，经过8次与第一级乘法数模转换器相同的循环处理后，输出低9位转换结果；The second-stage multiplication digital-to-analog converter unit MDAC2 receives the high-order 6-bit conversion result, and outputs the low-order 9-bit conversion result after 8 cycles of processing the same as the first-stage multiplication digital-to-analog converter;

高6位转换结果和低9位转换结果进行数据处理，错位相加合成的14位转换结果作为整个模数转换器输出数据。The high 6-bit conversion result and the low 9-bit conversion result are processed for data, and the 14-bit conversion result synthesized by dislocation addition is used as the output data of the entire analog-to-digital converter.

优选的，流水线操作的形式为：第一级乘法数模转换器单元MDAC1在完成高6位的转化后将结果传递给第二级乘法数模转换器单元MDAC2，第二级在完成低9位量化结果的同时，第一级完成下一个信号的高6位转换；第一级乘法数模转换器单元MDAC1的转换时间等于第二级乘法数模转换器单元MDAC2的转换时间并等于整个模数转换器的转换时间。Preferably, the form of the pipeline operation is: the first-stage multiplication digital-to-analog converter unit MDAC1 transfers the result to the second-stage multiplication digital-to-analog converter unit MDAC2 after completing the conversion of the upper 6 bits, and the second stage completes the lower 9-bit While quantizing the result, the first stage completes the conversion of the upper 6 bits of the next signal; the conversion time of the first-stage multiplying digital-to-analog converter unit MDAC1 is equal to the conversion time of the second-stage multiplying digital-to-analog converter unit MDAC2 and is equal to the entire analog-to-digital Converter conversion time.

优选的，第一级乘法数模转换器单元MDAC1每次处理过程为：对输入信号进行采样，该状态称为采样态；再对输入信号进行数据处理，此状态称为保持态，在保持态工作的同时采样态进行下一次的采样操作；每次处理得到1.5位结果，经5次循环，错位相加后输出高6位转换结果。Preferably, each processing process of the first-stage multiplication digital-to-analog converter unit MDAC1 is: sampling the input signal, which is called the sampling state; and then performing data processing on the input signal, which is called the hold state, and in the hold state The sampling state is working at the same time to carry out the next sampling operation; each processing gets 1.5 bit results, after 5 cycles, the high 6 bit conversion results are output after the misplaced addition.

优选的，第一级乘法数模转换器单元MDAC1包括1.5位模数转换器、1.5位数模转换器、由不同时序驱动的开关、电容阵列、差分运算放大器；Preferably, the first-stage multiplication digital-to-analog converter unit MDAC1 includes a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, capacitor arrays, and differential operational amplifiers;

差分运算放大器输入端的两个输入信号通过时序驱动的开关被电容阵列中用于采样的电容组进行采样，采样结果保存在电容组内，完成采样态操作；采样的同时，通过1.5位模数转换器对输入信号进行1.5位量化；The two input signals at the input terminal of the differential operational amplifier are sampled by the capacitor bank used for sampling in the capacitor array through the switch driven by timing, and the sampling result is stored in the capacitor bank to complete the sampling state operation; while sampling, through 1.5-bit analog-to-digital conversion The device performs 1.5-bit quantization on the input signal;

采样完成后，电路进入保持态，通过开关控制，使电容连接到1.5位数模转换器模块的输出上，差分运算放大器输出端向电容阵列中用于保持态的电容组充电，电容组电压在形成新平衡态的过程中完成乘法加偏置的函数运算，运算结果保存在电容组内，且该结果作为保持态的结果被下一个采样态的采样电容采样。After the sampling is completed, the circuit enters the holding state. Through the switch control, the capacitor is connected to the output of the 1.5-digit digital-to-analog converter module. The output terminal of the differential operational amplifier charges the capacitor bank used for the holding state in the capacitor array. The voltage of the capacitor bank is at In the process of forming a new equilibrium state, the function operation of multiplication and bias is completed, and the operation result is stored in the capacitor bank, and the result is sampled by the sampling capacitor of the next sampling state as the result of the holding state.

优选的，第二级乘法数模转换器单元MDAC2每次处理过程为：对输入信号进行采样，该状态称为采样态；再对输入信号进行数据处理，此状态称为保持态，在保持态工作的同时采样态进行下一次的采样操作；每次处理得到1.5位结果，经8次循环，错位相加后输出低9位转换结果。Preferably, each processing process of the second-stage multiplication digital-to-analog converter unit MDAC2 is: sampling the input signal, which is called a sampling state; then performing data processing on the input signal, which is called a hold state, and in the hold state Sampling state is working at the same time for the next sampling operation; each processing gets 1.5-bit result, after 8 cycles, the lower 9-bit conversion result is output after misplaced addition.

优选的，第二级乘法数模转换器单元MDAC2包括1.5位模数转换器、1.5位数模转换器、由不同时序驱动的开关、电容阵列、差分运算放大器；Preferably, the second-stage multiplication digital-to-analog converter unit MDAC2 includes a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, capacitor arrays, and differential operational amplifiers;

差分运算放大器输入端的两个输入信号通过时序驱动的开关被电容阵列中用于采样的电容组进行采样，采样结果保存在电容组内，完成采样态操作；在对输入信号采样的同时通过1.5位模数转换器进行1.5位量化；The two input signals at the input terminal of the differential operational amplifier are sampled by the capacitor bank used for sampling in the capacitor array through the switch driven by timing, and the sampling result is stored in the capacitor bank to complete the sampling state operation; while sampling the input signal, it passes 1.5 bits Analog-to-digital converter for 1.5-bit quantization;

采样完成后，电路进入保持态，通过开关控制，使电容连接到1.5位数模转换器模块的输出上，差分运算放大器输出端向电容阵列中用于保持态的电容组充电，电容组电压在形成新平衡态的过程中完成乘法加偏置的函数运算，运算结果保存在电容组内，且该结果作为保持态的结果被下一个采样态的采样电容采样。After the sampling is completed, the circuit enters the holding state. Through the switch control, the capacitor is connected to the output of the 1.5-digit digital-to-analog converter module. The output terminal of the differential operational amplifier charges the capacitor bank used for the holding state in the capacitor array. The voltage of the capacitor bank is at In the process of forming a new equilibrium state, the function operation of multiplication and bias is completed, and the operation result is stored in the capacitor bank, and the result is sampled by the sampling capacitor of the next sampling state as the result of the holding state.

优选的，还包括冗余加法模块，用于对高6位转换结果和低9位转换结果进行冗余加法运算，减去一位冗余位，合成14位转换结果。Preferably, a redundant addition module is also included, which is used to perform redundant addition operation on the upper 6-bit conversion result and the lower 9-bit conversion result, subtract one redundant bit, and synthesize a 14-bit conversion result.

优选的，还包括时钟相位高精度可调模块，驱动第一级乘法数模转换器单元MDAC1、第二级乘法数模转换器单元MDAC2，控制第一级乘法数模转换器单元MDAC2、第二级乘法数模转换器单元MDAC2流水化操作方式工作。Preferably, it also includes a high-precision adjustable clock phase module, which drives the first-stage multiplying digital-to-analog converter unit MDAC1 and the second-stage multiplying digital-to-analog converter unit MDAC2, and controls the first-stage multiplying digital-to-analog converter unit MDAC2 and the second stage. The multiplication digital-to-analog converter unit MDAC2 works in a pipelined operation mode.

优选的，时钟相位高精度可调模块由同相位时钟单元的输出信号、两相不交叠单元输出信号和与运算单元组成，同相位的时钟信号与不同相位的时钟信号经过运算得到不同时序时钟信号，控制第一级乘法数模转换器单元MDAC1、第二级乘法数模转换器单元MDAC2开关的通断。Preferably, the clock phase high-precision adjustable module is composed of the output signal of the same-phase clock unit, the output signal of the two-phase non-overlapping unit, and the AND operation unit. The clock signal of the same phase and the clock signal of different phases are calculated to obtain different timing clocks signal to control the on-off of the switches of the first-stage multiplying digital-to-analog converter unit MDAC1 and the second-stage multiplying digital-to-analog converter unit MDAC2.

优选的，第一级乘法数模转换器单元MDAC1、第二级乘法数模转换器单元MDAC2均采用模块化设计，电路结构相同，便于替换。Preferably, the first-stage multiplying digital-to-analog converter unit MDAC1 and the second-stage multiplying digital-to-analog converter unit MDAC2 adopt a modular design, have the same circuit structure, and are easy to replace.

本发明与现有技术相比的优点在于：The advantage of the present invention compared with prior art is:

(1)相对于单级循环型模数转换器，两级循环型模数转换器可以在相同转换速率下，相对于单级循环型模数转换器大幅度降低功耗，满足高速模数转换应用。(1) Compared with the single-stage circulating ADC, the two-stage circulating ADC can greatly reduce the power consumption compared with the single-stage circulating ADC at the same conversion rate, and meet the requirements of high-speed analog-to-digital conversion application.

(2)相同转换速率下，“6位+9位”架构的功耗仅相当于单级14位架构的三分之一，具有功耗优势。同时相对于其他两级架构，相同转换速率下功耗最低。(2) Under the same conversion rate, the power consumption of the "6-bit + 9-bit" architecture is only one-third of that of the single-stage 14-bit architecture, which has an advantage in power consumption. At the same time, compared with other two-level architectures, the power consumption is the lowest at the same conversion rate.

附图说明Description of drawings

图1为本发明十四位分辨率两级循环型模数转换器实施例示意图；1 is a schematic diagram of an embodiment of a fourteen-bit resolution two-stage cyclic analog-to-digital converter of the present invention;

图2为循环型模数转换单元保持态示意图，a为保持状态下积分器结构，b为输入输出信号关系图。Fig. 2 is a schematic diagram of the holding state of the cyclic analog-to-digital conversion unit, a is the structure of the integrator in the holding state, and b is a diagram of the relationship between input and output signals.

具体实施方法Specific implementation method

为了便于对本发明的理解，下面将结合附图以具体实施例为例作进一步的解释说明，且实施例不构成对本发明实施例的限定。In order to facilitate the understanding of the present invention, specific embodiments will be taken as examples for further explanation below in conjunction with the accompanying drawings, and the embodiments are not intended to limit the embodiments of the present invention.

本发明对模数转换器进行了深入的理论研究与试验验证，解决14位分辨率模数转换器实现低功耗的设计难题。The invention carries out in-depth theoretical research and experimental verification on the analog-to-digital converter, and solves the design problem of realizing low power consumption of the 14-bit resolution analog-to-digital converter.

循环型模数转换器乘法数模转换器单元MDAC主要基于开关电容电路，开光电容电路分采样状态和保持状态。如图2a所示,为保持状态下的积分器结构，采样电容C_S和保持电容C_f两极板电荷重分配，同时将输出电压相对于输入电压建立到C_f/C_s的倍数关系数值。图2b给出了输入输出信号关系图，输入信号为阶跃信号，输出信号受限于运算放大器的增益带宽积和有限增益，经过一段时间的缓慢建立，逐步逼近输入阶跃信号的高电平V_step，其中输出信号逼近输入阶跃信号的函数关系式为：The cyclic analog-to-digital converter multiplication digital-to-analog converter unit MDAC is mainly based on a switched capacitor circuit, and the switched capacitor circuit is divided into a sampling state and a holding state. As shown in Figure 2a, for the integrator structure in the holding state, the charges on the two plates of the sampling capacitor C _S and the holding capacitor C _f are redistributed, and the output voltage relative to the input voltage is established to a multiple relationship value of C _f /C _s . Figure 2b shows the relationship diagram of input and output signals. The input signal is a step signal, and the output signal is limited by the gain-bandwidth product and finite gain of the operational amplifier. After a period of slow establishment, it gradually approaches the high level of the input step signal V _step , where the functional relationship of the output signal approaching the input step signal is:

输出信号逼近V_step的差值需要小于模数转换器

的精度要求，单级循环型十四位模数转换器通常要求建立精度达到

根据上面的函数关系式可以得到：The difference between the output signal approaching V _step needs to be less than the analog-to-digital converter

Accuracy requirements, single-stage cyclic fourteen-bit analog-to-digital converters usually require the establishment of an accuracy of

According to the above functional relationship, we can get:

由上式计算得到t>10.4τ。Calculated from the above formula to get t>10.4τ.

相同转换周期下，量化位数越高，循环型模数转换器单次量化的时间越短，要达到相应的建立精度，需要运放拥有更大的GBW，而运放的尾电流与GBW的关系为：Under the same conversion period, the higher the number of quantization digits, the shorter the single quantization time of the circular ADC. To achieve the corresponding establishment accuracy, the op amp needs to have a larger GBW, and the tail current of the op amp is the same as the GBW The relationship is:

假设模数转换器的工作电压为3.3V，运放的静态功耗为：Assuming that the operating voltage of the analog-to-digital converter is 3.3V, the static power consumption of the op amp is:

P＝I×3.3P=I×3.3

通过计算得到，各种不同位数模数转换器对建立精度的要求列表如表1所示：Through calculation, the list of requirements for the establishment accuracy of various analog-to-digital converters is shown in Table 1:

表1不同位数模数转换器对建立精度的要求列表Table 1 List of requirements for establishment accuracy of different bit analog-to-digital converters

对于单级结构而言，量化位数越大，单位电容越大，信号建立周期越短，单级十四位模数转换器对运放的要求等同于在更短的时间内和更大的电容上建立到更高的精度，就会对运放的GBW提出更高的要求，进而增大运放的功耗。For a single-stage structure, the larger the number of quantization bits, the larger the unit capacitance, and the shorter the signal establishment period. The establishment of higher precision on the capacitor will put higher requirements on the GBW of the op amp, which will increase the power consumption of the op amp.

为了降低功耗，本发明舍弃了单级结构的设计，提出带一位冗余位的二级结构的技术路径。两级结构由两个不同量化位数的乘法数模转换模块构成，通过流水化操作，可以使第一级在进行量化第m个信号的同时第二级对第m-1个信号的第一级处理结果进行量化，放松对第一级的建立时间的要求，可大幅度降低功耗。In order to reduce power consumption, the present invention abandons the design of a single-level structure, and proposes a technical path of a two-level structure with one redundant bit. The two-stage structure is composed of two multiplicative digital-to-analog conversion modules with different quantization bits. Through pipeline operation, the first stage can quantize the mth signal while the second stage quantizes the first m-1th signal. Quantify the processing results of the first stage and relax the requirements for the first stage's establishment time, which can greatly reduce power consumption.

基于上述技术路径，对十四位分辨率两级循环型模数转换器的不同量化组合进行了分析验证，得到了不同组合下的运放尾电流、运放功耗。表2给出了所有组合中较优的组合(5+10-1)、(6+9-1)和(7+8-1)的数据，其中，量化位数是指第一级结构的量化位数，第一级需要采用1.75pF的电容才能取得相应的噪声和匹配性能。Based on the above technical path, the analysis and verification of different quantization combinations of fourteen-bit resolution two-stage cyclic analog-to-digital converters was carried out, and the op amp tail current and op amp power consumption under different combinations were obtained. Table 2 shows the data of the better combinations (5+10-1), (6+9-1) and (7+8-1) among all the combinations, where the number of digits of quantization refers to the first-level structure The number of quantization bits, the first stage needs to use a capacitor of 1.75pF to achieve the corresponding noise and matching performance.

表2两级结构下第一级不同位数模数转换器对建立精度的要求列表Table 2 List of requirements for the establishment accuracy of the first-level analog-to-digital converters with different digits under the two-level structure

在相同转换速率下，综合表1及表2的数据，对单级结构和两极不同量化组合的结构进行对比测试，得到如表3所示的总功耗对比表：Under the same conversion rate, the data in Table 1 and Table 2 are combined, and the single-stage structure and the structure of different quantization combinations of two poles are compared and tested, and the total power consumption comparison table shown in Table 3 is obtained:

表3基于不同结构的14位分辨率模数转换器总功耗表Table 3 Total power consumption of 14-bit resolution ADCs based on different structures

架构选择architecture choice 总功耗total power consumption 单级14位single stage 14 bit 63.7uW63.7uW 6位+9位架构6-bit + 9-bit architecture 12.6+14.7＝23.3uW12.6+14.7＝23.3uW 7位+8位架构7-bit + 8-bit architecture 16.8+10.5＝27.3uW16.8+10.5＝27.3uW 5位+10位架构5-bit + 10-bit architecture 9+19.9＝28.9uW9+19.9＝28.9uW

从表3可以得出，“6位+9位”架构的功耗仅相当于单级14位架构的三分之一，具有较大的功耗优势，同时相对于其他两种组合选择相比，功耗也较低。尤其是对于应用于多通道场景如CMOS图像传感器列级读出电路，通常达到一千列到一万列并联应用的规模，单通道的功耗优势在多通道应用中会大幅度显现出来。It can be concluded from Table 3 that the power consumption of the "6-bit + 9-bit" architecture is only one-third of that of the single-stage 14-bit architecture, which has a large power consumption advantage. Compared with the other two combination options , power consumption is also lower. Especially for multi-channel scenarios such as column-level readout circuits of CMOS image sensors, which usually reach a scale of 1,000 to 10,000 parallel applications, the power consumption advantage of a single channel will be greatly manifested in multi-channel applications.

基于上述的系统论证与分析，本发明提出了一种十四位分辨率两级循环型模数转换器，包括6位分辨率的第一级乘法数模转换器单元MDAC1、9位分辨率的第二级乘法数模转换器单元MDAC2、冗余加法模块、时钟相位高精度可调模块，电路图如图1所示。Based on the above-mentioned systematic demonstration and analysis, the present invention proposes a two-stage cyclic analog-to-digital converter with 14-bit resolution, including the first-stage multiplication digital-to-analog converter unit MDAC1 with 6-bit resolution and 9-bit resolution The circuit diagram of the second-stage multiplying digital-to-analog converter unit MDAC2, redundant addition module, and high-precision adjustable clock phase module is shown in Figure 1.

(1)图1为差分电路结构，电路结构分为上下相同的两部分，第一级乘法数模转换器单元MDAC1包含的电容C1p1、C2p1、C3p1和C1n1、C2n1、C3n1电容量相同，φ_s1p、φ_aAp、φ_1Ap、φ_2Ap、φ_3Ap、φ_4Ap和φ_s1n、φ_aAn、φ_1An、φ_2An、φ_3An、φ_4An时序相同，跨接pn两部分的φ_3A、φ_4A与φ_3Ap、φ_4Ap、φ_3An、φ_4An时序相同。第二级乘法数模转换器单元MDAC2包含的电容C1p2、C2p2、C3p2和C1n2、C2n2、C3n2电容量相同，φ_s2p、φ_aBp、φ_1Bp、φ_2Bp、φ_3Bp、φ_4Bp和φ_s2n、φ_aBn、φ_1Bn、φ_2Bn、φ_3Bn、φ_4Bn时序相同，跨接pn两部分的φ_3B、φ_4B与φ_3Bp、φ_4Bp、φ_3Bn、φ_4Bn时序相同。(1) Figure 1 shows the differential circuit structure. The circuit structure is divided into two parts with the same upper and lower parts. The capacitors C1p1, C2p1, C3p1 and C1n1, C2n1, and C3n1 contained in the first-stage multiplying digital-to-analog converter unit MDAC1 have the same capacitance, φ _s1p , φ _aAp , φ _1Ap , φ _2Ap , φ _3Ap , φ _4Ap and φ _s1n , φ _aAn , φ _1An , φ _2An , φ _3An , φ _{4An have} the same timing, and φ _3A , φ _4A and φ _3Ap across the two parts of pn , φ _4Ap , φ _3An , and φ _{4An have} the same timing. The capacitors C1p2, C2p2, C3p2 and C1n2, C2n2, C3n2 contained in the second-stage multiplying digital-to-analog converter unit MDAC2 have the same capacitance, φ _s2p , φ _aBp , φ _1Bp , φ _2Bp , φ _3Bp , φ _4Bp and φ _s2n , φ _aBn , φ _1Bn , φ _2Bn , φ _3Bn , φ _{4Bn have} the same timing, and φ _3B , φ _4B connecting the two parts of pn have the same timing as φ _3Bp , φ _4Bp , φ _3Bn , φ _4Bn .

(2)时钟相位高精度可调模块(2) Clock phase high-precision adjustable module

时钟相位高精度可调模块驱动第一级乘法数模转换器单元MDAC1、第二级乘法数模转换器单元MDAC2和冗余加法模块，控制第一级乘法数模转换器单元MDAC1、第二级乘法数模转换器单元MDAC2流水化方式工作。The clock phase high-precision adjustable module drives the first-stage multiplying digital-analog converter unit MDAC1, the second-stage multiplying digital-analog converter unit MDAC2 and the redundant addition module, and controls the first-stage multiplying digital-analog converter unit MDAC1, the second-stage The multiplication digital-to-analog converter unit MDAC2 works in a pipelined manner.

(3)第一级乘法数模转换器单元MDAC1(3) The first-stage multiplication digital-to-analog converter unit MDAC1

第一级乘法数模转换器单元MDAC1接收输入信号，经过5次循环处理后，每次输出1.5位结果，其中包含冗余位信息，错位相加后输出高6位转换结果，并传至第二级乘法数模转换器单元MDAC2。其中，第一级乘法数模转换器单元MDAC1包括1.5位比较器、1.5位数模转换器、开关、电容、差分运算放大器。如图1所示：The first-stage multiplying digital-to-analog converter unit MDAC1 receives the input signal, and after 5 cycles of processing, it outputs a 1.5-bit result each time, which contains redundant bit information, and outputs the upper 6-bit conversion result after the misplaced addition, and transmits it to the second Two-stage multiplying digital-to-analog converter unit MDAC2. Among them, the first-stage multiplying digital-to-analog converter unit MDAC1 includes a 1.5-bit comparator, a 1.5-bit digital-to-analog converter, a switch, a capacitor, and a differential operational amplifier. As shown in Figure 1:

差分运算放大器输入端的两个信号通过φ_s1p控制的开关被电容C1p1和C3p1采样，同时φ_s1p控制的开关跨接差分运算放大器输入输出端打开，将差分运算放大器短路，φ_3Ap控制的开关打开，将C1p1和C3p1电容的右端连接在一起并通过差分运算放大器的输出端充电，将采样结果保存在C1p1和C3p1电容的右端，此过程为采样态。C1n1、C2n1和C3n1的开关和n部分控制信号的时序与p型电路部分一致。The two signals at the input terminal of the differential operational amplifier are sampled by the capacitors C1p1 and C3p1 through the switch controlled by φ _s1p . At the same time, the switch controlled by φ _s1p is opened across the input and output terminals of the differential operational amplifier to short-circuit the differential operational amplifier, and the switch controlled by φ _3Ap is opened. Connect the right ends of the C1p1 and C3p1 capacitors together and charge them through the output of the differential operational amplifier, and store the sampling results at the right ends of the C1p1 and C3p1 capacitors. This process is the sampling state. The timing of the switches of C1n1, C2n1 and C3n1 and the control signals of the n part is consistent with that of the p-type circuit part.

采样完成后，φ_s1p控制的开关关闭，电路进入保持态，φ_aAp、φ_1Ap和φ_3Ap控制的开关打开，φ_s1p、φ_4Ap和φ_2Ap控制的开关关闭，C1p1电容连接到1.5位数模转换器模块的输出上，差分运算放大器输出端向C1p1和C3p1的左端充电，C3p1和C1p1的电容电压在形成新平衡态的过程中完成乘法加偏置的函数运算，运算结果保存在C2p1和C3p1的左端，且该结果作为保持态的结果被下一个采样态的采样电容采样。C1n1、C2n1和C3n1的开关和n部分控制信号的时序与p型电路部分一致。After the sampling is completed, the switch controlled by φ _s1p is closed and the circuit enters the hold state, the switches controlled by φ _aAp , φ _1Ap and φ _3Ap are opened, the switches controlled by φ _s1p , φ _4Ap and φ _2Ap are closed, and the C1p1 capacitor is connected to the 1.5-digit analog On the output of the converter module, the output terminal of the differential operational amplifier is charged to the left end of C1p1 and C3p1, and the capacitor voltage of C3p1 and C1p1 completes the function operation of multiplication and bias in the process of forming a new equilibrium state, and the operation results are stored in C2p1 and C3p1 , and this result is sampled by the sampling capacitor of the next sampling state as a result of the hold state. The timing of the switches of C1n1, C2n1 and C3n1 and the control signals of the n part is consistent with that of the p-type circuit part.

(4)第二级乘法数模转换器单元MDAC2(4) Second-stage multiplication digital-to-analog converter unit MDAC2

第二级乘法数模转换器单元MDAC2接收第一级乘法数模转换器单元MDAC1高6位转换结果，经过8次与第一级乘法数模转换器相同的循环处理后，输出低9位转换结果。其中，第二级乘法数模转换器单元MDAC2包括1.5位模数转换器、1.5位数模转换器、由不同时序驱动的开关、电容阵列、差分运算放大器。The second-stage multiplying digital-to-analog converter unit MDAC2 receives the high-order 6-bit conversion result of the first-stage multiplying digital-to-analog converter unit MDAC1, and outputs the low-order 9-bit conversion after 8 cycles of processing the same as the first-stage multiplying digital-to-analog converter. result. Among them, the second-stage multiplying digital-to-analog converter unit MDAC2 includes a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, a capacitor array, and a differential operational amplifier.

第二级乘法数模转换器单元MDAC2的两个输出信号通过φ_s2p控制的开关被第二级电容C1p2和C3p2采样，同时φ_s2p控制的开关跨接差分运算放大器输入输出端打开，将差分运算放大器短路，φ_3Bp控制的开关打开，将C1p2和C3p2电容的右端连接在一起并通过差分运算放大器的输出端充电，将采样结果保存在C1p2和C3p2电容的右端，此过程为采样态。The two output signals of the second-stage multiplying digital-to-analog converter unit MDAC2 are sampled by the second-stage capacitors C1p2 and C3p2 through the switch controlled by φ _s2p , and at the same time, the switch controlled by φ _s2p is opened across the input and output terminals of the differential operational amplifier, and the differential operation The amplifier is short-circuited, the switch controlled by φ _3Bp is opened, the right ends of the C1p2 and C3p2 capacitors are connected together and charged through the output of the differential operational amplifier, and the sampling results are stored in the right ends of the C1p2 and C3p2 capacitors. This process is a sampling state.

第一级乘法数模转换器单元MDAC1在第五次循环的保持态同时也是第二级乘法数模转换器的第一次循环的采样态中，φ_s2p、φ_2Bp、φ_3Bp、φ_aAp、φ_1Ap和φ_3Ap控制的开关打开，φ_aBp、φ_1Bp、φ_4Bp、φ_s1p、φ_2Ap和φ_4Ap控制的开关关闭。n部分控制信号的时序与p型电路部分一致。In the holding state of the fifth cycle of the first-stage multiplication digital-to-analog converter unit MDAC1, which is also the sampling state of the first cycle of the second-stage multiplication digital-to-analog converter, φ _s2p , φ _2Bp , φ _3Bp , φ _aAp , The switches controlled by φ _1Ap and φ _3Ap are opened, and the switches controlled by φ _aBp , φ _1Bp , φ _4Bp , φ _s1p , φ _2Ap and φ _4Ap are closed. The timing of the control signal of the n part is consistent with that of the p-type circuit part.

采样态完成后，φ_s2控制的开关关闭，第二级乘法数模转换器单元MDAC2电路进入保持态，φ_aBp、φ_1Bp和φ_3Bp控制的开关打开，φ_s2p、φ_4Bp和φ_2Bp控制的开关关闭，C1p2电容连接到1.5位数模转换器模块的输出上，差分运算放大器输出端向C1p2和C3p2的左端充电，C3p2和C1p2的电容电压在形成新平衡态的过程中完成乘法加偏置的函数运算，运算结果保存在C2p2和C3p2的左端，且该结果作为保持态的结果被下一个采样态的采样电容采样。C1n2、C2n2和C3n2的开关和n部分控制信号的时序与p型电路部分一致。After the sampling state is completed, the switch controlled by φ _s2 is closed, the second-stage multiplying digital-to-analog converter unit MDAC2 circuit enters the holding state, the switches controlled by φ _aBp , φ _1Bp and φ _3Bp are opened, and the switches controlled by φ _s2p , φ _4Bp and φ _2Bp The switch is closed, the C1p2 capacitor is connected to the output of the 1.5-digit digital-to-analog converter module, and the output terminal of the differential operational amplifier is charged to the left end of C1p2 and C3p2, and the capacitor voltages of C3p2 and C1p2 are multiplied and biased in the process of forming a new equilibrium state The function operation, the operation result is stored at the left end of C2p2 and C3p2, and the result is sampled by the sampling capacitor of the next sampling state as the result of the hold state. The timing of the switches of C1n2, C2n2 and C3n2 and the control signals of the n part is consistent with that of the p-type circuit part.

(5)冗余加法模块(5) Redundant addition module

本发明的两级结构含有一位冗余位，第一级乘法数模转换器单元MDAC1的高6位转换结果和第二级乘法数模转换器单元MDAC2的低9位转换结果通过冗余加法模块运算，减去一位冗余位，合成14位转换结果，作为整个模数转换器输出数据。The two-stage structure of the present invention contains a redundant bit, the high 6-bit conversion result of the first-stage multiplication digital-to-analog converter unit MDAC1 and the low-order 9-bit conversion result of the second-stage multiplication digital-to-analog converter unit MDAC2 through redundant addition Module operation, one redundant bit is subtracted, and a 14-bit conversion result is synthesized, which is used as the output data of the entire analog-to-digital converter.

以上所述，仅为本发明最佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。The above description is only the best specific implementation mode of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of changes or modifications within the technical scope disclosed in the present invention. Replacement should be covered within the protection scope of the present invention.

本发明说明书中未作详细描述的内容属于本领域专业技术人员的公知技术。The content that is not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.