CN115497816B - Semiconductor field effect integrated circuit and preparation method thereof - Google Patents
- ️Tue Oct 17 2023
CN115497816B - Semiconductor field effect integrated circuit and preparation method thereof - Google Patents
Semiconductor field effect integrated circuit and preparation method thereof Download PDFInfo
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- CN115497816B CN115497816B CN202211279018.0A CN202211279018A CN115497816B CN 115497816 B CN115497816 B CN 115497816B CN 202211279018 A CN202211279018 A CN 202211279018A CN 115497816 B CN115497816 B CN 115497816B Authority
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 230000005669 field effect Effects 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 106
- 238000002347 injection Methods 0.000 claims abstract description 75
- 239000007924 injection Substances 0.000 claims abstract description 75
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 51
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims description 38
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims description 33
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims description 33
- 238000002513 implantation Methods 0.000 claims description 27
- 238000005468 ion implantation Methods 0.000 claims description 22
- 108091006146 Channels Proteins 0.000 claims description 19
- 150000002500 ions Chemical class 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000005036 potential barrier Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 6
- 239000007943 implant Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention discloses a semiconductor field effect integrated circuit and a preparation method thereof, comprising the following steps: the semiconductor device comprises a P-type semiconductor substrate, a first region, a second region and an insulating plate; a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed inside the first region; a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar; insulating plates are respectively arranged on the upper layers of the first area and the second area. The first injection region and the second injection region are used for carrying out ion injection on the semiconductor integrated circuit, so that the conductive contact quality of the N-type semiconductor is improved, and the silicon dioxide insulating layer can effectively prevent impurities from penetrating into the surface of the substrate, so that the reliability and stability of the device integrated circuit are improved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a semiconductor field effect integrated circuit and a preparation method thereof.
Background
Semiconductor integrated circuit devices are of great interest for size, function and low cost fabrication, ion implantation is a method of introducing a controlled amount of impurities into a substrate to change electrical properties, and is almost always implemented by doping ion implantation in modern semiconductor processes, with different effects resulting from different implantation concentrations, and different process conditions being required for different devices. The prior art is difficult to master the metering of ion implantation. The ion implantation channel effect can influence the electrical parameters of the device, various adverse conditions can occur due to improper ion implantation, and along with the continuous change of the size of the semiconductor device, the existing ion implantation process is used for carrying out ion implantation on the active region to form the adverse condition of double traps, the situation influences the production of the semiconductor device, and the progress of the semiconductor process can be hindered.
Disclosure of Invention
To solve the above-mentioned problems occurring in the prior art, the present invention provides,
a semiconductor field effect integrated circuit, comprising:
the semiconductor device comprises a P-type semiconductor substrate, a first region, a second region and an insulating plate;
first region: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed inside the first region;
second region: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
insulating board: insulating plates are respectively arranged on the upper layers of the first area and the second area.
Preferably, the first region is coplanar with the second region, including:
the first injection region and the second injection region are injected by ion injection;
the first injection region is an N+ type conductive region;
the second injection region is an N-type conductive region;
the concentration of the first implanted region is higher than the concentration of the second implanted region.
Preferably, an N-type channel is formed between the first injection region and the second injection region, the channel width is 20 nanometers, the thickness is 5 nanometers, and the N-type channel is arranged on the upper layer of the P-type semiconductor;
and forming a silicon dioxide insulating layer with the thickness of 0.01-0.4 micrometers above the N-type channel.
Preferably, the insulating plates are respectively disposed on the upper layers of the first area and the second area, and the insulating plates comprise:
a first insulating layer: formed at an upper portion of the first region; a second insulating layer: formed at an upper portion of the second region;
the first insulating layer is prepared by local oxidation at 800+/-5 ℃ and the water vapor pressure of 20 standard atmospheric pressures, and the thickness is 0.05-0.1 micrometer;
the second insulating layer is formed in a dry oxygen atmosphere at a temperature of 800+ -5deg.C and has a thickness of 0.1-0.2 μm.
Preferably, the silicon dioxide insulating layer includes:
a photoresist mask is attached to the upper part of the silicon dioxide insulating layer, if the silicon dioxide insulating layer is etched, the photoresist mask is removed, heating is carried out at the temperature of 800+/-5 ℃, and an additional photoresist mask is formed on the silicon dioxide insulating layer through a standard photoetching method; if the silicon dioxide insulating layer is not etched, no treatment is needed; the thickness of the additional photoresist mask is 0.5-1.5 microns.
Preferably, the material of the P-type semiconductor substrate is silicon;
the thickness of the first insulating layer and the second insulating layer is 1 to 20 times that of the silicon dioxide insulating layer;
a channel is formed between the first injection region and the second injection region, and the channel is made of silicon.
Preferably, step S710: a semiconductor field effect integrated circuit comprises a P-type semiconductor substrate, a first region, a second region and an insulating plate;
step S720: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed inside the first region;
step S730: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
step S740: insulating plates are respectively arranged on the upper layers of the first area and the second area.
Preferably, in step S730, the first area is coplanar with the second area, including:
step S731: the first injection region and the second injection region are injected by ion injection;
step S732: forming an N+ type conductive region in the first implantation region through ion implantation;
step S733: forming an N-type conductive region in the second implantation region by ion implantation;
step S734: making the concentration of the first injection region higher than that of the second injection region;
step S735: an N-type channel is formed between the first implant region and the second implant region.
Preferably, in step S734, an N-type channel is formed between the first implantation region and the second implantation region, including:
step S7341: forming a first insulating layer on the upper part of the first region, wherein the first insulating layer is prepared by local oxidation at 800+/-5 ℃ and under the water vapor pressure of 20 standard atmospheric pressures, and the thickness of the first insulating layer is 0.05-0.1 micrometer;
step S7342: forming a second insulating layer on the upper part of the second region, wherein the second insulating layer is formed in a dry oxygen atmosphere at the temperature of 800+/-5 ℃ and has the thickness of 0.1-0.2 microns;
step S7343: a silicon dioxide insulating layer with a thickness of 0.01-0.4 micrometers is formed over the N-type channel.
Preferably, in step S7343, the silicon oxide insulating layer includes:
step S731: attaching a photoresist mask on the upper part of the silicon dioxide insulating layer;
step S732: if the silicon dioxide insulating layer is etched, the photoresist mask is removed, and heated at 800+ -5deg.C, and an additional photoresist mask is formed on the silicon dioxide insulating layer by standard photolithography, wherein the thickness of the additional photoresist mask is 0.5-1.5 μm.
Compared with the prior art, the invention has the following advantages:
the invention provides a semiconductor field effect integrated circuit and a preparation method thereof, wherein the semiconductor field effect integrated circuit is subjected to ion implantation by using two implantation areas, an insulating plate is arranged above the ion implantation area, the contact quality of N-type conduction is improved, the silicon dioxide insulating layer is arranged, impurities can be effectively prevented from penetrating into the surface of a substrate, and the reliability and the stability of the device integrated circuit are improved by doping ions with two different concentrations of N type.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a diagram of an exemplary semiconductor field effect integrated circuit according to an embodiment of the present invention;
FIG. 2 is a diagram of a semiconductor field effect integrated circuit according to an embodiment of the present invention;
fig. 3 is a step diagram of forming an N-type channel between a first implanted region and a second implanted region in an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
The embodiment of the invention provides a semiconductor field effect integrated circuit and a preparation method thereof.
Referring to fig. 1, a semiconductor field effect integrated circuit, comprising:
the semiconductor device comprises a P-type semiconductor substrate, a first region, a second region and an insulating plate;
first region: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed inside the first region;
second region: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
insulating board: insulating plates are respectively arranged on the upper layers of the first area and the second area.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that the preparation of the semiconductor field effect integrated circuit comprises a P-type semiconductor substrate, a first area, a second area and an insulating plate. The first region is positioned on the left side of the semiconductor substrate, a first injection region is formed in the first region, the second region is positioned on the right side of the semiconductor substrate, a second injection region is formed in the second region, the first region and the second region are coplanar, and insulating plates are respectively arranged on the upper layers of the first region and the second region.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the first area and the second area are divided, ion doping with different concentrations is injected, and the injected ions are directly combined with atoms and molecules on the surface of the material, so that the material is not easy to fall off, the temperature is not controlled in the injection process, and the surface of the material which cannot be treated by the common method can be reinforced.
In another embodiment, the first region is coplanar with the second region, comprising:
the first injection region and the second injection region are injected by ion injection;
the first injection region is an N+ type conductive region;
the second injection region is an N-type conductive region;
the concentration of the first implanted region is higher than the concentration of the second implanted region.
The working principle of the technical scheme is as follows: the solution adopted in this embodiment is that an n+ type conductive region is implanted in a first implantation region in the first region, an N-type conductive region is implanted in a second implantation region in the second region, and the implantation concentration of the first implantation region is higher than that of the second implantation region.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, ions with different concentrations are conveniently implanted through the two ion implantation areas.
In another embodiment, the first implantation region and the second implantation region are implanted by ion implantation, including:
an N-type channel is formed between the first and second implant regions, the channel having a width of 20 nm and a thickness of 5 nm, and the N-type channel being on top of the P-type semiconductor.
And forming a silicon dioxide insulating layer with the thickness of 0.01-0.4 micrometers above the N-type channel.
The working principle of the technical scheme is as follows: the scheme adopted in the embodiment is that an N-type channel is formed in the first injection region and the second injection region, a source electrode of a field effect transistor of the N-type channel is connected to an N-type semiconductor, and two electrodes are led out by using metal aluminum and respectively used as a drain electrode and a source electrode. The channel width is 20 nm, the depth is 5-100 nm, and the N-type channel is on the upper layer of the P-type semiconductor. And forming a silicon dioxide insulating layer with the thickness of 0.01-0.4 microns above the N-type channel, and depositing an aluminum electrode between the drain electrode and the source electrode, namely above the silicon dioxide insulating layer with the thickness of 0.01-0.4 microns, to serve as a grid ohmic contact electrode.
The magnitude of the integrated circuit current, i.e., the subthreshold, is measured by testing the turn-on voltage of the integrated circuit as follows:
wherein ,for the starting current of the integrated circuit, +.>For the voltage of gate and source, +.>A strong inversion of the voltage for the semiconductor substrate, < >>The ratio of the potential barrier parts of the source region and the channel region is represented, q is the charge of the implanted ions, k is the number of the implanted regions, and T is the temperature of the implanted ions.
The speed of the current conduction speed can be judged according to the subthreshold swing, and whether the switching performance of the device is good or not is deduced, wherein the formula is as follows:
wherein ,for the thickness of the gate depletion layer, +.>The smaller the value of the subthreshold swing S is, the better the device performance is.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the N-type channel can be used for obtaining smaller design size, improving the switching speed of the integrated circuit, being beneficial to the integration level of the circuit, reducing the power consumption and being compatible with the bipolar circuit.
In another embodiment, the insulating plates are respectively disposed on the upper layers of the first area and the second area, and the insulating plates include:
a first insulating layer: formed at an upper portion of the first region; a second insulating layer: formed at an upper portion of the second region;
the first insulating layer is prepared by local oxidation at 800+/-5 ℃ and the water vapor pressure of 20 standard atmospheric pressures, and the thickness is 0.05-0.1 micrometer;
the second insulating layer is formed in a dry oxygen atmosphere at a temperature of 800+ -5deg.C and has a thickness of 0.1-0.2 μm.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that a first insulating layer is formed on the upper part of the first area, a second insulating layer is formed on the upper part of the second area, the first insulating layer is made by local oxidation under the water vapor pressure of 800+/-5 ℃ and 20 standard atmospheric pressures, and the thickness is 0.05-0.1 micrometer; the second insulating layer is formed in a dry oxygen atmosphere at a temperature of 800+ -5deg.C and has a thickness of 0.1-0.2 μm.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the insulation layer is subjected to local oxidation so as to prevent voltage breakdown, and the insulation layer has good chemical stability and electrical insulation property.
In another embodiment, the silicon dioxide insulating layer includes:
a photoresist mask is attached to the upper part of the silicon dioxide insulating layer, if the silicon dioxide insulating layer is etched, the photoresist mask is removed, heating is carried out at the temperature of 800+/-5 ℃, and then an additional photoresist mask is formed on the silicon dioxide insulating layer through a standard photoetching method; if the silicon dioxide insulating layer is not etched, no treatment is needed; the thickness of the additional photoresist mask is 0.5-1.5 microns.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that a photoresist mask is attached to the upper part of the silicon dioxide insulating layer, if the silicon dioxide insulating layer is etched, the photoresist mask is removed, heating is carried out at the temperature of 800+/-5 ℃, then ultraviolet light irradiates the surface of the insulating layer attached with a photoresist film through a mask plate by a standard photoetching method, and the photoresist in an exposure area is caused to react chemically; then the photoresist in the exposed area or the unexposed area is dissolved and removed by a developing technology, so that the pattern on the mask plate is copied to the photoresist film; finally, the pattern is transferred to the insulating layer by using etching technology. And forming an additional photoresist mask over the silicon dioxide insulating layer; if the silicon dioxide insulating layer is not etched, no treatment is needed; the thickness of the additional photoresist mask is 0.5-1.5 microns.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the photoresist mask is attached to the silicon dioxide insulating layer, so that the problem that an integrated circuit is electrified due to the fact that the insulating layer loses insulation effect when the silicon oxide insulating layer is etched can be effectively prevented.
In another embodiment, the material of the P-type semiconductor substrate is silicon;
the thickness of the first insulating layer and the second insulating layer is 1 to 20 times that of the silicon dioxide insulating layer;
a channel is formed between the first injection region and the second injection region, and the channel is made of silicon.
The working principle of the technical scheme is as follows: the solution adopted in this embodiment is that the material of the substrate of the P-type semiconductor is silicon, and the thickness of the first insulating layer and the second insulating layer is 1 to 20 times that of the silicon dioxide insulating layer; a channel is formed between the first injection region and the second injection region, the channel is made of silicon, and the ion concentration injected into the channel is 2-3 x.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the ion implantation concentration can be accurately and controllably mastered, and due to the continuous change of the size of the integrated circuit, various devices also change in size, and the concentration and the depth of doping can be repeatedly controlled through ion implantation.
In another embodiment, referring to fig. 2, a method for manufacturing a semiconductor field effect integrated circuit, includes the steps of:
step S710: a semiconductor field effect integrated circuit comprises a P-type semiconductor substrate, a first region, a second region and an insulating plate;
step S720: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed inside the first region;
step S730: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
step S740: insulating plates are respectively arranged on the upper layers of the first area and the second area.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that the semiconductor field effect integrated circuit comprises a P-type semiconductor substrate, a first area, a second area and an insulating plate; a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed inside the first region; a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar; insulating plates are respectively arranged on the upper layers of the first area and the second area.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the first area and the second area are divided, ion doping with different concentrations is injected, and the injected ions are directly combined with atoms and molecules on the surface of the material, so that the material is not easy to fall off, and the material is not controlled by temperature in the injection process, so that the surface of the material which cannot be treated by the common method can be reinforced.
In another embodiment, in step S730, the first region is coplanar with the second region, including:
step S731: the first injection region and the second injection region are injected by ion injection;
step S732: forming an N+ type conductive region in the first implantation region through ion implantation;
step S733: forming an N-type conductive region in the second implantation region by ion implantation;
step S734: making the concentration of the first injection region higher than that of the second injection region;
step S735: an N-type channel is formed between the first implant region and the second implant region.
The working principle of the technical scheme is as follows: the solution adopted in this embodiment is that the first implantation region and the second implantation region are implanted by ion implantation, an n+ type conductive region is formed in the first implantation region by ion implantation, an N-type conductive region is formed in the second implantation region by ion implantation, the concentration of the first implantation region is higher than that of the second implantation region, and an N-type channel is formed between the first implantation region and the second implantation region.
And forming an N-type channel in the first injection region and the second injection region, wherein the source electrode of the field effect transistor of the N-type channel is connected to the N-type semiconductor, and two electrodes are led out by using metal aluminum and respectively used as a drain electrode and a source electrode. The channel width is 20 nm, the thickness is 5 nm, and the N-type channel is on the upper layer of the P-type semiconductor. And forming a silicon dioxide insulating layer with the thickness of 0.01-0.4 micron above the N-type channel, namely a gate oxide layer, and depositing an aluminum electrode on the silicon dioxide insulating layer between the drain electrode and the source electrode to serve as an ohmic contact electrode of the gate electrode.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the N-type channel can be used for obtaining smaller design size, improving the switching speed of the integrated circuit, being beneficial to the integration level of the circuit, reducing the power consumption and being compatible with the bipolar circuit.
In another embodiment, referring to fig. 3, in step S734, an N-type channel is formed between the first implanted region and the second implanted region, including:
step S7341: forming a first insulating layer on the upper part of the first region, wherein the first insulating layer is prepared by local oxidation at 800+/-5 ℃ and under the water vapor pressure of 20 standard atmospheric pressures, and the thickness of the first insulating layer is 0.05-0.1 micrometer;
step S7342: forming a second insulating layer on the upper part of the second region, wherein the second insulating layer is formed in a dry oxygen atmosphere at the temperature of 800+/-5 ℃ and has the thickness of 0.1-0.2 microns;
step S7343: and forming a silicon dioxide insulating layer, namely a gate oxide layer, with the thickness of 0.01-0.4 micrometers above the N-type channel.
The working principle of the technical scheme is as follows: the scheme adopted in the embodiment is that a first insulating layer is formed on the upper part of the first area, wherein the first insulating layer is prepared by local oxidation at 800+/-5 ℃ and under the water vapor pressure of 20 standard atmospheres, and the thickness is 0.05-0.1 micrometer; forming a second insulating layer on the upper part of the second region, wherein the second insulating layer is formed in a dry oxygen atmosphere at the temperature of 800+/-5 ℃ and has the thickness of 0.1-0.2 microns; a silicon dioxide insulating layer, namely a gate oxide layer, with a thickness of 0.01-0.4 micrometers is formed over the N-type channel.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the N-type channel can be used for obtaining smaller design size, improving the switching speed of the integrated circuit, being beneficial to the integration level of the circuit, reducing the power consumption and being compatible with the bipolar circuit.
In another embodiment, in step S7343, the second silicon oxide insulating layer includes:
step S731: attaching a photoresist mask on the upper part of the silicon dioxide insulating layer;
step S732: if the silicon dioxide insulating layer is etched, the photoresist mask is removed and heated at 800 + -5 deg.c, and then an additional photoresist mask is formed on the silicon dioxide insulating layer by a standard photolithography method, the additional photoresist mask having a thickness of 0.5-1.5 μm.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that a photoresist mask is attached to the upper part of the silicon dioxide insulating layer; if the silicon dioxide insulating layer is etched, the photoresist mask is removed and heated at 800 + -5 deg.c, and then an additional photoresist mask is formed on the silicon dioxide insulating layer by a standard photolithography method, the additional photoresist mask having a thickness of 0.5-1.5 μm.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the photoresist mask is attached to the silicon dioxide insulating layer, so that the problem that an integrated circuit is electrified due to the fact that the insulating layer loses insulation effect when the silicon oxide insulating layer is etched can be effectively prevented.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (6)
1. A semiconductor field effect integrated circuit, comprising:
the semiconductor device comprises a P-type semiconductor substrate, a first region, a second region and an insulating plate;
first region: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed inside the first region;
second region: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
insulating board: insulating plates are respectively arranged on the upper layers of the first area and the second area;
the first region is coplanar with the second region, comprising:
the first injection region and the second injection region are injected by ion injection;
the first injection region is an N+ type conductive region;
the second injection region is an N-type conductive region;
the concentration of the first injection region is higher than that of the second injection region;
the first implantation region and the second implantation region are implanted by ion implantation, and the method comprises the following steps:
forming an N-type channel between the first injection region and the second injection region, wherein the width of the channel is 20 nanometers, the depth is 5-100 nanometers, and the N-type channel is arranged on the upper layer of the P-type semiconductor;
forming a silicon dioxide insulating layer with the thickness of 0.01-0.4 micrometers above the N-type channel;
the magnitude of the integrated circuit current, i.e., the subthreshold, is measured by testing the turn-on voltage of the integrated circuit as follows:
；
wherein ,for the starting current of the integrated circuit, +.>For the voltage of gate and source, +.>A strong inversion of the voltage for the semiconductor substrate, < >>The ratio of the potential barrier parts of the source region and the channel region is represented, q is the charge of the injected ions, k is the number of the injected regions, and T is the temperature of the injected ions;
the speed of the current conduction speed can be judged according to the subthreshold swing, and whether the switching performance of the device is good or not is deduced, wherein the formula is as follows:
；
wherein ,for the thickness of the gate depletion layer, +.>The smaller the value of the subthreshold swing S is, the better the device performance is.
2. The semiconductor field effect integrated circuit as claimed in claim 1, wherein insulating plates are respectively disposed on the first region and the second region, and the semiconductor field effect integrated circuit comprises:
a first insulating layer: formed at an upper portion of the first region; a second insulating layer: formed at an upper portion of the second region;
the first insulating layer is prepared by local oxidation at 800+/-5 ℃ and the water vapor pressure of 20 standard atmospheric pressures, and the thickness is 0.05-0.1 micrometer;
the second insulating layer is formed in a dry oxygen atmosphere at a temperature of 800+ -5deg.C and has a thickness of 0.1-0.2 μm.
3. The semiconductor field effect integrated circuit of claim 1, wherein the silicon dioxide insulating layer comprises:
a photoresist mask is attached to the upper part of the silicon dioxide insulating layer, if the silicon dioxide insulating layer is etched, the photoresist mask is removed, heating is carried out at the temperature of 800+/-5 ℃, and an additional photoresist mask is formed on the silicon dioxide insulating layer through a standard photoetching method; if the silicon dioxide insulating layer is not etched, no treatment is needed; the thickness of the additional photoresist mask is 0.5-1.5 microns.
4. The semiconductor field effect integrated circuit of claim 1, comprising:
the P-type semiconductor substrate is made of silicon;
the thickness of the first insulating layer and the second insulating layer is 1 to 20 times that of the silicon dioxide insulating layer;
a channel is formed between the first injection region and the second injection region, and the channel is made of silicon.
5. A method for fabricating a semiconductor field effect integrated circuit, comprising the steps of:
step S710: a semiconductor field effect integrated circuit comprises a P-type semiconductor substrate, a first region, a second region and an insulating plate;
step S720: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed inside the first region;
step S730: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
step S740: insulating plates are respectively arranged on the upper layers of the first area and the second area;
the first region is coplanar with the second region, comprising:
the first injection region and the second injection region are injected by ion injection;
the first injection region is an N+ type conductive region;
the second injection region is an N-type conductive region;
the concentration of the first injection region is higher than that of the second injection region;
the first implantation region and the second implantation region are implanted by ion implantation, and the method comprises the following steps:
forming an N-type channel between the first injection region and the second injection region, wherein the width of the channel is 20 nanometers, the depth is 5-100 nanometers, and the N-type channel is arranged on the upper layer of the P-type semiconductor;
forming a silicon dioxide insulating layer with the thickness of 0.01-0.4 micrometers above the N-type channel;
the magnitude of the integrated circuit current, i.e., the subthreshold, is measured by testing the turn-on voltage of the integrated circuit as follows:
；
wherein ,for the starting current of the integrated circuit, +.>For the voltage of gate and source, +.>A strong inversion of the voltage for the semiconductor substrate, < >>The ratio of the potential barrier parts of the source region and the channel region is represented, q is the charge of the injected ions, k is the number of the injected regions, and T is the temperature of the injected ions;
the speed of the current conduction speed can be judged according to the subthreshold swing, and whether the switching performance of the device is good or not is deduced, wherein the formula is as follows:
；
wherein ,for the thickness of the gate depletion layer, +.>The smaller the value of the subthreshold swing S is, the better the device performance is.
6. The method of manufacturing a semiconductor field effect integrated circuit as claimed in claim 5, wherein the forming a silicon dioxide insulating layer having a thickness of 0.01-0.4 μm over the N-type channel comprises:
step S731: attaching a photoresist mask on the upper part of the silicon dioxide insulating layer;
step S732: if the silicon dioxide insulating layer is etched, the photoresist mask is removed, and heated at 800+ -5deg.C, and an additional photoresist mask is formed on the silicon dioxide insulating layer by standard photolithography, wherein the thickness of the additional photoresist mask is 0.5-1.5 μm.
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