CN115549676A - A Reference Sampling Phase Locked Loop Adapted to Low Voltage Applications - Google Patents

The invention relates to a reference sampling phase-locked loop suitable for low-voltage application, which comprises: the device comprises a reference sampling phase discriminator module, a low-pass filter module, a voltage-controlled oscillator, a frequency divider module and a clock signal generating module. The invention reduces the on-resistance of the sampling switch by adopting the high-level boost inverter, and reduces the sampling time constant under low voltage, thereby realizing the normal sampling and holding function. And meanwhile, the noise is improved by using a larger sampling capacitor, and the normal sampling operation and the excellent clock jitter performance of the phase-locked loop under low voltage are realized. And a low-pass filter is added at the output end of the reference sampling phase discriminator, and a high-frequency pole is introduced, so that the reference stray is improved on the premise of not influencing the phase margin. And the combination of the current mode logic frequency divider and the multi-mode programmable frequency divider is adopted to realize the normal operation of the reference sampling phase-locked loop under low voltage and the excellent stray and clock jitter performance.

一种适应低压应用的参考采样锁相环A Reference Sampling Phase Locked Loop Adapted to Low Voltage Applications

技术领域technical field

本发明属于半导体集成电路技术领域，具体涉及一种适应低压应用的参考采样锁相环。The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a reference sampling phase-locked loop suitable for low-voltage applications.

背景技术Background technique

对于锁相环系统，时钟抖动、杂散、相位噪声、功耗和面积等性能指标都是至关重要的。传统的电荷泵锁相环由于相位噪声和时钟抖动性能的提升需要牺牲较大的功耗和滤波器面积的问题而受到限制，从而推动了人们对更好的锁相环架构的需求。过去提出的亚采样锁相环和注入锁定锁相环也分别存在着鉴相范围太小和杂散受谐波影响的问题。For PLL systems, performance metrics such as clock jitter, spurs, phase noise, power consumption, and area are critical. Traditional charge-pump phase-locked loops are limited by the need to sacrifice large power and filter area to improve phase noise and clock jitter performance, driving the need for better phase-locked loop architectures. The sub-sampling PLL and injection-locked PLL proposed in the past also have the problems that the phase detection range is too small and the spurs are affected by harmonics.

而近几年提出的参考采样锁相环架构，通过使用参考采样鉴相器(RSPD)将锁相环的输入参考信号和反馈信号的相位差转换为电压进行比较来提高带内增益，从而实现相位噪声和时钟抖动的优化。为了进一步降低锁相环的功耗，降低电源电压是最直接的方法，然而，采样器在低压工作时的导通电阻RON增大，采样时间常数τ增大，造成采样器无法实现正常的采样保持功能，参考采样锁相环无法实现正常的锁相功能。同时只能使用更小的采样电容来维持采样时间常数远小于参考周期τ＝RC<<TREF，造成采样热噪声的恶化。低压工作下，数字电路的功耗降低，代价是工作速度的降低，造成分频器无法在高频工作时实现正常的分频功能，锁相环的工作频率受到限制。The reference sampling phase-locked loop architecture proposed in recent years uses a reference sampling phase detector (RSPD) to convert the phase difference between the input reference signal and the feedback signal of the phase-locked loop into a voltage for comparison to improve the in-band gain, thereby realizing Optimization of phase noise and clock jitter. In order to further reduce the power consumption of the phase-locked loop, reducing the power supply voltage is the most direct method. However, when the sampler is working at low voltage, the on-resistance RON increases, and the sampling time constant τ increases, which makes the sampler unable to achieve normal sampling. Hold function, the reference sampling phase-locked loop cannot realize the normal phase-lock function. At the same time, only a smaller sampling capacitor can be used to maintain the sampling time constant much smaller than the reference period τ=RC<<TREF, resulting in deterioration of sampling thermal noise. Under low-voltage operation, the power consumption of the digital circuit is reduced, and the price is the reduction of the working speed, which makes the frequency divider unable to realize the normal frequency division function when it works at high frequency, and the working frequency of the phase-locked loop is limited.

发明内容Contents of the invention

为了解决现有技术中存在的上述问题，本发明提供了一种适应低压应用的参考采样锁相环。本发明要解决的技术问题通过以下技术方案实现：In order to solve the above-mentioned problems in the prior art, the present invention provides a reference sampling phase-locked loop suitable for low-voltage applications. The technical problem to be solved in the present invention is realized through the following technical solutions:

本发明提供了一种适应低压应用的参考采样锁相环，包括：参考采样鉴相器模块、低通滤波器模块、压控振荡器、分频器模块和时钟信号生成模块，其中，The invention provides a reference sampling phase-locked loop suitable for low-voltage applications, including: a reference sampling phase detector module, a low-pass filter module, a voltage-controlled oscillator, a frequency divider module and a clock signal generation module, wherein,

所述参考采样鉴相器模块的参考信号输入端输入差分参考信号，输出端连接所述低通滤波器模块的输入端；所述低通滤波器模块的输出端连接所述压控振荡器的输入端，所述压控振荡器的输出信号作为锁相环输出的时钟信号；所述分频器模块的输入端连接所述压控振荡器的输出端，输出端连接所述时钟信号生成模块的输入端；所述时钟信号生成模块的输出端连接所述参考采样鉴相器模块的反馈信号输入端；The reference signal input terminal of the reference sampling phase detector module inputs a differential reference signal, and the output terminal is connected to the input terminal of the low-pass filter module; the output terminal of the low-pass filter module is connected to the voltage-controlled oscillator The input terminal, the output signal of the voltage-controlled oscillator is used as the clock signal output by the phase-locked loop; the input terminal of the frequency divider module is connected to the output terminal of the voltage-controlled oscillator, and the output terminal is connected to the clock signal generation module the input end of the clock signal generation module; the output end of the clock signal generation module is connected to the feedback signal input end of the reference sampling phase detector module;

所述参考采样鉴相器模块对输入的所述差分参考信号进行采样保持跟踪，得到差分采样输出信号；所述低通滤波器模块对所述差分采样输出信号进行低通滤波处理，得到纹波减小后的差分电压信号；所述差分电压信号作为所述压控振荡器的控制电压控制所述压控振荡器的输出频率；所述分频器模块对所述压控振荡器的输出信号进行分频，得到分频输出信号；所述时钟信号生成模块根据所述分频输出信号产生反馈时钟信号，所述参考采样鉴相器模块根据所述反馈时钟信号对所述差分参考信号进行采样。The reference sampling phase detector module performs sample-hold tracking on the input differential reference signal to obtain a differential sampling output signal; the low-pass filter module performs low-pass filtering processing on the differential sampling output signal to obtain a ripple The reduced differential voltage signal; the differential voltage signal is used as the control voltage of the voltage-controlled oscillator to control the output frequency of the voltage-controlled oscillator; the output signal of the voltage-controlled oscillator by the frequency divider module Perform frequency division to obtain a frequency division output signal; the clock signal generation module generates a feedback clock signal according to the frequency division output signal, and the reference sampling phase detector module samples the differential reference signal according to the feedback clock signal .

在本发明的一个实施例中，所述参考采样鉴相器模块包括两个参考采样鉴相器，两个所述参考采样鉴相器的参考信号输入端对应输入第一差分参考信号和第二差分参考信号，输出端对应输出第一差分采样输出信号和第二差分采样输出信号。In one embodiment of the present invention, the reference sampling phase detector module includes two reference sampling phase detectors, and the reference signal input terminals of the two reference sampling phase detectors correspondingly input the first differential reference signal and the second For the differential reference signal, the output terminal correspondingly outputs the first differential sampling output signal and the second differential sampling output signal.

在本发明的一个实施例中，低通滤波器模块包括两个低通滤波器，两个所述低通滤波器与两个所述参考采样鉴相器对应连接，分别对所述第一差分采样输出信号和所述第二差分采样输出信号进行低通滤波处理，对应得到第一差分电压信号和第二差分电压信号。In one embodiment of the present invention, the low-pass filter module includes two low-pass filters, and the two low-pass filters are correspondingly connected to the two reference sampling phase detectors, respectively for the first differential The sampled output signal and the second differential sampled output signal are subjected to low-pass filtering processing to obtain a first differential voltage signal and a second differential voltage signal correspondingly.

在本发明的一个实施例中，所述低通滤波器为无源滤波器、开关电容滤波器或有源滤波器。In one embodiment of the present invention, the low-pass filter is a passive filter, a switched capacitor filter or an active filter.

在本发明的一个实施例中，所述分频器模块包括依次连接的第一分频器和第二分频器，所述第一分频器的输入端连接所述压控振荡器的输出端，所述第二分频器的输出端连接所述时钟信号生成模块的输入端；In one embodiment of the present invention, the frequency divider module includes a first frequency divider and a second frequency divider connected in sequence, the input end of the first frequency divider is connected to the output of the voltage controlled oscillator terminal, the output terminal of the second frequency divider is connected to the input terminal of the clock signal generation module;

其中，所述第一分频器为注入锁定分频器、电流模式逻辑分频器、真单相时钟触发器分频器或米勒分频器；所述第二分频器为多模可编程分频器。Wherein, the first frequency divider is an injection locked frequency divider, a current mode logic frequency divider, a true single-phase clock flip-flop frequency divider or a Miller frequency divider; the second frequency divider is a multi-mode programmable frequency divider Program the divider.

在本发明的一个实施例中，所述时钟信号生成模块包括两相非交叠时钟生成器和两个高电平升压反相器，其中，In one embodiment of the present invention, the clock signal generating module includes a two-phase non-overlapping clock generator and two high-level boost inverters, wherein,

所述两相非交叠时钟生成器的输入端连接所述分频器模块的输出端，输出端与两个所述高电平升压反相器对应连接；The input end of the two-phase non-overlapping clock generator is connected to the output end of the frequency divider module, and the output end is correspondingly connected to the two high-level boost inverters;

所述两相非交叠时钟生成器对所述分频输出信号进行时序处理，得到第一两相非交叠的窄脉冲信号和第二两相非交叠的窄脉冲信号；The two-phase non-overlapping clock generator performs timing processing on the frequency division output signal to obtain a first two-phase non-overlapping narrow pulse signal and a second two-phase non-overlapping narrow pulse signal;

所述第一两相非交叠的窄脉冲信号经过对应的高电平升压反相器升压处理得到第一反馈时钟信号；The first two-phase non-overlapping narrow pulse signal is boosted by a corresponding high-level boost inverter to obtain a first feedback clock signal;

所述第二两相非交叠的窄脉冲信号经过对应的高电平升压反相器升压处理得到第二反馈时钟信号；The second two-phase non-overlapping narrow pulse signal is boosted by a corresponding high-level boost inverter to obtain a second feedback clock signal;

所述第一反馈时钟信号和所述第二反馈时钟信号分别输入两个所述参考采样鉴相器的反馈信号输入端。The first feedback clock signal and the second feedback clock signal are respectively input to the feedback signal input terminals of the two reference sampling phase detectors.

在本发明的一个实施例中，所述高电平升压反相器包括第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管和第一电容，其中，In an embodiment of the present invention, the high-level boost inverter includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a first capacitor, wherein ,

所述第一MOS管的源极和所述第三MOS管的源极均连接电源端；Both the source of the first MOS transistor and the source of the third MOS transistor are connected to a power supply terminal;

所述第一MOS管的栅极分别连接所述第二MOS管的栅极、所述第四MOS管的栅极和所述第五MOS管的栅极，漏极分别连接所述第二MOS管的漏极和所述第一电容的第一极板；The gate of the first MOS transistor is respectively connected to the gate of the second MOS transistor, the gate of the fourth MOS transistor and the gate of the fifth MOS transistor, and the drain is respectively connected to the second MOS transistor. the drain of the tube and the first plate of the first capacitor;

所述第二MOS管的源极和所述第五MOS管的源极均连接接地端；Both the source of the second MOS transistor and the source of the fifth MOS transistor are connected to a ground terminal;

所述第三MOS管的漏极分别连接所述第一电容的第二极板和所述第四MOS管的源极，栅极分别连接所述第四MOS管的漏极和所述第五MOS管的漏极；The drain of the third MOS transistor is respectively connected to the second plate of the first capacitor and the source of the fourth MOS transistor, and the gate is respectively connected to the drain of the fourth MOS transistor and the fifth MOS transistor. The drain of the MOS tube;

所述第一MOS管的栅极作为所述高电平升压反相器的输入端，所述第三MOS管的栅极作为所述高电平升压反相器的输出端。The gate of the first MOS transistor serves as an input terminal of the high-level boost inverter, and the gate of the third MOS transistor serves as an output terminal of the high-level boost inverter.

在本发明的一个实施例中，所述参考采样鉴相器包括第一采样开关、第二采样开关、第一采样电容和第二采样电容，其中，In one embodiment of the present invention, the reference sampling phase detector includes a first sampling switch, a second sampling switch, a first sampling capacitor and a second sampling capacitor, wherein,

所述第一采样开关和所述第二采样开关串联，所述第一采样开关的第一端作为所述参考采样鉴相器的参考信号输入端，所述第二采样开关的第二端作为所述参考采样鉴相器的输出端；The first sampling switch and the second sampling switch are connected in series, the first terminal of the first sampling switch is used as the reference signal input terminal of the reference sampling phase detector, and the second terminal of the second sampling switch is used as The output terminal of the reference sampling phase detector;

所述第一采样电容连接在所述第一采样开关的第二端与接地端之间，所述第二采样电容连接在所述第二采样开关的第二端与接地端之间；The first sampling capacitor is connected between the second terminal of the first sampling switch and the ground terminal, and the second sampling capacitor is connected between the second terminal of the second sampling switch and the ground terminal;

所述第一采样开关根据所述第一反馈时钟信号实现开启或关断，所述第二采样开关根据所述第二反馈时钟信号实现开启或关断。The first sampling switch is turned on or off according to the first feedback clock signal, and the second sampling switch is turned on or off according to the second feedback clock signal.

与现有技术相比，本发明的有益效果在于：Compared with prior art, the beneficial effect of the present invention is:

1.本发明的适应低压应用的参考采样锁相环，通过在参考采样鉴相器的输出端添加低通滤波器，引入高频极点，在不影响相位裕度的前提下，对参考杂散进行改善。1. The reference sampling phase-locked loop adapting to low-voltage application of the present invention, by adding a low-pass filter at the output end of the reference sampling phase detector, introduces a high-frequency pole, and under the premise of not affecting the phase margin, the reference spurious Make improvements.

2.本发明的适应低压应用的参考采样锁相环，利用高电平升压反相器减低采样开关的导通电阻，实现采样器在低压下的正常采样保持功能。2. The reference sampling phase-locked loop adapted to low-voltage applications of the present invention uses a high-level boost inverter to reduce the on-resistance of the sampling switch, so as to realize the normal sampling and holding function of the sampler under low voltage.

3.本发明的适应低压应用的参考采样锁相环，采用两种分频器，利用高速分频器降低多模可编程分频器所需的工作频率，解决由于低压工作带来的分频器工作速度降低的问题，从而提高锁相环可实现的工作频率。3. The reference sampling phase-locked loop adapted to low-voltage applications of the present invention adopts two kinds of frequency dividers, utilizes high-speed frequency dividers to reduce the required operating frequency of multi-mode programmable frequency dividers, and solves the frequency division caused by low-voltage operation The problem of reducing the working speed of the device, thereby increasing the achievable working frequency of the phase-locked loop.

上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

附图说明Description of drawings

图1是本发明实施例提供的一种适应低压应用的参考采样锁相环的模块框图；FIG. 1 is a block diagram of a reference sampling phase-locked loop adapted to low-voltage applications provided by an embodiment of the present invention;

图2是本发明实施例提供的一种适应低压应用的参考采样锁相环的结构框图；FIG. 2 is a structural block diagram of a reference sampling phase-locked loop adapted to low-voltage applications provided by an embodiment of the present invention;

图3是本发明实施例提供的一种参考采样鉴相器的电路图；Fig. 3 is a circuit diagram of a reference sampling phase detector provided by an embodiment of the present invention;

图4是本发明实施例提供的一种参考采样鉴相器的工作原理示意图；Fig. 4 is a schematic diagram of the working principle of a reference sampling phase detector provided by an embodiment of the present invention;

图5是本发明实施例提供的一种高电平升压反相器的电路图；FIG. 5 is a circuit diagram of a high-level boost inverter provided by an embodiment of the present invention;

图6是本发明实施例提供的一种高电平升压反相器的输入输出波形图；FIG. 6 is an input and output waveform diagram of a high-level boost inverter provided by an embodiment of the present invention;

具体实施方式detailed description

为了进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及具体实施方式，对依据本发明提出的一种适应低压应用的参考采样锁相环进行详细说明。In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, a reference sampling phase-locked loop suitable for low-voltage applications proposed according to the present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

有关本发明的前述及其他技术内容、特点及功效，在以下配合附图的具体实施方式详细说明中即可清楚地呈现。通过具体实施方式的说明，可对本发明为达成预定目的所采取的技术手段及功效进行更加深入且具体地了解，然而所附附图仅是提供参考与说明之用，并非用来对本发明的技术方案加以限制。The aforementioned and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description of specific implementations with accompanying drawings. Through the description of specific embodiments, the technical means and effects of the present invention to achieve the intended purpose can be understood more deeply and specifically, but the accompanying drawings are only for reference and description, and are not used to explain the technical aspects of the present invention. program is limited.

实施例一Embodiment one

请结合参见图1和图2，图1是本发明实施例提供的一种适应低压应用的参考采样锁相环的模块框图；图2是本发明实施例提供的一种适应低压应用的参考采样锁相环的结构框图。如图所示，本实施例的适应低压应用的参考采样锁相环，包括：参考采样鉴相器模块、低通滤波器模块、压控振荡器(VCO)、分频器模块和时钟信号生成模块。其中，参考采样鉴相器模块的参考信号输入端输入差分参考信号，输出端连接低通滤波器模块的输入端；低通滤波器模块的输出端连接压控振荡器的输入端，压控振荡器的输出信号FOUT作为锁相环输出的时钟信号；分频器模块的输入端连接压控振荡器的输出端，输出端连接时钟信号生成模块的输入端；时钟信号生成模块的输出端连接参考采样鉴相器模块的反馈信号输入端。Please refer to Figure 1 and Figure 2 in combination, Figure 1 is a block diagram of a reference sampling phase-locked loop adapted to low-voltage applications provided by an embodiment of the present invention; Figure 2 is a reference sampling phase-locked loop adapted to low-voltage applications provided by an embodiment of the present invention Block diagram of a phase-locked loop. As shown in the figure, the reference sampling phase-locked loop adapted to low-voltage applications of this embodiment includes: a reference sampling phase detector module, a low-pass filter module, a voltage-controlled oscillator (VCO), a frequency divider module and a clock signal generation module. Wherein, the reference signal input terminal of the reference sampling phase detector module inputs a differential reference signal, and the output terminal is connected to the input terminal of the low-pass filter module; the output terminal of the low-pass filter module is connected to the input terminal of the voltage-controlled oscillator, and the voltage-controlled oscillation The output signal FOUT of the device is used as the clock signal output by the phase-locked loop; the input end of the frequency divider module is connected to the output end of the voltage-controlled oscillator, and the output end is connected to the input end of the clock signal generation module; the output end of the clock signal generation module is connected to the reference Feedback signal input terminal of sampling phase detector module.

具体地，参考采样鉴相器模块对输入的差分参考信号进行采样保持跟踪，得到差分采样输出信号；低通滤波器模块对差分采样输出信号进行低通滤波处理，得到纹波减小后的差分电压信号；差分电压信号作为压控振荡器的控制电压控制压控振荡器的输出频率；分频器模块对压控振荡器的输出信号FOUT进行分频，得到分频输出信号；时钟信号生成模块根据分频输出信号产生反馈时钟信号，参考采样鉴相器模块根据反馈时钟信号对差分参考信号进行采样。Specifically, the reference sampling phase detector module performs sample-hold tracking on the input differential reference signal to obtain the differential sampling output signal; the low-pass filter module performs low-pass filtering on the differential sampling output signal to obtain the differential Voltage signal; the differential voltage signal is used as the control voltage of the voltage-controlled oscillator to control the output frequency of the voltage-controlled oscillator; the frequency divider module divides the frequency of the output signal FOUT of the voltage-controlled oscillator to obtain a frequency-divided output signal; the clock signal generation module A feedback clock signal is generated according to the frequency division output signal, and the reference sampling phase detector module samples the differential reference signal according to the feedback clock signal.

在本实施例中，参考采样鉴相器模块包括两个参考采样鉴相器(RSPD)，两个参考采样鉴相器的参考信号输入端对应输入第一差分参考信号FREFP和第二差分参考信号FREFN，输出端对应输出第一差分采样输出信号VSP和第二差分采样输出信号VSN。In this embodiment, the reference sampling phase detector module includes two reference sampling phase detectors (RSPD), and the reference signal input terminals of the two reference sampling phase detectors correspondingly input the first differential reference signal FREFP and the second differential reference signal FREFN, the output terminal correspondingly outputs the first differential sampling output signal VSP and the second differential sampling output signal VSN.

低通滤波器模块包括两个低通滤波器(LPF)，两个低通滤波器与两个参考采样鉴相器对应连接，分别对第一差分采样输出信号VSP和第二差分采样输出信号VSN进行低通滤波处理，对应得到第一差分电压信号VCP和第二差分电压信号VCN。The low-pass filter module includes two low-pass filters (LPF), and the two low-pass filters are correspondingly connected with two reference sampling phase detectors, respectively for the first differential sampling output signal VSP and the second differential sampling output signal VSN The low-pass filtering process is performed to correspondingly obtain the first differential voltage signal VCP and the second differential voltage signal VCN.

可选地，本实施例的两个低通滤波器可以是无源滤波器、开关电容滤波器或有源滤波器，在此不做限制。可选地，低通滤波器为一阶低通滤波器，也可以为其他阶的低通滤波器，具体阶数在此不做限制。Optionally, the two low-pass filters in this embodiment may be passive filters, switched capacitor filters or active filters, which are not limited here. Optionally, the low-pass filter is a first-order low-pass filter, or a low-pass filter of other orders, and the specific order is not limited here.

在本实施例中，在参考采样鉴相器的输出端添加低通滤波器，引入高频极点，在不影响相位裕度的前提下，对参考杂散进行改善。具体原理如下：设该低通滤波器LPF为一阶滤波器，其传递函数为1/(1+s*R*C)，则引入高频极点wp＝-1/R*C，其中s为复频率，R为滤波电阻，C为滤波电容，来实现低通滤波的功能。那么，在高频极点wp频率处，幅值曲线的斜率额外变化-20dB/dec，所以可以增强对高频噪声的抑制能力。设一个环路包含一个零点wz和两个极点wp1，wp2，则相位裕度PM＝180°+arctan(wc/wz)-arctan(wc/wp1)-arctan(wc/wp2)。由相位裕度PM公式可以看出，当高频极点wp远大于锁相环环路带宽wc时，则高频极点wp不影响锁相环的相位裕度。In this embodiment, a low-pass filter is added at the output end of the reference sampling phase detector to introduce a high-frequency pole, so as to improve the reference spur without affecting the phase margin. The specific principle is as follows: if the low-pass filter LPF is a first-order filter, and its transfer function is 1/(1+s*R*C), then the high-frequency pole wp=-1/R*C is introduced, where s is Complex frequency, R is the filter resistor, and C is the filter capacitor to realize the function of low-pass filter. Then, at the high-frequency pole wp frequency, the slope of the amplitude curve additionally changes by -20dB/dec, so the ability to suppress high-frequency noise can be enhanced. Suppose a loop contains a zero point wz and two poles wp1, wp2, then the phase margin PM=180°+arctan(wc/wz)-arctan(wc/wp1)-arctan(wc/wp2). It can be seen from the phase margin PM formula that when the high-frequency pole wp is much larger than the loop bandwidth wc of the phase-locked loop, the high-frequency pole wp does not affect the phase margin of the phase-locked loop.

进一步地，分频器模块包括依次连接的第一分频器和第二分频器，第一分频器的输入端连接压控振荡器的输出端，第二分频器的输出端连接时钟信号生成模块的输入端。Further, the frequency divider module includes a first frequency divider and a second frequency divider connected in sequence, the input terminal of the first frequency divider is connected to the output terminal of the voltage controlled oscillator, and the output terminal of the second frequency divider is connected to the clock Input to the signal generation block.

可选地，第一分频器为注入锁定分频器(ILFD)、电流模式逻辑分频器(CML)、真单相时钟触发器分频器(ETSPC)或米勒分频器(Miller)。Optionally, the first frequency divider is an injection locked frequency divider (ILFD), a current mode logic frequency divider (CML), a true single-phase clock flip-flop frequency divider (ETSPC) or a Miller frequency divider (Miller) .

在本实施例中，第一分频器为电流模式逻辑四分频器(CML_DIV4)，第二分频器为多模可编程分频器(MMDIV)。In this embodiment, the first frequency divider is a current mode logic frequency divider by four (CML_DIV4), and the second frequency divider is a multi-mode programmable frequency divider (MMDIV).

具体地，压控振荡器的输出信号FOUT经过电流模式逻辑四分频器(CML_DIV4)进行四分频，得到四分频输出信号F1，电流模式逻辑四分频器用于将输出信号FOUT的频率降低到多模可编程分频器(MMDIV)的工作频率，四分频输出信号F1经过多模可编程分频器的分频得到作为锁相环反馈信号的分频输出信号FDIV。Specifically, the output signal FOUT of the voltage-controlled oscillator is divided by four through the current-mode logic divider (CML_DIV4) to obtain the four-frequency output signal F1, and the current-mode logic divider is used to reduce the frequency of the output signal FOUT To the working frequency of the multi-mode programmable frequency divider (MMDIV), the frequency-divided output signal F1 is divided by the multi-mode programmable frequency divider to obtain the frequency-divided output signal FDIV as the feedback signal of the phase-locked loop.

在本实施例中，采用电流模式逻辑四分频器来降低多模可编程分频器所需的工作频率，解决由于低压工作带来的分频器工作速度降低的问题，从而提高锁相环可实现的工作频率。In this embodiment, a current-mode logic four-frequency divider is used to reduce the required operating frequency of the multi-mode programmable frequency divider, and solve the problem of reduced operating speed of the frequency divider due to low-voltage operation, thereby improving the phase-locked loop. achievable operating frequency.

进一步地，时钟信号生成模块包括两相非交叠时钟生成器(Nonoverlap ClockGeneration)和两个高电平升压反相器(HBINV)，其中，两相非交叠时钟生成器的输入端连接分频器模块的输出端，输出端与两个高电平升压反相器对应连接。Further, the clock signal generation module includes a two-phase nonoverlap clock generator (Nonoverlap ClockGeneration) and two high-level boost inverters (HBINV), wherein the input terminals of the two-phase nonoverlap clock generator are connected to the branch The output terminal of the frequency converter module is correspondingly connected with two high-level boost inverters.

具体地，两相非交叠时钟生成器对分频输出信号进行时序处理，得到第一两相非交叠的窄脉冲信号V1和第二两相非交叠的窄脉冲信号V2；第一两相非交叠的窄脉冲信号V1经过对应的高电平升压反相器升压处理得到第一反馈时钟信号CK1；第二两相非交叠的窄脉冲信号V2经过对应的高电平升压反相器升压处理得到第二反馈时钟信号CK2；第一反馈时钟信号CK1和第二反馈时钟信号CK2分别输入两个参考采样鉴相器的反馈信号输入端。Specifically, the two-phase non-overlapping clock generator performs sequential processing on the frequency-divided output signal to obtain the first two-phase non-overlapping narrow pulse signal V1 and the second two-phase non-overlapping narrow pulse signal V2; the first two The non-overlapping narrow pulse signal V1 is boosted by the corresponding high-level boost inverter to obtain the first feedback clock signal CK1; the second two-phase non-overlapping narrow pulse signal V2 is boosted by the corresponding high-level The second feedback clock signal CK2 is obtained through step-up processing of the voltage inverter; the first feedback clock signal CK1 and the second feedback clock signal CK2 are respectively input to the feedback signal input terminals of the two reference sampling phase detectors.

在本实施例中，第一两相非交叠的窄脉冲信号V1和第二两相非交叠的窄脉冲信号V2工作在分频频率，第一反馈时钟信号CK1和第二反馈时钟信号CK2为在低压下得到高摆幅的两相非交叠窄脉冲信号。In this embodiment, the first two-phase non-overlapping narrow pulse signal V1 and the second two-phase non-overlapping narrow pulse signal V2 work at the frequency division frequency, the first feedback clock signal CK1 and the second feedback clock signal CK2 In order to obtain high-swing two-phase non-overlapping narrow pulse signals at low voltage.

本实施例的适应低压应用的参考采样锁相环的工作原理为：首先经过高电平升压反相器升压的反馈时钟信号CK1和CK2，通过参考采样鉴相器对输入的差分参考信号FREFP和FREFN进行采样保持跟踪，得到差分采样输出信号VSP和VSN。低通滤波器对差分采样输出信号VSP和VSN进行低通滤波，得到纹波减小后的差分电压信号VCP和VCN。低通滤波器的差分输出电压信号VCP和VCN作为压控振荡器的控制电压来控制压控振荡器的输出频率，得到输出信号FOUT。压控振荡器的输出信号FOUT经过电流模式逻辑四分频器进行四分频，得到四分频输出信号F1。四分频输出信号F1经过多模可编程分频器的分频得到作为锁相环反馈信号的分频输出信号FDIV。分频输出信号FDIV经过两相非交叠时钟产生器的时序处理，产生工作在分频频率的两相非交叠的窄脉冲信号V1和V2。两相非交叠的窄脉冲信号V1和V2经过高电平升压反相器的升压功能，在低压下得到高摆幅的两相非交叠窄脉冲信号CK1和CK2(也就是反馈时钟信号)。锁相环通过负反馈，按照以上过程循环工作，直到实现压控振荡器的输出信号FOUT和输入的差分参考信号FREFP和FREFN的相位相等，也就完成了锁相环相位锁定的功能。The working principle of the reference sampling phase-locked loop adapted to low-voltage applications in this embodiment is as follows: firstly, the feedback clock signals CK1 and CK2 boosted by the high-level boost inverter, and the input differential reference signal through the reference sampling phase detector FREFP and FREFN sample and hold tracking to obtain differential sampling output signals VSP and VSN. The low-pass filter performs low-pass filtering on the differential sampling output signals VSP and VSN to obtain differential voltage signals VCP and VCN with reduced ripple. The differential output voltage signals VCP and VCN of the low-pass filter are used as the control voltage of the voltage-controlled oscillator to control the output frequency of the voltage-controlled oscillator to obtain the output signal FOUT. The output signal FOUT of the voltage-controlled oscillator is divided by four through the current-mode logic frequency divider to obtain a four-frequency output signal F1. The four-frequency division output signal F1 is divided by the multi-mode programmable frequency divider to obtain the frequency division output signal FDIV as the feedback signal of the phase-locked loop. The frequency-divided output signal FDIV is sequentially processed by the two-phase non-overlapping clock generator to generate two-phase non-overlapping narrow pulse signals V1 and V2 working at the frequency-division frequency. The two-phase non-overlapping narrow pulse signals V1 and V2 pass through the boost function of the high-level boost inverter to obtain high-swing two-phase non-overlapping narrow pulse signals CK1 and CK2 (that is, the feedback clock Signal). Through negative feedback, the phase-locked loop works cyclically according to the above process until the phases of the output signal FOUT of the voltage-controlled oscillator and the input differential reference signals FREFP and FREFN are equal, and the phase-locking function of the phase-locked loop is completed.

进一步地，结合参见图3和图5，对本实施例的参考采样鉴相器以及高电平升压反相器的电路进行具体说明。Further, with reference to FIG. 3 and FIG. 5 , the circuits of the reference sampling phase detector and the high-level boost inverter in this embodiment are described in detail.

如图3所示的参考采样鉴相器的电路图，本实施例的参考采样鉴相器包括第一采样开关S₁、第二采样开关S₂、第一采样电容Cs和第二采样电容C_H。其中，第一采样开关S₁和第二采样开关S₂串联，第一采样开关S₁的第一端作为参考采样鉴相器的参考信号输入端，第二采样开关S₂的第二端作为参考采样鉴相器的输出端；第一采样电容Cs连接在第一采样开关S₁的第二端与接地端之间，第二采样电容C_H连接在第二采样开关S₂的第二端与接地端之间；第一采样开关S₁根据第一反馈时钟信号CK1实现开启或关断，第二采样开关S₂根据第二反馈时钟信号CK2实现开启或关断。The circuit diagram of the reference sampling phase detector shown in Figure 3, the reference sampling phase detector of this embodiment includes a first sampling switch S ₁ , a second sampling switch S ₂ , a first sampling capacitor Cs and a second sampling capacitor _CH . Wherein, the _first sampling switch S1 and the _second sampling switch S2 are connected in series, the first terminal of the _first sampling switch S1 is used as the reference signal input terminal of the reference sampling phase detector, and the second terminal of the _second sampling switch S2 is used as Reference to the output terminal of the sampling phase detector; the first sampling capacitor Cs is connected between the second terminal of the _first sampling switch S1 and the ground terminal, and the second sampling capacitor _CH is connected to the second terminal of the _second sampling switch S2 Between the terminal and the ground: the _first sampling switch S1 is turned on or off according to the first feedback clock signal CK1, and the second sampling switch S2 is turned on or off according to the _second feedback clock signal CK2.

本实施例的参考采样鉴相器的工作原理如下：The working principle of the reference sampling phase detector of the present embodiment is as follows:

工作于多模可编程分频器输出频率的第一反馈时钟信号CK1和第二反馈时钟信号CK2作为采样信号，FREF为输入参考信号(即就是，第一差分参考信号FREFP或第二差分参考信号FREFN)，第一采样开关S₁和第二采样开关S₂分别为主从两级采样的采样开关，第一采样电容Cs和第二采样电容C_H分别为主从两级采样的采样电容，采样输出信号VS和采样输出信号VH分别为主从两级采样的采样输出信号，(在本实施例中，采样输出信号VH即就是第一差分采样输出信号VSP或第二差分采样输出信号VSN)。反馈时钟信号CK1,CK2和参考信号FREF之间的相位差代表了参考采样锁相环的反馈信号和参考信号之间的相位差，通过跟踪保持采样器转换为电压信号，参考采样是指采样频率为参考频率。The first feedback clock signal CK1 and the second feedback clock signal CK2 working at the output frequency of the multimode programmable frequency divider are used as sampling signals, and FREF is an input reference signal (that is, the first differential reference signal FREFP or the second differential reference signal FREFN), the first sampling switch S ₁ and the second sampling switch S ₂ are respectively the sampling switches of master-slave two-stage sampling, the first sampling capacitor Cs and the second sampling capacitor _CH are respectively master-slave two-stage sampling sampling capacitors, The sampling output signal VS and the sampling output signal VH are the sampling output signals of master-slave two-stage sampling respectively, (in this embodiment, the sampling output signal VH is the first differential sampling output signal VSP or the second differential sampling output signal VSN) . The phase difference between the feedback clock signal CK1, CK2 and the reference signal FREF represents the phase difference between the feedback signal of the reference sampling phase-locked loop and the reference signal, which is converted into a voltage signal by the track-and-hold sampler, and the reference sampling refers to the sampling frequency as the reference frequency.

请参见图4所示的参考采样鉴相器的工作原理示意图，当第一反馈时钟信号CK1的上升沿过零点和参考信号FREF的上升沿对准，此时的相位差为0，第二反馈时钟信号CK2对主采样器的采样输出信号VS进一步采样，得到采样输出信号VH。此时，采样输出信号VH的电压值等于压控振荡器锁定后所需的控制电压VDC。Please refer to the schematic diagram of the working principle of the reference sampling phase detector shown in FIG. The clock signal CK2 further samples the sampling output signal VS of the main sampler to obtain the sampling output signal VH. At this time, the voltage value of the sampling output signal VH is equal to the required control voltage VDC after the voltage-controlled oscillator is locked.

当第一反馈时钟信号CK1和第二反馈时钟信号CK2滞后于参考信号FREF，此时的相位差不为0，得到的采样输出信号VH的电压值小于压控振荡器锁定后所需的控制电压VDC。When the first feedback clock signal CK1 and the second feedback clock signal CK2 lag behind the reference signal FREF, the phase difference at this time is not 0, and the voltage value of the sampled output signal VH obtained is less than the required control voltage after the voltage-controlled oscillator is locked. VDC.

当第一反馈时钟信号CK1和第二反馈时钟信号CK2领先于参考信号FREF，此时的相位差不为0，得到的采样输出信号VH的电压值大于压控振荡器锁定后所需的控制电压VDC。When the first feedback clock signal CK1 and the second feedback clock signal CK2 are ahead of the reference signal FREF, the phase difference at this time is not 0, and the voltage value of the sampled output signal VH obtained is greater than the required control voltage after the voltage-controlled oscillator is locked. VDC.

如图5所示的高电平升压反相器的电路图，本实施例的高电平升压反相器包括第一MOS管M1、第二MOS管M2、第三MOS管M3、第四MOS管M4、第五MOS管M5和第一电容C_HB。其中，第一MOS管M1的源极和第三MOS管M3的源极均连接电源端VDD；第一MOS管M1的栅极分别连接第二MOS管M2的栅极、第四MOS管M4的栅极和第五MOS管M5的栅极，漏极分别连接第二MOS管M2的漏极和第一电容C_HB的第一极板；第二MOS管M2的源极和第五MOS管M5的源极均连接接地端VSS；第三MOS管M3的漏极分别连接第一电容C_HB的第二极板和第四MOS管M4的源极，栅极分别连接第四MOS管M4的漏极和第五MOS管M5的漏极；第一MOS管M1的栅极作为高电平升压反相器的输入端，第三MOS管M3的栅极作为高电平升压反相器的输出端。The circuit diagram of the high-level boost inverter shown in Figure 5, the high-level boost inverter of this embodiment includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor MOS transistor M4, fifth MOS transistor M5 and first capacitor _CHB . Wherein, the source of the first MOS transistor M1 and the source of the third MOS transistor M3 are both connected to the power supply terminal VDD; the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2 and the gate of the fourth MOS transistor M4 respectively. The gate and the gate of the fifth MOS transistor M5, and the drain are respectively connected to the drain of the second MOS transistor M2 and the first plate of the first capacitor _CHB ; the source of the second MOS transistor M2 is connected to the fifth MOS transistor M5 The source of the third MOS transistor M3 is connected to the ground terminal VSS; the drain of the third MOS transistor M3 is respectively connected to the second plate of the first capacitor _CHB and the source of the fourth MOS transistor M4, and the gate is respectively connected to the drain of the fourth MOS transistor M4 pole and the drain of the fifth MOS transistor M5; the gate of the first MOS transistor M1 is used as the input terminal of the high-level boost inverter, and the gate of the third MOS transistor M3 is used as the input terminal of the high-level boost inverter output.

本实施例的高电平升压反相器的工作原理如下：The working principle of the high-level boost inverter in this embodiment is as follows:

有一个随第一电容C_HB增大而增大的参数h，其中0<h<1。高电平升压反相器在电源电压较低的情况下，将反馈时钟信号的高电平升压，显著降低了参考采样鉴相器中的采样开关S₁和S₂的导通电阻R_ON，使得采样开关和采样电容的时间常数τ＝R_ON*C_S远小于参考时钟周期TREF，从而实现正常的采样功能。相同的采样开关尺寸实现了更小的R_ON，允许使用更大的电容来减小采样电容带来的采样噪声，实现低压下更加优越的带内噪声性能。There is a parameter h that increases with the increase of the first capacitance _CHB , where 0<h<1. When the power supply voltage is low, the high-level boost inverter boosts the high level of the feedback clock signal, which significantly reduces the _on -resistance R _of the sampling switches S1 and S2 in the reference sampling phase detector _ON , so that the time constant τ=R _ON *C _S of the sampling switch and the sampling capacitor is much smaller than the reference clock period TREF, so as to realize the normal sampling function. The same size of the sampling switch achieves a smaller R _ON , allowing the use of larger capacitors to reduce the sampling noise caused by the sampling capacitor and achieve better in-band noise performance at low voltage.

如图6所示的高电平升压反相器的输入输出波形图，当高电平升压反相器的输入IN为电源电压VDD时，第一MOS管M1和第四MOS管M4关断，第二MOS管M2和第五MOS管M5导通，节点电压VA和输出OUT被放电至0，同时第三MOS管M3导通，节点电压VB被预充电到电源电压VDD。当高电平升压反相器的输入IN为从电源电压VDD翻转到低电平0时，第一MOS管M1和第四MOS管M4导通，第二MOS管M2和第五MOS管M5关断，节点电压VA被充电至电源电压VDD，节点电压VB通过第一电容C_HB的电压自举效果达到(1+h)*VDD的高电平电压，同时输出OUT被充电到(1+h)*VDD的高电平电压，从而实现了高电平升压反相器的高电平升压功能。The input and output waveform diagram of the high-level boost inverter shown in Figure 6, when the input IN of the high-level boost inverter is the power supply voltage VDD, the first MOS transistor M1 and the fourth MOS transistor M4 are turned off When the second MOS transistor M2 and the fifth MOS transistor M5 are turned on, the node voltage VA and the output OUT are discharged to 0, while the third MOS transistor M3 is turned on, and the node voltage VB is precharged to the power supply voltage VDD. When the input IN of the high-level boost inverter is flipped from the power supply voltage VDD to the low level 0, the first MOS transistor M1 and the fourth MOS transistor M4 are turned on, and the second MOS transistor M2 and the fifth MOS transistor M5 Turn off, the node voltage VA is charged to the power supply voltage VDD, the node voltage VB reaches the high-level voltage of (1+h)*VDD through the voltage bootstrap effect of the first capacitor _CHB , and the output OUT is charged to (1+h) h) The high-level voltage of *VDD, thus realizing the high-level boost function of the high-level boost inverter.

在本实施例中，利用高电平升压反相器减低采样开关的导通电阻，实现采样器在低压下的正常采样保持功能。具体原理如下：In this embodiment, the high-level boost inverter is used to reduce the on-resistance of the sampling switch, so as to realize the normal sampling and holding function of the sampler under low voltage. The specific principles are as follows:

采样开关的导通电阻R_ON＝1/{un*Cox*S*(VGS-VTH)}，其中un为电子迁移率，Cox为单位面积的栅氧化层电容，S为采样开关的宽长比，VGS为采样开关中MOS管的栅源电压也就是采样器的采样电压，VTH为采样开关中MOS管的阈值电压。高电平升压反相器通过对采样电压进行升压增大了公式中的VGS，从而减小了导通电阻R_ON。The on-resistance R _ON of the sampling switch =1/{un*Cox*S*(VGS-VTH)}, where un is the electron mobility, Cox is the gate oxide capacitance per unit area, and S is the width-to-length ratio of the sampling switch , VGS is the gate-source voltage of the MOS tube in the sampling switch, that is, the sampling voltage of the sampler, and VTH is the threshold voltage of the MOS tube in the sampling switch. The high-level boost inverter increases the VGS in the formula by boosting the sampling voltage, thereby reducing the on-resistance R _ON .

当采样开关导通后，输出电压从零上升到最大输入电平所需的时间为速度度量标准，可以用时间常数τ＝R_ON*CS来描述，CS为采样电容的大小。如果采样速度不够快，也就是时间常数τ没有远小于采样时间，就无法在采样时间中完整地对输入信号进行采样，会导致采样输出的失真。根据时间常数τ的公式可以看出，在不改变采样电容CS时，减小导通电阻R_ON可以增加采样速度，实现正常的采样功能。在参考采样锁相环中，采样时间通常为参考周期或采样信号的高电平脉宽。When the sampling switch is turned on, the time required for the output voltage to rise from zero to the maximum input level is the speed metric, which can be described by the time constant τ=R _ON *CS, where CS is the size of the sampling capacitor. If the sampling speed is not fast enough, that is, the time constant τ is not much smaller than the sampling time, the input signal cannot be completely sampled within the sampling time, which will lead to distortion of the sampling output. According to the formula of the time constant τ, it can be seen that when the sampling capacitor CS is not changed, reducing the on-resistance R _ON can increase the sampling speed and realize the normal sampling function. In a reference sampling PLL, the sampling time is usually the reference period or the high-level pulse width of the sampling signal.

采样开关的导通电阻R_ON引入了电阻热噪声K*T/CS，其中K为玻尔兹曼常数，T为温度，CS为采样电容的大小。为了降低噪声，采样电容必须足够大，但是会造成时间常数τ＝R_ON*CS的增大而降低采样速度。而减小电阻R_ON可以在不增大时间常数τ的前提下，增大采样电容来降低噪声。The on-resistance R _ON of the sampling switch introduces resistive thermal noise K*T/CS, where K is the Boltzmann constant, T is the temperature, and CS is the size of the sampling capacitor. In order to reduce the noise, the sampling capacitance must be large enough, but it will cause the increase of the time constant τ=R _ON *CS and reduce the sampling speed. And reducing the resistance R _ON can reduce the noise by increasing the sampling capacitance without increasing the time constant τ.

在具体实施例中，利用0.18μm CMOS工艺制作出工作频率为3.8GHz-4.7GHz，工作电压1V-1.8V,时钟抖动为109fs，参考杂散为-82dBc的参考采样锁相环，实现低压低杂散低抖动的优越性能。In a specific embodiment, a reference sampling phase-locked loop with an operating frequency of 3.8GHz-4.7GHz, an operating voltage of 1V-1.8V, a clock jitter of 109fs, and a reference spur of -82dBc is fabricated using a 0.18μm CMOS process to achieve low voltage and low Superior performance with low spurious jitter.

应当说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的物品或者设备中还存在另外的相同要素。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。It should be noted that in this article, relational terms such as first and second etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the terms "comprises", "comprises" or any other variation are intended to cover a non-exclusive inclusion such that an article or device comprising a set of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the article or device comprising said element. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.