CN115765957B - Clock phase synchronization adjustment method and system based on LVDS source - Google Patents

The invention provides a clock phase synchronization adjustment method based on LVDS source, which detects a synchronization code under the phase relation of the current clock and LVDS data, and then carries out the following steps: at the current initial adjustment position, clock phase shifting is carried out to the negative phase, and x clock phases tap are accumulated and shifted until the synchronization code is lost; returning to the current initial adjustment position, performing clock phase movement to the positive phase, and accumulating and moving y clock phases tap until the synchronization code is lost; finally, the current optimal phase position is obtained according to the calculation of the clock phase tap of the two shiftsThe clock phase is loaded to the current optimal phase position Tap _{Optimum for the production of a product} .

Clock phase synchronization adjustment method and system based on LVDS source

Technical Field

The invention relates to the technical field of CT detector data reception, in particular to a clock phase synchronization adjustment method and system based on an LVDS source.

Background

LVDS (Low-VoltageDifferentialSignaling) Low-voltage differential signal is a differential signal technology with Low power consumption, low bit error rate, low crosstalk and Low radiation, the transmission technology can reach more than 155Mbps, the core of the LVDS technology is to adopt extremely Low voltage swing high-speed differential transmission data, point-to-point or point-to-multipoint connection can be realized, and the transmission medium can be a copper PCB (printed circuit board) wire or a balanced cable, so that LVDS has become one of the most widely used interfaces for inter-chip communication, such as being used for transmitting video data in our chips as display output.

At present, an ADC chip used in a CT detector mostly adopts synchronous LVDS to perform high-speed data transmission, and when the data is not aligned with the clock phase, the received data will make errors, so that an image generates an artifact.

The prior art utilizes bitslip functions of LVDS data in an FPGA to adjust data bit, so that although the data can be aligned, error data can be easily acquired when signals are dithered, namely the phase and the data phase do not reach an optimal phase interval.

Disclosure of Invention

In order to overcome the technical defects, the invention aims to provide a clock phase synchronization adjustment method and a clock phase synchronization adjustment system based on an LVDS source, which dynamically adjust clock phases to realize the most stable clock and data phases.

The invention discloses a clock phase synchronization adjustment method based on LVDS source, which comprises the following steps of: at the current initial adjustment position, clock phase shifting is carried out to the negative phase, and x clock phases tap are accumulated and shifted until the synchronization code is lost; returning to the current initial adjustment position, performing clock phase movement to the positive phase, and accumulating and moving y clock phases tap until the synchronization code is lost; obtaining the current optimal phase position according to the clock phase tap calculation of the two shiftsThe clock phase is loaded to the current optimal phase position Tap _{Optimum for the production of a product} .

Preferably, the detecting the synchronization code in the phase relation between the current clock and the LVDS data includes: when no synchronization code is detected in the phase relationship of the current clock and the LVDS data, then a bitslip process is performed to detect the synchronization code.

Preferably, if the synchronization code is not detected in the phase relationship between the current clock and the LVDS data, then performing bitslip to detect the synchronization code includes adjusting a clock phase tap if the synchronization code is also detected in bitslip, and then continuing to repeat the above detection process until the synchronization code is found.

Preferably, the detecting the synchronization code in the phase relation between the current clock and the LVDS data includes: detecting a synchronous code under the phase relation of the current clock and LVDS data in real time by taking a preset time as an interval; the time interval is 1min-5min.

Preferably, in the current initial adjustment position, clock phase shift is performed to the negative phase, and x clock phases tap are accumulated and shifted until the synchronization code is lost; returning to the current initial adjustment position, performing clock phase shift to the positive phase, and accumulating shift of y clock phases tap until the synchronization code is lost, wherein the step of accumulating shift comprises the steps of: the x clock phases tap of each negative shift and the y clock phases tap of positive shift and the shift time are recorded.

The invention also discloses a clock phase synchronization adjustment system based on the LVDS source, which is characterized by comprising a data acquisition module, an FPGA module and a clock synchronization module; the data acquisition module acquires clock and LVDS data and sends the clock and LVDS data to the FPGA module, and when the FPGA module detects a synchronous code under the phase relation of the current clock and the LVDS data, the following steps are carried out: the clock synchronization module is controlled at the current initial adjustment position, performs clock phase movement to the negative phase, and cumulatively moves x clock phases tap until the synchronization code is lost; the clock synchronization module is controlled to return to the current initial adjustment position, clock phase movement is carried out to the positive phase, and y clock phases tap are accumulated and moved until the synchronization code is lost; the FPGA module calculates and obtains the current optimal phase position according to the clock phase tap of the two movementsAnd sent to the clock synchronization module to load the clock phase to the current optimal phase position Tap _{Optimum for the production of a product} .

The invention also discloses a computer readable storage medium, on which a computer program is stored, which when being executed by a processor implements the steps of the clock phase synchronization adjustment method.

After the technical scheme is adopted, compared with the prior art, the method has the following beneficial effects:

1. In the synchronous calibration process of data, the clock phase is dynamically moved to find the phase range of clock and data offset, and then the phase in the middle range is selected, so that the stability is optimal when the phase fluctuates positively and negatively, and the stability of the acquired data is ensured.

Drawings

FIG. 1 is a flow chart of a method for adjusting clock phase synchronization according to the present invention;

Fig. 2 is a phase shift schematic diagram of a clock phase synchronization adjustment method according to the present invention.

Detailed Description

Advantages of the invention are further illustrated in the following description, taken in conjunction with the accompanying drawings and detailed description.

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present disclosure. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" depending on the context.

In the description of the present invention, it should be understood that the terms "longitudinal," "transverse," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.

In the description of the present invention, unless otherwise specified and defined, it should be noted that the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, mechanical or electrical, or may be in communication with each other between two elements, directly or indirectly through intermediaries, as would be understood by those skilled in the art, in view of the specific meaning of the terms described above.

In the following description, suffixes such as "module", "component", or "unit" for representing elements are used only for facilitating the description of the present invention, and are not of specific significance per se. Thus, "module" and "component" may be used in combination.

Referring to fig. 1-2, when receiving LVDS clock and data, the invention detects the phase relation between the synchronous code and the clock in real time, firstly adopts the dynamic movement of the clock phase to find the phase range of the clock and the data, then selects the phase of the middle range, and automatically adjusts the new clock phase after detecting the error of the synchronous code, so that the data are synchronized again. Therefore, when the phase is subjected to positive and negative fluctuation, the stability is optimal, so that the stability of the acquired data is ensured.

The invention discloses a clock phase synchronization adjustment system based on an LVDS source, which comprises a data acquisition module, an FPGA module and a clock synchronization module.

The data acquisition module acquires clock and LVDS data and sends the clock and LVDS data to the FPGA module, and when the FPGA module detects a synchronous code under the phase relation of the current clock and the LVDS data, the following steps are carried out: the clock synchronization module is controlled at the current initial adjustment position, clock phase movement is carried out to the negative phase, and x clock phases tap are accumulated and moved until the synchronization code is lost; the clock synchronization module is controlled to return to the current initial adjustment position, clock phase movement is carried out to the positive phase, and y clock phases tap are accumulated and moved until the synchronization code is lost; the FPGA module calculates and obtains the current optimal phase position according to the clock phase tap of the two movementsAnd sent to the clock synchronization module to load the clock phase to the current optimal phase position Tap _{Optimum for the production of a product} .

Based on the clock phase synchronization adjustment system, the invention discloses a clock phase synchronization adjustment method based on an LVDS source, and when a synchronous code is detected under the phase relation of a current clock and LVDS data, the following adjustment steps are carried out: at the current initial adjustment position, clock phase shifting is carried out to the negative phase, and x clock phases tap are accumulated and shifted until the synchronization code is lost; returning to the current initial adjustment position, performing clock phase movement to the positive phase, and accumulating and moving y clock phases tap until the synchronization code is lost; obtaining the current optimal phase position according to the clock phase tap calculation of the two shiftsThe clock phase is loaded to the current optimal phase position Tap _{Optimum for the production of a product} .

It should be noted that, the displacement toward the negative direction and then toward the positive direction is only a preferred manner, and in the actual process, the displacement toward the positive direction and then toward the negative direction may be performed to obtain the optimal phase position.

Preferably, if the synchronization code is not detected in the phase relationship between the current clock and the LVDS data, then bitslip processes are performed to detect the synchronization code.

Further, if the synchronization code is detected in the process bitslip, after adjusting a clock phase tap, the above detection process is continuously repeated until the synchronization code is found.

Preferably, the synchronization code under the phase relation of the current clock and the LVDS data is detected in real time by taking the preset time as an interval; the time interval is 1min-5min, and the clock phase is adjusted in real time.

Preferably, the data report can be formed by recording x clock phases tap of each negative displacement, y clock phases tap of positive displacement and displacement time, and the data report can be analyzed later when needed.

See fig. 1 for a preferred embodiment:

1. firstly, the FPGA module internally receives clock and data LVDS signals from a detector;

The FPGA module detects whether the synchronous code can be detected under the phase relation of the current clock and the data;

3. if the synchronous code is not detected, carrying out bitslip functions, and polling for a week to confirm whether the synchronous code exists;

4. If the synchronous code is not detected in one circle of polling, adjusting a clock phase tap, and then repeating the process of the step 2-3 until the synchronous code is found; if the step 3 detects the synchronous code, the following clock phase optimal adjustment is carried out;

5. detecting a synchronous code under the current phase, and closing bitslip functions;

6. Firstly, clock phase shifting is carried out to the negative phase, one tap is accumulated once for each shift until the synchronous code is lost, and the calculation of the negative phase is finished, and the shift is carried out for x times;

7. Loading the phase to the initial position (position not shifted to the negative phase) in the step 5 again, shifting the clock phase according to the positive phase, accumulating one tap every time, and shifting y times until the synchronization code is lost;

8. the phase domain degree of the clock and the data is calculated through the steps 6 and 7, and then the middle position of the positive phase and the negative phase is the phase position with the optimal stability;

9. Reloading the clock phase to Tap _{Optimum for the production of a product} ;

And 10, continuously detecting the synchronous code under the phase relation of the current clock and the data in real time by the FPGA module.

Likewise, the displacement in the negative direction and then the displacement in the positive direction are only one preferred mode, and in the actual process, the displacement in the positive direction and then the displacement in the negative direction can be performed first so as to obtain the optimal phase position.

The invention also discloses a computer readable storage medium, on which a computer program is stored, which computer program when executed by a processor implements the steps of the method for adjusting clock phase synchronization.

It should be noted that the embodiments of the present invention are preferred and not limited in any way, and any person skilled in the art may make use of the above-disclosed technical content to change or modify the same into equivalent effective embodiments without departing from the technical scope of the present invention, and any modification or equivalent change and modification of the above-described embodiments according to the technical substance of the present invention still falls within the scope of the technical scope of the present invention.