CN115912880A - Current-limiting protection circuit, boost converter, current-limiting protection chip and electronic equipment - Google Patents

The application relates to the technical field of electronics and discloses a current-limiting protection circuit, a boost converter, a current-limiting protection chip and electronic equipment. The boost converter comprises a first switch device, a second switch device and a first inductor, when the current limiting protection circuit detects that the current of the first inductor is larger than the preset current at the first moment, the current limiting protection circuit keeps the first switch device off and the second switch device on before the next rising edge of a frequency division signal of a clock signal of the boost converter at the first moment, so that the first inductor discharges. Therefore, the period of discharging of the first inductor in the boost converter can be longer than one clock period, the discharging duration of the first inductor is increased, the current in the first inductor can be effectively reduced, and the failure of the boost converter caused by the continuous increase of the current in the first inductor is avoided.

Current-limiting protection circuit, boost converter, current-limiting protection chip and electronic equipment

Technical Field

The present disclosure relates to electronic technologies, and in particular, to a current-limiting protection circuit, a boost converter, a current-limiting protection chip, and an electronic device.

Background

A boost converter is a circuit which boosts input voltage based on an energy storage device and outputs the boosted input voltage with higher output voltage, and is widely applied to circuits with power supply voltage lower than that required by electric devices. Typically, a boost converter includes at least one switching device (e.g., a semiconductor diode, a transistor, etc.) and at least one energy storage device (e.g., an inductor, etc.). Each conversion cycle of the boost converter may be divided into an energy storage phase, in which the energy storage device is charged by the input voltage and supplied by the energy storage device to the load, and a freewheeling phase, in which the energy storage device is discharged and supplied to the load. Furthermore, the speed of charging of the energy storage device in the boost converter increases with increasing input voltage, and the speed of discharging decreases with decreasing difference between the output voltage and the input voltage.

When the output voltage and the input voltage of the boost converter are relatively close, the current in the energy storage device gradually increases along with the increase of the continuous working time of the boost converter. Thus, when the current in the energy storage device exceeds the saturation current of the energy storage device, the energy storage device may fail, and the boost converter may fail.

Disclosure of Invention

In view of this, the present application provides a current-limiting protection circuit, a boost converter, a current-limiting protection chip and an electronic device. The current-limiting protection circuit can control the time of inductor discharging to exceed the period of the clock signal of the boost converter when the current of the inductor in the boost converter is larger than the preset current, so that the current in the inductor is reduced, and the failure of the boost converter caused by the continuous increase of the current in the inductor is avoided.

In a first aspect, an embodiment of the present application provides a current-limiting protection circuit, which is applied to a boost converter, where the boost converter includes a first switching device, a second switching device, and a first inductor, and the current-limiting protection circuit includes: the current detection circuit is used for generating a current limiting signal, and the current limiting signal is effective when the inductive current of the first inductor is larger than the preset current; the driving circuit is used for forming a first boosting path from a first moment when the current limiting signal is converted from invalid to valid to the next period of the first signal; the first boost path is a boost path formed by the boost converter when the first switch device is turned off, the second switch device is turned on and the first inductor discharges; the first signal is a frequency-divided signal of a clock signal of the boost converter.

When the inductive current of the first inductor is larger than the preset current, the current-limiting protection circuit can enable the first inductor to be in a discharging state from the first moment when the current-limiting signal is converted from invalid to effective to the next period of the first signal. The first signal is a frequency division signal of a clock signal of the boost converter, so that the period of the first signal is greater than that of the clock signal, the discharge time of the first inductor can be greater than one clock period, the discharge time of the first inductor is increased, the reduction amount of the inductor current of the first inductor can be increased, and the failure of the boost converter caused by the continuous increase of the current in the inductor is avoided.

For example, in some implementations, the first switching device may be the following switching transistor Q1, the second switching device may be the following freewheeling transistor Q2, the first inductor may be the following inductor L, the clock signal may be the following CLK signal, the first signal may be the following divided signal CLK _ HF, the current detection circuit may be the following current detection circuit Ti1, and the driving circuit may be the following driving circuit Dr2.

In a possible implementation of the first aspect, the current limiting protection circuit further includes a current limiting control circuit, the current limiting control circuit is configured to generate a switching signal, and the driving circuit forms a first boost path before a next cycle of the first signal comes from a first time when the current limiting signal is converted from invalid to valid based on the switching signal and the current limiting signal;

wherein: in each period of converting the current limiting signal from invalid to an effective clock signal in the current period of the first signal, the switching signal is invalid before a preset time and effective after the preset time; in the case that the current limiting signal is changed from inactive to active at the first time in the current period of the first signal, the switching signal remains inactive until the next period of the first signal from the start of the next clock signal after the first time.

For example, in some implementations, the switching signal may be switching signal S hereinafter _C The predetermined time may be the following inductive current I _L Corresponding switching voltage (V) _ISENSE ) With a predetermined signal (V) _SLOPE ) At the moment the sum (V _ Ref 2) drops to the reference voltage CP1_ OUT, the current limit control circuit may be the current limit control circuit 10 hereinafter.

In a possible implementation of the first aspect, the driving circuit forms the first boost path before a next cycle of the first signal comes from a first time when the current limit signal is converted from inactive to active based on the switching signal and the current limit signal by:

in the current period of the first signal, under the condition that the current limiting signal is converted from invalid to valid at the first moment, the driving circuit outputs a signal for enabling the first switching device to be cut off to the first switching device and outputs a signal for enabling the second switching device to be switched on to the second switching device before the first moment to the nth clock signal period where the first moment is located and before the nth clock signal period is ended and before the switching signal is converted from invalid to valid.

In the implementation mode, when a certain clock signal period detects that a current-limiting signal is converted from invalid to valid, the driving circuit is not controlled by a switching signal but directly outputs a signal for enabling the first switching device to be cut off to the first switching device and outputs a signal for enabling the second switching device to be switched on to the second switching device in the residual time of the clock signal period; after the clock signal period is over, the driving circuit is controlled by the switch signal continuously, and when the switch signal is effective, the signal for turning off the first switch device is output to the first switch device, and the signal for turning on the second switch device is output to the second switch device.

For example, in some implementations, the signal for turning off the first switching device and the signal for turning on the second switching device may be the DUTY signal DUTY hereinafter.

In one possible implementation of the first aspect, the driving circuit is further configured to: in the current period of the first signal, before the current limiting signal is detected to be converted from invalid to valid, when the switching signal is valid, a second boosting path is formed, and when the switching signal is invalid, a first boosting path is formed; the second boost path is a boost path formed by the boost converter when the first switch device is turned on, the second switch device is turned off and the first inductor is charged.

In this implementation, in the current cycle of the first signal, before it is detected that the current limiting signal is changed from inactive to active, the driving circuit is controlled by the switching signal, and when the switching signal is active, the second boost path is formed, and when the switching signal is inactive, the first boost path is formed.

In one possible implementation of the first aspect, the first switching device is an N-channel MOSFET, the second switching device is a P-channel MOSFET, and the driving circuit forms the first boost path by inputting a low-level signal to gates of the first switching device and the second switching device, and forms the second boost path by inputting a high-level signal to gates of the first switching device and the second switching device.

In one possible implementation of the first aspect, the current limit control circuit includes: the circuit comprises a first resistor, a second resistor, an AND gate, a first capacitor, a first comparator, a second comparator, a controlled switch and a trigger;

wherein: the first resistor is electrically connected to the drain electrode of the second switching device, the other end of the first resistor is electrically connected to one end of the second resistor and the positive phase input end of the first comparator, and the other end of the second resistor is grounded; the negative phase input end of the first comparator is used for receiving a first reference voltage, and the output end of the first comparator is electrically connected with the negative phase input end of the second comparator, one end of the controlled switch and one end of the first capacitor; the other end of the controlled switch and the other end of the first capacitor are grounded, the controlled switch is closed when a first control signal is valid and is opened when the first control signal is invalid, wherein the first control signal is invalid when the current limiting signal is invalid, is valid when the current limiting signal is converted from invalid to valid, and is recovered to be invalid on the next rising edge of the first signal; the positive phase input end of the second comparator is used for receiving a second reference voltage, and the output end of the second comparator is electrically connected with one input end of the AND gate; the other input end of the AND gate is used for receiving a clock signal, and the output end of the AND gate is electrically connected with a clock interface of the trigger; the input end of the trigger is used for receiving an effective signal, the reset end is used for receiving a clock signal, and the positive output end is used for outputting a switch signal to the driving circuit, wherein the reset end is effective in a rising edge, and the clock interface is effective in a falling edge.

For example, in some implementations, the first resistor may be a resistor R1, the first resistor may be a resistor R2, the AND gate may be an AND gate AND1, the first comparator may be a comparator CP1, the second comparator may be a comparator CP2, the controlled switch may be a controlled switch CK1, the trigger may be a trigger TR1, the first reference voltage may be a preset reference voltage V _ Ref1, AND the second reference voltage may be a preset reference voltage V _ Ref1, respectively _ISENSE With a predetermined signal V _SLOPE V _ Ref2, the first control signal may be P _ EA hereinafter.

In a possible implementation of the first aspect, the preset time is a time when the second reference voltage is smaller than the output signal of the first comparator in each cycle of the clock signal.

In one possible implementation of the first aspect, the current-limiting protection circuit further includes a control signal generation circuit, configured to generate the first control signal based on the first signal and a sampled voltage at the other end of the first inductor.

In one possible implementation of the first aspect, the control signal generating circuit includes: the first NOT gate, the second NOT gate, the NAND gate, the third comparator, the first N-channel MOSFET and the second N-channel MOSFET; wherein: the input end of the first NOT gate is used for receiving a first signal, and the output end of the first NOT gate is electrically connected to one input end of the NAND gate and the grid of the second N-channel MOSFET; the other input end of the NAND gate is electrically connected to the output end of the second NOT gate, and the output end of the NAND gate is electrically connected to the input end of the second NOT gate and the drain electrode of the second N-channel MOSFET; the output end of the second NOT gate is used for outputting a first control signal; a positive phase input end of the third comparator is used for receiving the sampling voltage, a negative phase input end of the third comparator is used for receiving a third reference voltage, and an output end of the third comparator is electrically connected to the grid electrode of the first N-channel MOSFET; the source electrode of the first N-channel MOSFET is electrically connected with the drain electrode of the second N-channel MOSFET; the source of the second N-channel MOSFET is grounded.

For example, in some implementations, the first NOT gate may be a NOT gate NOT1 hereinafter, the second NOT gate may be a NOT gate NOT2 hereinafter, the third comparator may be a comparator CP3 hereinafter, the first N-channel MOSFET may be an N-channel MOSFET Q3 hereinafter, the second N-channel MOSFET may be an N-channel MOSFET Q4 hereinafter, the sampling voltage may be a sampling voltage V _ SW hereinafter, and the third reference voltage may be a reference voltage V _ SW _ Ref hereinafter.

In one possible implementation of the first aspect, the first signal is a divided-by-two signal or a divided-by-three signal of the clock signal.

In a second aspect, embodiments of the present application provide a boost converter including a first switching device, a second switching device, a first inductor, and a current limiting protection circuit provided by the first aspect and various possible implementations of the first aspect.

In a third aspect, an embodiment of the present application provides a current-limiting protection chip, where the current-limiting protection chip includes the current-limiting protection circuit provided in the first aspect and various possible implementations of the first aspect.

In a fourth aspect, an embodiment of the present application provides an electronic device, which includes a first switching device, a second switching device, a first inductor, and a current limiting protection circuit provided in the first aspect and various possible implementations of the first aspect.

Drawings

FIG. 1A illustrates a schematic diagram of an application scenario of a boost converter, according to some embodiments of the present application;

FIG. 1B illustrates a schematic diagram of another boost converter application scenario, according to some embodiments of the present application;

Detailed Description

Illustrative embodiments of the present application include, but are not limited to, current limiting protection circuits, boost converters, current limiting protection chips, and electronics.

For ease of understanding, terms referred to in the embodiments of the present application will be first introduced.

(1) Boost converter

A boost converter, also called a DC boost converter, a DC boost chopper, or the like, is a DC-DC (direct current-direct current) converter for boosting a voltage, and an output (load) voltage thereof is higher than an input voltage. The boost converter includes at least one switching device (e.g., semiconductor diode, transistor, etc.) and at least one energy storage device (e.g., inductor, etc.). Each conversion cycle of the boost converter may be divided into an energy storage phase, in which the energy storage device is charged by the input voltage and supplied by the energy storage device to the load, and a freewheeling phase, in which the energy storage device is discharged and supplied to the load. Furthermore, the speed of charging of the energy storage device in the boost converter increases with increasing input voltage, and the speed of discharging decreases with decreasing difference between the output voltage and the input voltage.

Boost converters are widely used in power supply equipment (e.g., chargers, dc power supplies) and electronic equipment having an input voltage lower than that required by power-consuming circuits. For example, referring to fig. 1A, the voltage input to the electronic device 01 is V1, and the voltage required by the circuit 012 in the electronic device 01 is V2, V2> V1. In this case, the electronic device 01 may be provided with a boost converter 011 for converting the input voltage V1 into V2 and outputting the converted voltage to the power consumption circuit 012. For another example, referring to fig. 1B, the power supply device 01 may be configured to receive an input voltage V1, convert the voltage V1 into a voltage V2 (V2 > V1), and output the voltage V2 to other electronic devices for use.

The technical solution of the embodiment of the present application is described below with reference to the accompanying drawings.

Wherein, one end of the inductor L is used for receiving an input voltage V _in The other end of the switch tube Q1 is electrically connected with the drain electrode of the switch tube Q1 and the source electrode of the follow current tube Q2; the grid electrode of the switching tube Q1 is electrically connected with the driving circuit Dr1 and is used for receiving a switching tube control signal V sent by the driving circuit Dr1 _GN The source electrode of the switching tube Q1 is grounded; the gate of the follow current tube Q2 is electrically connected to the driving circuit Dr1, and is used for receiving a follow current tube control signal V sent by the driving circuit Dr1 _GP The drain of the follow current tube Q2 is electrically connected to one end of the capacitor C1 for outputting an output voltage V _out And electrically connected to a load; the other end of the capacitor C1 is grounded; the driving circuit Dr1 is used for receiving a clock signal (hereinafter referred to as CLK signal) and outputting different switch tube control signals V according to whether the clock signal CLK is effective or not _GN And follow current tube control signal V _GP 。

It will be appreciated that in some embodiments, the CLK signal may be a square wave.

It will be appreciated that in some embodiments, the CLK signal may be generated by an Oscillator (OSC).

Specifically, in some embodiments, the inductor L is charged with a current I _L Change slope S of _{Charging of electricity} Can be based onThe following equation (1).

S _{Charging method and apparatus} ＝V _in /L ₀ (1)

In the formula (1), L ₀ The inductance value of the inductor L.

While the current I is flowing when the inductor L is discharging _L Change slope S of _{Discharging electricity} May be determined based on the following formula (2).

S _{Discharge of electricity} ＝(V _out -V _in )/ L ₀ (2)

Optionally, in some embodiments, k =2 or k =3, i.e. the divided signal CLK _ HF is a divided-by-two signal or a divided-by-three signal of the CLK signal.

The current detection circuit Ti is used for detecting the inductive current I _L Generating a current limiting signal P, wherein the current limiting signal P is at the inductor current I _L Greater than a predetermined current I _M It is effective. For example, the current detection circuit Ti1 may detect the current flowing through the source of the switching tube Q1 (i.e. the current I of the inductor L) _L ) And in the inductor current I _L Greater than a predetermined current I _M At this time, an active current limit signal (e.g., high level) is output to the driving circuit Dr2.

The current limit control circuit 10 is used for generating a switching signal S according to the CLK signal and the current limit signal P _c 。

The switching signal Sc is asserted after a predetermined time of each period of the CLK signal when the current limit signal P is not asserted. In addition, when the current limit signal P is detected to be active in the nth CLK signal period, the switching signal Sc remains inactive from the (n + 1) th CLK signal period until the rising edge of the next divided signal CLK _ HF arrives.

In some embodiments, the predetermined time may be the inductor current I _L Corresponding switching voltage (V) _ISENSE ) And a predetermined signal (V) _SLOPE ) To the time when the sum (V _ Ref 2) of (a) falls to the reference voltage CP1_ OUT.

The driving circuit Dr2 is used for receiving the switching signal S sent by the current limiting control circuit 10 _c And a current limit signal P, and based on the switching signal S _c And the current limiting signal P is used for controlling the on and off of the switching tube Q1 and the follow current tube Q2. For example, the inductor current I is detected at time t _L Greater than a predetermined current I _M In the meantime, the switching tube Q1 is kept off and the follow current tube Q2 is kept on until the next rising edge of the frequency division signal CLK _ HF comes from time t, and the inductor L continues to discharge.

In some embodiments, the switch tube control signal V _GN And follow current tube control signal V _GP The signals may be the same signal (hereinafter referred to as DUTY cycle signal DUTY), and when the DUTY cycle signal DUTY is active (for example, when the DUTY cycle signal DUTY is at a high level), the switching tube Q1 is turned on, and the freewheeling tube Q2 is turned off; when the DUTY signal DUTY is inactive (for example, at a low level), the switching tube Q1 is turned off and the freewheeling tube Q2 is turned on.

As shown in fig. 5, the current limit control circuit 10 includes a flip-flop TR1, a comparator CP2, an AND gate AND1, a resistor R2, a capacitor C2, AND a controlled switch CK1.

The other end of the resistor R2 is grounded.

The other end of the controlled switch CK1 and the other end of the capacitor C2 are grounded, and the controlled switch CK1 is controlled by a control signal P _ EA. In the control signal P _ EA, the controlled switch CK1 is turned on, so that the signal input to the comparator CP2 (i.e., the output signal CP1_ OUT of the comparator CP 1) is inactive and the output of the comparator CP2 is always active.

The control signal P _ EA is obtained based on a divided signal CLK _ HF (hereinafter, referred to as a divided signal CLK _ HF) of the CLK signal and a voltage V _ SW at one end of the drain of the switching tube Q1 (or the source of the follow current tube Q2) to which the inductor L is electrically connected. When V _ SW is greater than the reference voltage V _ SW _ Ref (i.e. the inductor current I) _L Greater than a predetermined current I _M Time), the control signal P _ EA is asserted and continuesBy the next rising edge of the CLK HF signal, it becomes inactive. For a specific implementation, reference may be made to the embodiment shown in fig. 6, which is not described herein again.

The positive input terminal of the comparator CP2 is used for receiving the inductive current I _L Corresponding switching voltage V _ISENSE With a predetermined signal V _SLOPE AND V _ Ref2, the output terminal is electrically connected to one input terminal of the AND gate AND 1. When V _ Ref2 is greater than CP1_ OUT (the aforementioned preset time), the comparator CP2 outputs an active signal (e.g., high level); and outputs an invalid signal (e.g., low level) when V _ Ref2 is smaller than CP1_ OUT (the aforementioned preset time).

It can be understood that the inductor current I _L Corresponding switching voltage V _ISENSE And the inductive current I _L In a positive correlation, the inductor current I _L The larger, V _ISENSE The larger; presetting signal V _SLOPE For sawtooth wave signals, preset signal V _SLOPE Is the same as the CLK signal, and in each period, the signal V is preset _SLOPE The current-continuing tube Q2 rises from the conduction time with a preset initial value and a preset slope, and falls to the preset initial value when the current-continuing tube Q2 is cut off.

The flip-flop TR1 has an input terminal D for receiving an active signal (e.g., a logic signal "1", an analog signal greater than a predetermined voltage, etc.), a RESET terminal RESET for receiving a CLK signal, and a positive output terminal Q for outputting a switching signal S to the driving circuit Dr2 _C 。

When the RESET terminal RESET of the flip-flop TR1 detects a rising edge of the CLK signal, the signal at the positive output terminal Q is set to be RESET (e.g., set to a low level or a logic signal 0). The driving circuit Dr2 detects the switching signal S _C When the current is invalid, an invalid DUTY ratio signal DUTY is output to the grids of the switching tube Q1 and the follow current tube Q2, so that the switching tube Q1 is cut off, the follow current tube Q2 is conducted, and the inductive current I of the inductor L is _L And (4) descending.

Inductor current I in inductor L during the period when CLK signal is active _L When the voltage V _ Ref2 at the non-inverting input terminal of the comparator CP2 drops to a level such that it becomes smaller than the signal CP1_ OUT output at the output terminal of the comparator CP1, the signal CP2_ OUT output at the output terminal of the comparator CP2 changes from high level to low level, AND the output of the AND gate AND1 changes from high level to low level. The flip-flop TR1 sets (e.g. to high or logic signal 1) the signal output from the positive output Q when it detects that the signal of the CLOCK interface CLOCK transitions from high to low (i.e. when a falling edge is detected), i.e. outputs an active switching signal S to the driver circuit Dr2 _C . The driving circuit Dr2 detects the switching signal S _C When the current is effective, an effective DUTY ratio signal DUTY is output to the grids of the switching tube Q1 and the follow current tube Q2, so that the switching tube Q1 is switched on, the follow current tube Q2 is switched off, and the inductive current I of the inductor L is _L And (4) rising.

If at time t of the nth CLK signal period the current detection circuit Ti1 detects the inductor current I _L Greater than a predetermined current I _M The active current limit signal P is sent to the driver circuit Dr2. Furthermore, the driving circuit Dr2 outputs an invalid DUTY ratio signal DUTY to the gates of the switching tube Q1 and the follow current tube Q2 from the time t to the end of the nth CLK signal period, so that the switching tube Q1 is turned off, the follow current tube Q2 is turned on, and the inductor current I of the inductor L is _L And (4) descending.

Accordingly, at time t, the control signal P _ EA transitions from inactive to active and continues until the next rising edge of the divided signal CLK _ HF. Therefore, during the period that P _ EA is active, the controlled switch CK1 is closed, so that the signal at the negative phase input end of the comparator CP2 is pulled low, the signal output by the comparator CP2 to the input end of the AND gate AND1 is always active, AND further the signal at the CLOCK interface CLOCK of the flip-flop TR1 is always active.

In each CLK signal cycle from the (n + 1) th CLK signal cycle until the next rising edge of the divided signal CLK _ HF arrives, the flip-flop TR1 RESETs the signal at the positive output terminal Q when the RESET terminal RESET detects the rising edge of the CLK signal. Since the signal of the CLOCK interface CLOCK of the flip-flop TR1 is always valid, the flip-flop TR1 does not change the signal of the positive output terminal Q, and the flip-flop TR1 outputs the switching signal S to the driving circuit Dr2 _C Remain invalid. The driving circuit Dr2 outputs an invalid DUTY ratio signal DUTY to the gates of the switching tube Q1 and the follow current tube Q2, so that the switching tube Q1 is turned off, the follow current tube Q2 is turned on, and the inductive current I of the inductor L is _L And (4) descending.

That is, the inductor current I of the inductor L is within the time from the time t of the nth CLK signal period until the next rising edge of the divided signal CLK _ HF arrives _L The current is decreased, the discharge time of the inductor L is increased, and the current I of the inductor can be effectively avoided _L The continuous rise causes the inductor L to fail.

For the sake of understanding, a specific circuit for generating the aforementioned control signal P _ EA is described below, and the circuit can generate the aforementioned control signal P _ EA based on the divided signal CLK _ HF of the CLK signal and the reference voltage V _ SW _ Ref of the inductor L connected to one end of the switching tube Q1.

The input end of the NOT gate NOT1 is used for receiving a frequency division signal CLK _ HF of a CLK signal, and the output end of the NOT gate NOT1 is electrically connected with one input end of the NAND gate NAND1 and the grid of the N-channel MOSFET Q4; the other input end of the NAND gate NAND1 is electrically connected with the output end of the NOT2, and the output end of the NAND gate NAND1 is electrically connected with the input end of the NOT2 and the drain electrode of the N-channel MOSFET Q4; the output end of the NOT2 is used for outputting a control signal P _ EA; a positive phase input end of the comparator CP3 is used for receiving the voltage V _ SW, a negative phase input end is used for receiving a reference voltage V _ SW _ Ref, and an output end is electrically connected to the gate of the N-channel MOSFET Q3; the source electrode of the N-channel MOSFET Q3 is electrically connected with the drain electrode of the N-channel MOSFET Q4; the source of N-channel MOSFET Q4 is connected to ground.

When the sampling voltage V _ SW is less than the reference voltage V _ SW _ Ref, the signal output by the comparator Q3 is invalid, the N-channel MOSFET Q3 is turned off, the input terminal of the NOT gate NOT2 is at a high level, and the control signal P _ EA is invalid. Assuming that the sampling voltage V _ SW is greater than the reference voltage V _ SW _ Ref (the signal output by the comparator Q3 is valid) and the frequency-divided signal CLK _ HF is at a low level at a certain time, the gate of the N-channel MOSFET Q4 is at a high level, the N-channel MOSFETs Q3 and Q4 are turned on, so that the input terminal of the NOT gate NOT2 is pulled down to a low level, and the output of the NOT gate NOT2 (i.e., the control signal P _ EA) is at a high level. Before the rising edge of the frequency-divided signal CLK _ HF arrives, the input states of the NAND gate NAND1 and the NOT gate NOT2 do NOT change, and the control signal P _ EA remains at a high level. When the rising edge of the frequency-divided signal CLK _ HF arrives, the level input to the NAND gate NAND1 by the NOT gate NOT1 is converted from high level to low level, the output of the NAND gate NAND1 is converted into high level, the input of the NOT gate NOT2 is further converted into high level, and the output of the NOT gate NOT2 (i.e., the control signal P _ EA) is high level.

It will be appreciated that the divided signal CLK _ HF may be k (k) of the CLK signal>1) The larger the value of k is, the larger the inductive current I of the inductor L is _L The longer the fall time.

As shown in fig. 7, the divided signal CLK _ HF is a divided-by-two signal of the CLK signal, and the period of the CLK signal is T.

Inductor current I with inductor L _L Decrease at t ₁ At this time, the reference voltage V _ Ref2 at the positive phase input terminal of the comparator CP2 decreases to the voltage output from the small comparator CP1 to the negative phase input terminal of the comparator CP2, and the output signal CP2_ OUT of the comparator CP2 changes from the high level to the low level. The signal output from the AND gate AND1 to the CLOCK interface CLOCK of the flip-flop TR1 is thereby converted from high level to low level (i.e., falling edge), AND when the falling edge is detected by the flip-flop TR1, the signal (switching signal S) output from the output terminal Q is output _C ) Set to high. The driving circuit Dr2 outputs a high-level DUTY ratio signal DUTY to the switching tube Q1 and the follow current tube Q2, so that the switching tube Q1 is switched on, the follow current tube Q2 is switched off, and the inductive current I of the inductor L is _L And (4) rising.

It is understood that in other embodiments, the output signal _ CP2_ OUT of the comparator CP2 may be at t due to circuit delay and the like ₂ The time is not limited herein, and the low level is converted into the high level.

At time T, flip-flop TR1 outputs a signal (switching signal S) from output terminal Q when RESET detects a rising edge of the 2 nd CLK signal cycle _C ) Reset to low. The driving circuit Dr2 continues to output a low-level DUTY ratio signal DUTY to the switching tube Q1 and the follow current tube Q2, so that the switching tube Q1 is cut offThe follow current tube Q2 is conducted, and the inductive current I of the inductor L _L And continues to descend.

Inductor current I following inductor L _L Decrease at t ₃ At this time, the reference voltage V _ Ref2 at the positive phase input terminal of the comparator CP2 decreases to the voltage output from the small comparator CP1 to the negative phase input terminal of the comparator CP2, and the output signal CP2_ OUT of the comparator CP2 changes from the high level to the low level. The signal output from the AND gate AND1 to the CLOCK interface CLOCK of the flip-flop TR1 is thereby converted from high level to low level (i.e., falling edge), AND when the falling edge is detected by the flip-flop TR1, the signal (switching signal S) output from the output terminal Q is output _C ) Set to high. Then the driving circuit Dr2 outputs a high-level DUTY ratio signal DUTY to the switching tube Q1 and the follow current tube Q2, so that the switching tube Q1 is switched on, the follow current tube Q2 is switched off, and the inductive current I of the inductor L is _L And (4) rising.

It is understood that, in some embodiments, the current limiting control circuit 10, the current detection circuit Ti1 and the driving circuit Dr2 may also be referred to as a current limiting protection circuit.

It is understood that, in some embodiments, the current limiting control circuit 10, the current detection circuit Ti1, and the driving circuit Dr2 may be integrated on a current limiting protection chip.

Further, an electronic device is provided in an embodiment of the present application, and the electronic device includes the current limiting control circuit 10, the current detection circuit Ti1, and the driving circuit Dr2.

It should be noted that in the accompanying drawings, some structural or methodical features may be shown in a particular arrangement and/or order. However, it is to be understood that such specific arrangement and/or ordering may not be required. Rather, in some embodiments, the features may be arranged in a manner and/or order different from that shown in the illustrative figures. In addition, the inclusion of a structural or methodical feature in a particular figure is not meant to imply that such feature is required in all embodiments, and in some embodiments, may not be included or may be combined with other features.

It should be noted that, in the embodiments of the apparatuses in the present application, each unit/module is a logical unit/module, and physically, one logical unit/module may be one physical unit/module, or may be a part of one physical unit/module, and may also be implemented by a combination of multiple physical units/modules, where the physical implementation manner of the logical unit/module itself is not the most important, and the combination of the functions implemented by the logical unit/module is the key to solve the technical problem provided by the present application. Furthermore, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units/modules which are not so closely related to solve the technical problems presented in the present application, which does not indicate that no other units/modules exist in the above-mentioned device embodiments.

It is noted that, in the examples and descriptions of this patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

While the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.