CN116702821A - A smart card integrating multiple chips and its control method - Google Patents

本发明提出了一种集成多芯片的智能卡及其控制方法，智能卡包括主芯片和多个从芯片，主芯片通过主IO接口与外部读卡器的7816接口连接，使得主芯片能够从外部读卡器获取到控制指令；每个从芯片的IO接口分别独立连接于主芯片的不同GPIO接口，每个GPIO接口可以通过模拟7186时序实现7186接口的模拟，在需要从芯片执行控制指令时，主芯片能够基于模拟的7186时序将控制指令发送给指定的从芯片，并通过主芯片将应答信息反馈至外部读卡器，实现了主从芯片之间的信息通信和独立运行。根据本实施例的技术方案，能够在智能卡中集成多个芯片，实现一卡多号、一卡多运营商或者一卡多SE，每个芯片独立运行且互不影响，提高智能卡的使用灵活性。

The present invention proposes an integrated multi-chip smart card and its control method. The smart card includes a main chip and multiple slave chips. The main chip is connected to the 7816 interface of an external card reader through the main IO interface, so that the main chip can read the card from the outside. The IO interface of each slave chip is independently connected to different GPIO interfaces of the main chip. Each GPIO interface can simulate the 7186 interface by simulating the 7186 timing sequence. When the slave chip needs to execute the control command, the main chip Based on the simulated 7186 sequence, the control command can be sent to the specified slave chip, and the response information can be fed back to the external card reader through the master chip, realizing the information communication and independent operation between the master and slave chips. According to the technical solution of this embodiment, multiple chips can be integrated in the smart card to realize one card with multiple numbers, one card with multiple operators or one card with multiple SEs, each chip operates independently and does not affect each other, improving the use flexibility of the smart card .

一种集成多芯片的智能卡及其控制方法A smart card integrating multiple chips and its control method

技术领域technical field

本发明涉及智能卡技术领域，特别涉及一种集成多芯片的智能卡及其控制方法。The invention relates to the technical field of smart cards, in particular to an integrated multi-chip smart card and a control method thereof.

背景技术Background technique

目前，智能卡中每颗物理芯片可以对应一个号码或者一个运营商，为了实现一卡多号或者一卡多运营商，需要将多个智能卡芯片合封到一张智能卡中。相关技术已经能够在智能卡中集成1颗或者2颗智能卡芯片，当集成的智能卡芯片数量达到3颗或者以上，就需要采用多个7816主接口进行连接通信，但是目前市面上并没有带多个7816主接口的芯片，无法实现多芯片的集成。At present, each physical chip in a smart card can correspond to a number or an operator. In order to realize one card with multiple numbers or one card with multiple operators, it is necessary to seal multiple smart card chips into one smart card. Related technologies have been able to integrate 1 or 2 smart card chips in a smart card. When the number of integrated smart card chips reaches 3 or more, it is necessary to use multiple 7816 main interfaces for connection and communication. However, there are currently no multiple 7816 chips on the market. The chip of the main interface cannot realize the integration of multiple chips.

发明内容Contents of the invention

本发明旨在至少解决现有技术中存在的技术问题之一。为此，本发明提出一种集成多芯片的智能卡及其控制方法，能够在智能卡中集成多颗独立运行的芯片。The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the present invention proposes a multi-chip integrated smart card and a control method thereof, which can integrate a plurality of independently operating chips in the smart card.

第一方面，本发明实施例提供了一种集成多芯片的智能卡，包括：In a first aspect, an embodiment of the present invention provides a smart card integrating multiple chips, including:

主芯片，所述主芯片包括主IO接口和多个GPIO接口，所述主IO接口用于连接外部读卡器的7816接口；Main chip, the main chip includes a main IO interface and a plurality of GPIO interfaces, the main IO interface is used to connect the 7816 interface of the external card reader;

多个从芯片，所述从芯片包括从IO接口，所述从IO接口连接于所述GPIO接口，每个所述从IO接口所连接的所述GPIO接口不同，所述主芯片通过所述GPIO接口模拟7186时序与所述从芯片进行通信。A plurality of slave chips, the slave chip includes a slave IO interface, the slave IO interface is connected to the GPIO interface, each of the slave IO interfaces is connected to a different GPIO interface, and the master chip passes through the GPIO The interface simulates the timing of 7186 to communicate with the slave chip.

根据本发明的一些实施例，所述主芯片和所述从芯片还包括SWP接口，所述主芯片和所述从芯片的SWP接口均连接于所述外部读卡器的SWP接口，其中，当所述主芯片的SWP功能被激活，所述从芯片的SWP接口的引脚状态为悬空，或者，当所述从芯片的SWP功能被激活，所述主芯片和未被激活SWP功能的所述从芯片的SWP接口的引脚状态为悬空，SWP功能处于激活状态的所述从芯片的数量为1。According to some embodiments of the present invention, the master chip and the slave chip further include a SWP interface, and the SWP interfaces of the master chip and the slave chip are both connected to the SWP interface of the external card reader, wherein, when The SWP function of the master chip is activated, and the pin state of the SWP interface of the slave chip is suspended, or, when the SWP function of the slave chip is activated, the master chip and the unactivated SWP function The pin state of the SWP interface of the slave chip is floating, and the number of the slave chip whose SWP function is activated is 1.

根据本发明的一些实施例，所述主芯片和所述从芯片复用RST引脚、VCC引脚、CLK引脚和GND引脚，所述主芯片和所述从芯片响应于输入到所述RST引脚的复位时序进行复位，所述主芯片和所述从芯片通过所述VCC引脚从所述外部读卡器获取工作电源，所述主芯片和所述从芯片通过所述CLK引脚从所述外部读卡器获取工作时钟。According to some embodiments of the present invention, the master chip and the slave chip multiplex the RST pin, the VCC pin, the CLK pin and the GND pin, and the master chip and the slave chip respond to input to the The reset timing of the RST pin is reset, the master chip and the slave chip obtain working power from the external card reader through the VCC pin, and the master chip and the slave chip pass the CLK pin Get the working clock from the external card reader.

第二方面，本发明实施例提供了一种集成多芯片的智能卡的控制方法，应用于如第一方面所述的集成多芯片的智能卡，所述控制方法包括：In a second aspect, an embodiment of the present invention provides a control method for an integrated multi-chip smart card, which is applied to the integrated multi-chip smart card described in the first aspect, and the control method includes:

所述主芯片获取所述外部读卡器发送的控制指令；The main chip obtains the control instruction sent by the external card reader;

通过应答芯片响应所述控制指令并生成应答信息，其中，所述应答芯片为所述主芯片或者多个所述从芯片中的目标从芯片，当所述应答芯片为所述目标从芯片，所述主芯片基于所述GPIO接口模拟的7186时序将所述控制指令发送至所述目标从芯片；Responding to the control instruction through a response chip and generating response information, wherein the response chip is the master chip or a target slave chip among the plurality of slave chips, when the response chip is the target slave chip, the The master chip sends the control instruction to the target slave chip based on the 7186 timing simulated by the GPIO interface;

所述主芯片将所述应答信息发送至所述外部读卡器，其中，当所述应答芯片为所述目标从芯片，所述应答信息由所述目标从芯片发送至所述主芯片。The master chip sends the response information to the external card reader, wherein, when the response chip is the target slave chip, the response information is sent from the target slave chip to the master chip.

根据本发明的一些实施例，所述主芯片中预设有所述主芯片和各个所述从芯片的芯片标识，在所述主芯片获取所述外部读卡器发送的控制指令之前，所述方法还包括：According to some embodiments of the present invention, the master chip is preset with chip identifications of the master chip and each of the slave chips, and before the master chip obtains the control command sent by the external card reader, the Methods also include:

通过所述主芯片获取芯片选择指令，所述芯片选择指令携带有选择标识；Obtaining a chip selection instruction through the main chip, the chip selection instruction carrying a selection identifier;

所述主芯片根据所述选择标识和所述芯片标识确定所述应答芯片。The main chip determines the response chip according to the selection identifier and the chip identifier.

根据本发明的一些实施例，在所述主芯片获取所述外部读卡器发送的控制指令之前，所述方法还包括：According to some embodiments of the present invention, before the main chip acquires the control instruction sent by the external card reader, the method further includes:

当所述主芯片获取到新的芯片选择指令，根据所述新的芯片选择指令中携带的新的选择标识重新确定新的应答芯片；When the main chip acquires a new chip selection command, re-determine a new response chip according to the new selection identifier carried in the new chip selection command;

或者，当所述主芯片获取到选择复位指令，将所述主芯片确定为所述应答芯片。Or, when the master chip acquires the selection reset instruction, determine the master chip as the response chip.

根据本发明的一些实施例，所述主芯片和所述从芯片还包括SWP接口，所述主芯片和所述从芯片的SWP接口均连接于所述外部读卡器的SWP接口，所述集成多芯片的智能卡的控制方法还包括：According to some embodiments of the present invention, the master chip and the slave chip further include SWP interfaces, the SWP interfaces of the master chip and the slave chip are both connected to the SWP interface of the external card reader, and the integrated The control method of the multi-chip smart card also includes:

当所述主芯片的SWP功能被激活，将所述从芯片的SWP接口的引脚状态配置为悬空；When the SWP function of the master chip is activated, the pin state of the SWP interface of the slave chip is configured as floating;

或者，当所述从芯片的SWP功能被激活，将所述主芯片和未被激活SWP功能的所述从芯片的SWP接口的引脚状态配置为悬空，其中，SWP功能处于激活状态的所述从芯片的数量为1。Or, when the SWP function of the slave chip is activated, the pin state of the SWP interface of the master chip and the slave chip whose SWP function is not activated is configured as floating, wherein the SWP function is activated. The number of slave chips is 1.

根据本发明的一些实施例，所述主芯片和所述从芯片复用RST引脚、VCC引脚、CLK引脚和GND引脚，所述主芯片和所述从芯片通过所述VCC引脚从所述外部读卡器获取工作电源，所述主芯片和所述从芯片通过所述CLK引脚从所述外部读卡器获取工作时钟，所述主芯片和所述从芯片响应于输入到所述RST引脚的复位时序进行复位。According to some embodiments of the present invention, the master chip and the slave chip multiplex the RST pin, VCC pin, CLK pin and GND pin, and the master chip and the slave chip pass through the VCC pin Obtain working power from the external card reader, the master chip and the slave chip obtain the working clock from the external card reader through the CLK pin, and the master chip and the slave chip respond to input to The reset timing of the RST pin is reset.

第三方面，本发明实施例提供了一种电子设备，包括有如上述第一方面所述的集成多芯片的智能卡。In a third aspect, an embodiment of the present invention provides an electronic device, including the smart card integrated with multiple chips as described in the first aspect.

第四方面，本发明实施例提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令用于执行如上述第二方面所述的集成多芯片的智能卡的控制方法。In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to execute the method for controlling an integrated multi-chip smart card as described in the second aspect above .

根据本发明实施例的集成多芯片的智能卡，至少具有如下有益效果：智能卡包括主芯片和多个从芯片，主芯片通过主IO接口与外部读卡器的7816接口连接，使得主芯片能够从外部读卡器获取到控制指令；每个从芯片的IO接口分别独立连接于主芯片的不同GPIO接口，每个GPIO接口可以通过模拟7186时序实现7186接口的模拟，在需要从芯片执行控制指令时，主芯片能够基于模拟的7186时序将控制指令发送给指定的从芯片，并通过主芯片将应答信息反馈至外部读卡器，实现了主从芯片之间的信息通信和独立运行。根据本实施例的技术方案，能够在智能卡中集成多个芯片，实现一卡多号、一卡多运营商或者一卡多SE，每个芯片独立运行且互不影响，提高智能卡的使用灵活性。The smart card integrating multiple chips according to the embodiment of the present invention has at least the following beneficial effects: the smart card includes a main chip and a plurality of slave chips, and the main chip is connected to the 7816 interface of the external card reader through the main IO interface, so that the main chip can be read from the outside The card reader obtains the control command; the IO interface of each slave chip is independently connected to different GPIO interfaces of the main chip, and each GPIO interface can simulate the 7186 interface by simulating the 7186 timing sequence. When it is necessary to execute the control command from the chip, Based on the simulated 7186 timing sequence, the main chip can send control instructions to the designated slave chip, and feed back the response information to the external card reader through the main chip, realizing the information communication and independent operation between the master and slave chips. According to the technical solution of this embodiment, multiple chips can be integrated in the smart card to realize one card with multiple numbers, one card with multiple operators or one card with multiple SEs, each chip operates independently and does not affect each other, improving the flexibility of use of the smart card .

附图说明Description of drawings

图1是本发明一个实施例提供的集成多芯片的智能卡的结构示意图；Fig. 1 is a schematic structural diagram of an integrated multi-chip smart card provided by an embodiment of the present invention;

图2是本发明另一个实施例提供的集成多芯片的智能卡的控制方法的流程图；Fig. 2 is a flow chart of a control method for an integrated multi-chip smart card provided by another embodiment of the present invention;

图3是本发明另一个实施例提供的时序示例图；Fig. 3 is a timing diagram provided by another embodiment of the present invention;

图4是本发明另一个实施例提供的确定应答芯片的流程图；Fig. 4 is a flow chart of determining the response chip provided by another embodiment of the present invention;

图5是本发明另一个实施例提供的更换应答芯片的流程图；Fig. 5 is a flow chart of replacing the response chip provided by another embodiment of the present invention;

图6是本发明另一个实施例提供的激活SWP功能的流程图；Fig. 6 is a flow chart of activating the SWP function provided by another embodiment of the present invention;

图7是本发明另一个实施例提供的电子设备的装置示意图。Fig. 7 is a schematic diagram of an electronic device provided by another embodiment of the present invention.

具体实施方式Detailed ways

下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

在本发明的描述中，需要理解的是，涉及到方位描述，例如上、下、前、后、左、右等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。In the description of the present invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc. indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only In order to facilitate the description of the present invention and simplify the description, it does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.

在本发明的描述中，若干的含义是一个或者多个，多个的含义是两个以上，大于、小于、超过等理解为不包括本数，以上、以下、以内等理解为包括本数。如果有描述到第一、第二只是用于区分技术特征为目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量或者隐含指明所指示的技术特征的先后关系。In the description of the present invention, several means one or more, and multiple means more than two. Greater than, less than, exceeding, etc. are understood as not including the original number, and above, below, within, etc. are understood as including the original number. If the description of the first and second is only for the purpose of distinguishing the technical features, it cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features relation.

本发明的描述中，除非另有明确的限定，设置、安装、连接等词语应做广义理解，所属技术领域技术人员可以结合技术方案的具体内容合理确定上述词语在本发明中的具体含义。In the description of the present invention, unless otherwise clearly defined, words such as setting, installation, and connection should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

本发明实施例提供了一种集成多芯片的智能卡及其控制方法，智能卡包括主芯片和多个从芯片，主芯片通过主IO接口与外部读卡器的7816接口连接，使得主芯片能够从外部读卡器获取到控制指令；每个从芯片的IO接口分别独立连接于主芯片的不同GPIO接口，每个GPIO接口可以通过模拟7186时序实现7186接口的模拟，在需要从芯片执行控制指令时，主芯片能够基于模拟的7186时序将控制指令发送给指定的从芯片，并通过主芯片将应答信息反馈至外部读卡器，实现了主从芯片之间的信息通信和独立运行。根据本实施例的技术方案，能够在智能卡中集成多个芯片，实现一卡多号、一卡多运营商或者一卡多SE，每个芯片独立运行且互不影响，提高智能卡的使用灵活性。The embodiment of the present invention provides a smart card with integrated multi-chips and its control method. The smart card includes a master chip and a plurality of slave chips. The card reader obtains the control command; the IO interface of each slave chip is independently connected to different GPIO interfaces of the main chip, and each GPIO interface can simulate the 7186 interface by simulating the 7186 timing sequence. When it is necessary to execute the control command from the chip, Based on the simulated 7186 timing sequence, the main chip can send control instructions to the designated slave chip, and feed back the response information to the external card reader through the main chip, realizing the information communication and independent operation between the master and slave chips. According to the technical solution of this embodiment, multiple chips can be integrated in the smart card to realize one card with multiple numbers, one card with multiple operators or one card with multiple SEs, each chip operates independently and does not affect each other, improving the flexibility of use of the smart card .

下面结合附图，对本发明实施例的技术方案作进一步阐述。The technical solutions of the embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

参照图1，图1为本发明实施例提供的一种集成多芯片的智能卡的结构示意图，该智能卡包括：Referring to Fig. 1, Fig. 1 is a schematic structural diagram of a smart card integrating multiple chips provided by an embodiment of the present invention, the smart card includes:

主芯片1，主芯片1包括主IO接口和多个GPIO接口，主IO接口用于连接外部读卡器3的7816接口；The main chip 1, the main chip 1 includes the main IO interface and multiple GPIO interfaces, the main IO interface is used to connect the 7816 interface of the external card reader 3;

多个从芯片，从芯片包括从IO接口，从IO接口连接于GPIO接口，每个从IO接口所连接的GPIO接口不同，主芯片1通过GPIO接口模拟7186时序与从芯片进行通信。Multiple slave chips, the slave chip includes a slave IO interface, the slave IO interface is connected to the GPIO interface, each slave IO interface is connected to a different GPIO interface, and the master chip 1 communicates with the slave chip through the GPIO interface to simulate the 7186 timing.

需要说明的是，如图1所示，在智能卡中包括至少3个芯片，其中包括一个主芯片1和多个从芯片。主芯片1的主IO接口与外部读卡器3的7186接口连接，使得主芯片1能够与外部读卡器3进行通信交互，例如获取外部读卡器3发送的指令，又如，主芯片1向外部读卡器3发送应答信息。从芯片的从IO接口与主芯片1的GPIO接口唯一对应连接，即主芯片1的每个GPIO接口连接一个从芯片，使得每个主芯片1能够根据不同的GPIO接口独立与对应的从芯片进行数据收发，实现每个物理芯片的独立运行。示例性地，如图1所示，主芯片1包括3个GPIO接口，分别为GPIO1、GPIO2和GPIO3，智能卡中包括3个从芯片，分别为第一从芯片21、第二从芯片22和第三从芯片23，第一从芯片21的从IO接口与GPIO1连接，第二从芯片22的从IO接口与GPIO2连接，第三从芯片23的从IO接口与GPIO3连接。从芯片的最大数量可以是主芯片1能提供的GPIO接口的最大数量，确保每个从芯片的从IO接口能够唯一连接一个GPIO接口即可。It should be noted that, as shown in FIG. 1 , the smart card includes at least 3 chips, including a master chip 1 and multiple slave chips. The main IO interface of the main chip 1 is connected to the 7186 interface of the external card reader 3, so that the main chip 1 can communicate and interact with the external card reader 3, for example, obtain instructions sent by the external card reader 3, and for example, the main chip 1 Send response information to the external card reader 3. The slave IO interface of the slave chip is uniquely connected to the GPIO interface of the master chip 1, that is, each GPIO interface of the master chip 1 is connected to a slave chip, so that each master chip 1 can independently communicate with the corresponding slave chip according to different GPIO interfaces. Data is sent and received to realize the independent operation of each physical chip. Exemplarily, as shown in Figure 1, the main chip 1 includes 3 GPIO interfaces, respectively GPIO1, GPIO2 and GPIO3, and the smart card includes 3 slave chips, respectively the first slave chip 21, the second slave chip 22 and the first slave chip 22. Three slave chips 23, the slave IO interface of the first slave chip 21 is connected to GPIO1, the slave IO interface of the second slave chip 22 is connected to GPIO2, and the slave IO interface of the third slave chip 23 is connected to GPIO3. The maximum number of slave chips can be the maximum number of GPIO interfaces that the main chip 1 can provide, and it is only necessary to ensure that the slave IO interface of each slave chip can be uniquely connected to one GPIO interface.

需要说明的是，由于从芯片通过从IO接口独占主芯片1的一个GPIO接口，因此本实施例的每颗芯片能够独立响应外部读卡器3发送的控制指令。示例性地，当外部读卡器3发送的控制指令由主芯片1应答，主芯片1通过主IO接口接收到控制指令后直接响应并且反馈即可；当外部读卡器3发送的控制指令由第一从芯片21进行应答，主芯片1通过主IO接口接收到控制指令后，基于GPIO1模拟的7186时序将控制指令发送给第一从芯片21的从IO接口，第一从芯片21获取到控制指令后进行响应，生成的应答信息可以通过主芯片1转发至外部读卡器3，此时主芯片1只进行控制指令和应答信息的转发，并不涉及指令的响应，从而实现每颗芯片独立响应控制指令，确保指令响应的准确性。It should be noted that, since the slave chip monopolizes a GPIO interface of the master chip 1 through the slave IO interface, each chip in this embodiment can independently respond to the control command sent by the external card reader 3 . Exemplarily, when the control command sent by the external card reader 3 is answered by the main chip 1, the main chip 1 directly responds and feeds back after receiving the control command through the main IO interface; when the control command sent by the external card reader 3 is sent by the The first slave chip 21 responds. After the master chip 1 receives the control command through the master IO interface, it sends the control command to the slave IO interface of the first slave chip 21 based on the 7186 timing sequence simulated by GPIO1, and the first slave chip 21 acquires the control command. Respond after the command, and the generated response information can be forwarded to the external card reader 3 through the main chip 1. At this time, the main chip 1 only forwards the control command and response information, and does not involve the response of the command, so that each chip is independent. Respond to control instructions to ensure the accuracy of instruction responses.

需要说明的是，主芯片对7186时序进行模拟是基于通信需求触发，具体模拟7186时序的GPIO接口根据需要通信的目标从芯片确定，例如上述所述，当需要与第一从芯片21进行通信，通过GPIO1模拟7186时序并进行信息交互，其余GPIO接口不执行操作，以确保信息交互的独立性。It should be noted that the main chip's simulation of the 7186 timing sequence is triggered based on communication requirements. The specific GPIO interface for simulating the 7186 timing sequence is determined according to the target slave chip that needs to communicate. For example, as described above, when it is necessary to communicate with the first slave chip 21, Simulate the timing of 7186 through GPIO1 and perform information interaction, and the other GPIO interfaces do not perform operations to ensure the independence of information interaction.

通过本实施例的技术方案，智能卡能够通过主芯片的多个GPIO接口集成多个从芯片，需要主芯片应答时，主芯片可以直接从外部读卡器接收指令并且响应；需要从芯片应答时，由于控制指令是由外部读卡器通过7186接口发送的，通过主芯片的GPIO口模拟7186时序，从而实现7186接口的模拟，使得控制指令能够转发到对应的从芯片进行响应，通过主芯片作为从芯片的指令转发芯片，由于在智能卡内基于7186时序的模拟实现了信息传递，使得智能卡内能够实现3颗以上物理芯片独立运行，在无需芯片具备多个7186接口的情况下实现了在智能卡内集成多颗芯片，使得智能卡能够用于实现一卡多号和一卡多运营商。Through the technical solution of this embodiment, the smart card can integrate multiple slave chips through multiple GPIO interfaces of the master chip. When the master chip needs to respond, the master chip can directly receive instructions from the external card reader and respond; when the slave chip needs to respond, Since the control command is sent by the external card reader through the 7186 interface, the 7186 timing sequence is simulated through the GPIO port of the main chip, thereby realizing the simulation of the 7186 interface, so that the control command can be forwarded to the corresponding slave chip for response, and the master chip acts as a slave The instruction forwarding chip of the chip realizes the information transmission based on the simulation of 7186 timing in the smart card, so that more than 3 physical chips can run independently in the smart card, and realizes the integration in the smart card without the need for the chip to have multiple 7186 interfaces. With multiple chips, the smart card can be used to realize one card with multiple numbers and one card with multiple operators.

另外，在一些实施例中，参照图1，主芯片和从芯片还包括SWP接口，主芯片和从芯片的SWP接口均连接于外部读卡器的SWP接口，其中，当主芯片的SWP功能被激活，从芯片的SWP接口的引脚状态为悬空，或者，当从芯片的SWP功能被激活，主芯片和未被激活SWP功能的从芯片的SWP接口的引脚状态为悬空，SWP功能处于激活状态的从芯片的数量为1。In addition, in some embodiments, referring to FIG. 1, the master chip and the slave chip also include SWP interfaces, and the SWP interfaces of the master chip and the slave chip are connected to the SWP interface of the external card reader, wherein, when the SWP function of the master chip is activated , the pin state of the SWP interface of the slave chip is floating, or, when the SWP function of the slave chip is activated, the pin state of the SWP interface of the master chip and the slave chip that has not activated the SWP function is floating, and the SWP function is activated The number of slave chips is 1.

需要说明的是，如图1所示，智能卡中每个芯片的SWP接口均与外部读卡器3的SWP接口相连接，所有芯片的SWP功能同一时间只激活一个，其他不激活的SWP功能配置引脚状态为悬空，使得当前激活的SWP接口不受其他芯片SWP接口影响。It should be noted that, as shown in Figure 1, the SWP interface of each chip in the smart card is connected to the SWP interface of the external card reader 3, and only one SWP function of all chips is activated at the same time, and other inactive SWP functions are configured The state of the pin is suspended, so that the currently activated SWP interface is not affected by the SWP interface of other chips.

示例性地，如图1所示，当主芯片1的SWP功能被激活，第一从芯片21、第二从芯片22和第三从芯片23的SWP接口的引脚状态设置为悬空；又如，当第二从芯片22的SWP功能被激活，主芯片1、第一从芯片21和第三从芯片23的SWP接口的引脚状态设置为悬空。Exemplarily, as shown in Figure 1, when the SWP function of master chip 1 is activated, the pin state of the SWP interface of the first slave chip 21, the second slave chip 22 and the third slave chip 23 is set to be suspended; When the SWP function of the second slave chip 22 is activated, the state of the pins of the SWP interfaces of the master chip 1 , the first slave chip 21 and the third slave chip 23 is set to be suspended.

另外，在一些实施例中，参照图1，主芯片和从芯片复用RST引脚、VCC引脚、CLK引脚和GND引脚，主芯片和从芯片响应于输入到RST引脚的复位时序进行复位，主芯片和从芯片通过VCC引脚从外部读卡器获取工作电源，主芯片和从芯片通过CLK引脚从外部读卡器获取工作时钟。In addition, in some embodiments, referring to FIG. 1, the master chip and the slave chip multiplex the RST pin, the VCC pin, the CLK pin and the GND pin, and the master chip and the slave chip respond to the reset sequence input to the RST pin After reset, the master chip and the slave chip get working power from the external card reader through the VCC pin, and the master chip and the slave chip get the working clock from the external card reader through the CLK pin.

需要说明的是，主芯片和从芯片复用RST引脚，当RST引脚产生复位时序时，能够确保所有芯片同时进行复位，确保各个芯片的状态保持一致。It should be noted that the master chip and the slave chip multiplex the RST pin, and when the RST pin generates a reset sequence, it can ensure that all chips are reset at the same time to ensure that the states of each chip are consistent.

需要说明的是，主芯片和从芯片复用VCC引脚获取工作电源，能够确保主芯片和从芯片同时具备工作电源，避免单个芯片断电。It should be noted that the master chip and the slave chip multiplex the VCC pin to obtain the working power, which can ensure that the master chip and the slave chip have working power at the same time, and avoid a single chip from being powered off.

需要说明的是，主芯片和从芯片复用CLK引脚获取工作时钟，能够确保多个芯片工作在相同的时钟，避免时钟不对应导致通信出错。It should be noted that the master chip and the slave chip multiplex the CLK pin to obtain the working clock, which can ensure that multiple chips work on the same clock, and avoid communication errors caused by mismatched clocks.

另外，本发明实施例还提供了一种集成多芯片的智能卡的控制方法，应用于如图1所示的集成多芯片的智能卡，参照图2，集成多芯片的智能卡的控制方法包括但不限于有以下步骤：In addition, the embodiment of the present invention also provides a control method for an integrated multi-chip smart card, which is applied to the integrated multi-chip smart card shown in Figure 1. Referring to Figure 2, the control method for the integrated multi-chip smart card includes but is not limited to There are following steps:

S21，主芯片获取外部读卡器发送的控制指令；S21, the main chip obtains the control command sent by the external card reader;

S22，通过应答芯片响应控制指令并生成应答信息，其中，应答芯片为主芯片或者多个从芯片中的目标从芯片，当应答芯片为目标从芯片，主芯片基于GPIO接口模拟的7186时序将控制指令发送至目标从芯片；S22, responding to the control command through the response chip and generating response information, wherein the response chip is the master chip or the target slave chip among multiple slave chips, when the response chip is the target slave chip, the master chip will control the The instruction is sent to the target slave chip;

S23，主芯片将应答信息发送至外部读卡器，其中，当应答芯片为目标从芯片，应答信息由目标从芯片发送至主芯片。S23, the master chip sends the response information to the external card reader, wherein, when the response chip is the target slave chip, the response information is sent from the target slave chip to the master chip.

需要说明的是，智能卡与外部读卡器的接口连接关系可以参考图1所示实施例的描述，在此不重复赘述。It should be noted that for the interface connection relationship between the smart card and the external card reader, reference may be made to the description of the embodiment shown in FIG. 1 , which will not be repeated here.

需要说明的是，参考图1所示实施例的描述，每颗芯片均可以独立作为控制指令的应答芯片，由于外部读卡器只与主芯片连接，并不能直接与从芯片进行通信，因此在主芯片获取到外部读卡器发送的控制指令后，需要由主芯片确保控制指令传递到应答芯片，即由主芯片确定控制指令是由自己处理还是派发到对应的多个从芯片中的一个目标从芯片。当应答芯片为主芯片，主芯片接收到控制指令后直接响应生成应答信息，并且通过主IO接口直接反馈至外部读卡器即可。当应答芯片为目标从芯片，由于主芯片与从芯片可以通过GPIO口模拟的7186时序进行信息交互，以主芯片作为中转芯片将控制指令转发到目标从芯片，由目标从芯片对控制指令进行响应并生成应答信息。It should be noted that, with reference to the description of the embodiment shown in Figure 1, each chip can be independently used as a response chip for control commands. Since the external card reader is only connected to the master chip, it cannot directly communicate with the slave chip. After the main chip obtains the control command sent by the external card reader, the main chip needs to ensure that the control command is passed to the response chip, that is, the main chip determines whether the control command is processed by itself or dispatched to one of the corresponding multiple slave chips. from the chip. When the response chip is the main chip, the main chip directly responds to generate response information after receiving the control command, and directly feeds back to the external card reader through the main IO interface. When the response chip is the target slave chip, since the master chip and the slave chip can exchange information through the 7186 timing simulated by the GPIO port, the master chip is used as the transfer chip to forward the control command to the target slave chip, and the target slave chip responds to the control command and generate a response message.

需要说明的是，芯片对控制指令的响应和生成应答信息为本领域技术人员熟知的技术，本实施例对此不多做赘述。It should be noted that the response of the chip to the control command and the generation of response information are technologies well known to those skilled in the art, and this embodiment will not repeat them here.

示例性地，参照图3所示，图3为本实施例提供的指令时序图，当主芯片需要将控制指令派发到目标从芯片，主芯片用于连接目标从芯片的GPIO接口模拟7816时序，以实现兼容芯片原有7816接口通信，例如，当外部读卡器发送控制指令0x953b2e66718c1f5a到主芯片，主芯片通过模拟7816时序发送给目标从芯片，目标从芯片处理完后返回0x9000给主芯片，主芯片再将0x9000返回给外部读卡器。Exemplarily, referring to FIG. 3, FIG. 3 is an instruction timing diagram provided in this embodiment. When the master chip needs to dispatch control instructions to the target slave chip, the master chip is used to connect the GPIO interface of the target slave chip to simulate the 7816 timing sequence to Realize the original 7816 interface communication of the compatible chip. For example, when the external card reader sends the control command 0x953b2e66718c1f5a to the main chip, the main chip sends it to the target slave chip through simulating the 7816 sequence, and the target slave chip returns 0x9000 to the main chip after processing. Then return 0x9000 to the external card reader.

需要说明的是，当主芯片为应答芯片时，应答信息由主芯片自身生成，当目标从芯片为应答芯片时，应答信息由目标从芯片生成并发送至主芯片，主芯片在生成或者获取到应答信息后，通过主IO接口返回至外部读卡器，从而实现响应控制指令的完整过程。It should be noted that when the master chip is the response chip, the response information is generated by the master chip itself; when the target slave chip is the response chip, the response information is generated by the target slave chip and sent to the master chip, and the master chip generates or obtains the response After receiving the information, it returns to the external card reader through the main IO interface, so as to realize the complete process of responding to the control command.

另外，在一实施例中，主芯片中预设有主芯片和各个从芯片的芯片标识，参照图4，在执行图2所示的步骤S21之前，还包括但不限于有以下步骤：In addition, in one embodiment, the master chip is preset with chip identifications of the master chip and each slave chip. Referring to FIG. 4 , before performing step S21 shown in FIG. 2 , it also includes but is not limited to the following steps:

S41，通过主芯片获取芯片选择指令，芯片选择指令携带有选择标识；S41. Obtain a chip selection instruction through the main chip, and the chip selection instruction carries a selection identifier;

S42，主芯片根据选择标识和芯片标识确定应答芯片。S42. The main chip determines the response chip according to the selection identifier and the chip identifier.

需要说明的是，根据图2所示实施例的描述，在获取到控制指令后需要由主芯片确定自身处理还是派发到目标从芯片，本实施例通过芯片选择指令确定具体的应答芯片，芯片选择指令可以通过外部读卡器生成并发送到主芯片，主芯片在通过芯片选择指令确定应答芯片后可以保存该信息，从而将后续获取到的控制指令都配发到该芯片。It should be noted that, according to the description of the embodiment shown in Figure 2, after obtaining the control command, it is necessary for the master chip to determine whether to process it or dispatch it to the target slave chip. In this embodiment, the specific response chip is determined through the chip selection command, and the chip selection The command can be generated by an external card reader and sent to the main chip. After the main chip determines the response chip through the chip selection command, the information can be saved, so that all subsequent control commands obtained are distributed to the chip.

需要说明的是，为了区分不同的芯片，可以为每个芯片预设芯片标识，例如图1所示的4个芯片，为主芯片配置的芯片标识为00，为第一从芯片配置的芯片标识为01，为第二从芯片配置的芯片标识为02，为第三从芯片配置的芯片标识为03，芯片选择指令的格式可以为0x00A404000200XX，其中XX为对应的选择标识，例如当需要选择主芯片作为应答芯片，芯片选择指令可以是0x00A40400020000，当需要选择第三从芯片作为应答芯片，芯片选择指令可以是0x00A40400020003。主芯片获取到芯片选择指令后，根据选择标识所处的位置进行标识的提取，再通过与芯片标识进行比对确定应答芯片。It should be noted that, in order to distinguish different chips, a chip ID can be preset for each chip. For example, for the four chips shown in Figure 1, the chip ID configured for the master chip is 00, and the chip ID configured for the first slave chip is 00. 01, the chip ID configured for the second slave chip is 02, the chip ID configured for the third slave chip is 03, the format of the chip selection command can be 0x00A404000200XX, where XX is the corresponding selection ID, for example, when the master chip needs to be selected As the response chip, the chip selection command can be 0x00A40400020000, when the third slave chip needs to be selected as the response chip, the chip selection command can be 0x00A40400020003. After the main chip obtains the chip selection instruction, it extracts the identification according to the location of the selection identification, and then determines the response chip by comparing with the chip identification.

另外，在一实施例中，参照图5，在执行图2所示的步骤S21之前，还包括但不限于有以下步骤：In addition, in one embodiment, referring to FIG. 5 , before performing step S21 shown in FIG. 2 , it also includes but is not limited to the following steps:

S51当主芯片获取到新的芯片选择指令，根据新的芯片选择指令中携带的新的选择标识重新确定新的应答芯片；S51 When the main chip acquires a new chip selection instruction, re-determine a new response chip according to the new selection identifier carried in the new chip selection instruction;

S52，当主芯片获取到选择复位指令，将主芯片确定为应答芯片。S52, when the main chip obtains the selection reset instruction, determine the main chip as the response chip.

需要说明的是，根据图4所示实施例的描述，可以通过向主芯片发送芯片选择指令确定应答芯片，主芯片确定应答芯片后记录该选择，将每次获取到的控制指令配发到应答芯片，当需要切换不同的芯片作为应答芯片时，可以向主芯片发送新的芯片选择指令，使得主芯片根据新的芯片选择指令重复图4所示实施例的步骤确定新的应答芯片，在此对芯片选择的步骤不重复赘述。It should be noted that, according to the description of the embodiment shown in Figure 4, the response chip can be determined by sending a chip selection command to the main chip, the main chip determines the response chip and records the selection, and distributes the control command obtained each time to the response chip. Chip, when it is necessary to switch different chips as the response chip, it can send a new chip selection instruction to the main chip, so that the main chip repeats the steps of the embodiment shown in Figure 4 to determine a new response chip according to the new chip selection instruction. The steps of chip selection are not repeated.

需要说明的是，除了对应答芯片进行选择和切换，还可以向主芯片发送复位指令，使得智能卡复位对应答芯片的选择，在复位后可以选择默认芯片作为应答芯片，例如可以将主芯片设置为默认芯片，当然也可以设置其中一个从芯片作为默认芯片，本实施例对此不多做限定。It should be noted that, in addition to selecting and switching the answering chip, a reset command can also be sent to the main chip, so that the smart card resets the selection of the answering chip. After the reset, the default chip can be selected as the answering chip. For example, the main chip can be set to The default chip, of course, can also set one of the slave chips as the default chip, which is not limited in this embodiment.

需要说明的是，默认芯片还可以作为初始的应答芯片，即智能卡获取到芯片选择指令之前的应答芯片，例如在智能卡首次使用时，确保多颗芯片中有一颗作为应答芯片实现控制指令的应答即可。It should be noted that the default chip can also be used as the initial response chip, that is, the response chip before the smart card obtains the chip selection command. Can.

另外，在一实施例中，参照图6，集成多芯片的智能卡的控制方法还包括但不限于有以下步骤：In addition, in one embodiment, referring to FIG. 6 , the control method of the smart card integrating multiple chips also includes but not limited to the following steps:

S61，当主芯片的SWP功能被激活，将从芯片的SWP接口的引脚状态配置为悬空；S61, when the SWP function of the main chip is activated, the pin state of the SWP interface of the slave chip is configured as floating;

S62，当从芯片的SWP功能被激活，将主芯片和未被激活SWP功能的从芯片的SWP接口的引脚状态配置为悬空，其中，SWP功能处于激活状态的从芯片的数量为1。S62. When the SWP function of the slave chip is activated, the pin state of the SWP interface of the master chip and the slave chip whose SWP function is not activated is configured as floating, wherein the number of slave chips whose SWP function is activated is 1.

需要说明的是，如图1所示，智能卡中每个芯片的SWP接口均与外部读卡器的SWP接口相连接，所有芯片的SWP功能同一时间只激活一个，其他不激活的SWP功能配置引脚状态为悬空，使得当前激活的SWP接口不受其他芯片SWP接口影响。It should be noted that, as shown in Figure 1, the SWP interface of each chip in the smart card is connected to the SWP interface of the external card reader, and only one SWP function of all chips is activated at the same time, and other inactive SWP function configuration boots The state of the pin is floating, so that the currently activated SWP interface is not affected by the SWP interface of other chips.

另外，在一实施例中，主芯片和从芯片复用RST引脚、VCC引脚、CLK引脚和GND引脚，主芯片和从芯片通过VCC引脚从外部读卡器获取工作电源，主芯片和从芯片通过CLK引脚从外部读卡器获取工作时钟，主芯片和从芯片响应于输入到RST引脚的复位时序进行复位。In addition, in one embodiment, the master chip and the slave chip multiplex RST pins, VCC pins, CLK pins and GND pins, the master chip and the slave chip obtain operating power from the external card reader through the VCC pin, and the master chip The chip and the slave chip obtain the working clock from the external card reader through the CLK pin, and the master chip and the slave chip reset in response to the reset sequence input to the RST pin.

需要说明的是，主芯片和从芯片复用RST引脚，当RST引脚产生复位时序时，能够确保所有芯片同时进行复位，确保各个芯片的状态保持一致。It should be noted that the master chip and the slave chip multiplex the RST pin, and when the RST pin generates a reset sequence, it can ensure that all chips are reset at the same time to ensure that the states of each chip are consistent.

需要说明的是，主芯片和从芯片复用VCC引脚获取工作电源，能够确保主芯片和从芯片同时具备工作电源，避免单个芯片断电。It should be noted that the master chip and the slave chip multiplex the VCC pin to obtain the working power, which can ensure that the master chip and the slave chip have working power at the same time, and avoid a single chip from being powered off.

需要说明的是，主芯片和从芯片复用CLK引脚获取工作时钟，能够确保多个芯片工作在相同的时钟，避免时钟不对应导致通信出错。It should be noted that the master chip and the slave chip multiplex the CLK pin to obtain the working clock, which can ensure that multiple chips work on the same clock, and avoid communication errors caused by mismatched clocks.

如图7所示，图7是本发明一个实施例提供的电子设备的结构图。本发明还提供了一种电子设备，包括如上所述的集成多芯片的智能卡，还包括：As shown in FIG. 7, FIG. 7 is a structural diagram of an electronic device provided by an embodiment of the present invention. The present invention also provides an electronic device, including the above-mentioned integrated multi-chip smart card, and also includes:

处理器701，可以采用通用的中央处理器(Central Processing Unit，CPU)、微处理器、应用专用集成电路(Application Specific Integrated Circuit，ASIC)、或者一个或多个集成电路等方式实现，用于执行相关程序，以实现本申请实施例所提供的技术方案；The processor 701 may be implemented by a general-purpose central processing unit (Central Processing Unit, CPU), a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute Relevant programs to realize the technical solutions provided by the embodiments of the present application;

存储器702，可以采用只读存储器(Read Only Memory，ROM)、静态存储设备、动态存储设备或者随机存取存储器(Random Access Memory，RAM)等形式实现。存储器702可以存储操作系统和其他应用程序，在通过软件或者固件来实现本说明书实施例所提供的技术方案时，相关的程序代码保存在存储器702中，并由处理器701来调用执行本申请实施例的集成多芯片的智能卡的控制方法；The memory 702 may be implemented in the form of a read only memory (Read Only Memory, ROM), a static storage device, a dynamic storage device, or a random access memory (Random Access Memory, RAM). The memory 702 can store operating systems and other application programs. When implementing the technical solutions provided by the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 702 and called by the processor 701 to execute the implementation of the present application. The control method of the integrated multi-chip smart card of the example;

输入/输出接口703，用于实现信息输入及输出；The input/output interface 703 is used to realize information input and output;

通信接口704，用于实现本设备与其他设备的通信交互，可以通过有线方式(例如USB、网线等)实现通信，也可以通过无线方式(例如移动网络、WIFI、蓝牙等)实现通信；The communication interface 704 is used to realize the communication interaction between the device and other devices, and the communication can be realized through a wired method (such as USB, network cable, etc.), or can be realized through a wireless method (such as a mobile network, WIFI, Bluetooth, etc.);

总线705，在设备的各个组件(例如处理器701、存储器702、输入/输出接口703和通信接口704)之间传输信息；A bus 705, which transmits information between various components of the device (such as a processor 701, a memory 702, an input/output interface 703, and a communication interface 704);

其中处理器701、存储器702、输入/输出接口703和通信接口704通过总线705实现彼此之间在设备内部的通信连接。The processor 701 , the memory 702 , the input/output interface 703 and the communication interface 704 are connected to each other within the device through the bus 705 .

本申请实施例还提供了一种存储介质，存储介质为计算机可读存储介质，该存储介质存储有计算机程序，该计算机程序被处理器执行时实现上述集成多芯片的智能卡的控制方法。The embodiment of the present application also provides a storage medium, the storage medium is a computer-readable storage medium, and the storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned control method of the integrated multi-chip smart card is realized.

存储器作为一种非暂态计算机可读存储介质，可用于存储非暂态软件程序以及非暂态性计算机可执行程序。此外，存储器可以包括高速随机存取存储器，还可以包括非暂态存储器，例如至少一个磁盘存储器件、闪存器件、或其他非暂态固态存储器件。在一些实施方式中，存储器可选包括相对于处理器远程设置的存储器，这些远程存储器可以通过网络连接至该处理器。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。以上所描述的装置实施例仅仅是示意性的，其中作为分离部件说明的单元可以是或者也可以不是物理上分开的，实现了以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。As a non-transitory computer-readable storage medium, memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory optionally includes memory located remotely from the processor, and these remote memories may be connected to the processor via a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and may be implemented so as to be located in one place, or may also be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统可以被实施为软件、固件、硬件及其适当的组合。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包括计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。Those skilled in the art can understand that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware and an appropriate combination thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit . Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those of ordinary skill in the art, the term computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can Any other medium used to store desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embody computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

以上是对本发明的较佳实施进行了具体说明，但本发明并不局限于上述实施方式，熟悉本领域的技术人员在不违背本发明精神的共享条件下还可作出种种等同的变形或替换，这些等同的变形或替换均包括在本发明权利要求所限定的范围内。The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned embodiment, and those skilled in the art can also make various equivalent deformations or replacements without violating the spirit of the present invention. These equivalent modifications or replacements are all within the scope defined by the claims of the present invention.