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CN116827097A - A high-side gate drive circuit that is immune to dVS/dt noise - Google Patents

  • ️Fri Sep 29 2023

CN116827097A - A high-side gate drive circuit that is immune to dVS/dt noise - Google Patents

A high-side gate drive circuit that is immune to dVS/dt noise Download PDF

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Publication number
CN116827097A
CN116827097A CN202310866262.5A CN202310866262A CN116827097A CN 116827097 A CN116827097 A CN 116827097A CN 202310866262 A CN202310866262 A CN 202310866262A CN 116827097 A CN116827097 A CN 116827097A Authority
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circuit
gate
transistor
signal
output
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2023-07-14
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代雄志
王传政
喻明艳
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Beijing Zhuoxin Semiconductor Technology Co ltd
Hangzhou Dianzi University
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Beijing Zhuoxin Semiconductor Technology Co ltd
Hangzhou Dianzi University
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2023-07-14
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2023-07-14
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2023-09-29
2023-07-14 Application filed by Beijing Zhuoxin Semiconductor Technology Co ltd, Hangzhou Dianzi University filed Critical Beijing Zhuoxin Semiconductor Technology Co ltd
2023-07-14 Priority to CN202310866262.5A priority Critical patent/CN116827097A/en
2023-09-29 Publication of CN116827097A publication Critical patent/CN116827097A/en
Status Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

本发明公开了一种可抗dVS/dt噪声的高侧栅极驱动电路。本发明高压电平移位电路的输入来源于低侧脉冲边缘获取电路产生的双路窄脉冲，其输出作为电流源电路的输入，控制电流源电路是否工作；电流源电路的两路输出信号一方面作为RS触发器的输入，另一方面两路信号经过与非门和非门的逻辑转换后，产生传输门的控制信号；传输门的输入信号为RS触发器电路的输出信号，其输出信号为输出驱动电路的输入信号，反相器为输出驱动电路的一部分，输出驱动级电路通过输出驱动信号控制外部功率管的开与关。本发明抗共模噪声能力更强，且在电源电压稳定时，不影响电路的正常工作状况。本发明中无需加入额外滤波电路，电路传输延时大大降低，有效提高信号的传输效率。

The invention discloses a high-side gate drive circuit that is resistant to dV S /dt noise. The input of the high-voltage level shift circuit of the present invention comes from the dual-channel narrow pulses generated by the low-side pulse edge acquisition circuit, and its output is used as the input of the current source circuit to control whether the current source circuit works; the two-channel output signals of the current source circuit are one On the one hand, it serves as the input of the RS flip-flop, and on the other hand, the two signals are converted by the logic of the NAND gate and the NOT gate to generate the control signal of the transmission gate; the input signal of the transmission gate is the output signal of the RS flip-flop circuit, and its output signal As the input signal of the output drive circuit, the inverter is part of the output drive circuit. The output drive stage circuit controls the on and off of the external power tube through the output drive signal. The invention has stronger resistance to common mode noise and does not affect the normal working condition of the circuit when the power supply voltage is stable. In the present invention, there is no need to add additional filtering circuits, the circuit transmission delay is greatly reduced, and the signal transmission efficiency is effectively improved.

Description

一种可抗dVS/dt噪声的高侧栅极驱动电路A high-side gate drive circuit that is immune to dVS/dt noise

技术领域Technical field

本发明涉及可抗噪声干扰的高压栅极驱动领域，特别涉及一种应用于电机驱动领域的高压半桥栅极驱动芯片中，为防止高侧驱动电路因dVS/dt噪声导致输出有误所使用的噪声消除电路设计。The present invention relates to the field of high-voltage gate drives that are resistant to noise interference, and in particular to a high-voltage half-bridge gate drive chip used in the field of motor drives, in order to prevent high-side drive circuits from output errors due to dV S /dt noise. Noise cancellation circuit design used.

背景技术Background technique

栅极驱动电路在电机驱动、自动化控制、开关电源等领域有着广泛应用，信号传输的可靠性一直是相关产品设计的追求目标。Gate drive circuits are widely used in motor drive, automation control, switching power supply and other fields. The reliability of signal transmission has always been the goal of related product design.

半桥驱动芯片内部电路分为高侧电路和低侧电路。其中高侧栅极驱动电路输入采用双路窄脉冲驱动以减少在高压管处的功耗，双路窄脉冲经电平转换电路和滤波电路后由RS触发器将其还原，还原信号作为输出功率管的驱动信号。低侧电路的信号传输延时与高侧电路信号传输延时相匹配，两侧输出同时作为外部半桥结构拓扑的功率管的输入控制信号。当浮动地低侧功率管截止，高侧功率管导通时，VS被外部高压电源抬升，自举电路使VS维持在高压电平的过程中，VB始终高于VS15V，即电源电压值。由于高侧电路中起电平转换作用的LMOS器件存在寄生电容，当VS电平快速上升时，随之产生的位移电流会对寄生电容充电，并在LDMOS漏极和电源间的电阻上产生压降，导致干扰信号的产生，即dVS/dt噪声。该干扰信号可传递到后级电路导致RS触发器发生意料之外的复位输出，从而影响最终输出结果。传统的方案一般采用脉冲滤波电路，但此方案需要保证作为有效信号的双路窄脉冲不被滤除，滤波能力有限且延时较大。采用该方案难以显著提升芯片的抗dVS/dt噪声能力。The internal circuit of the half-bridge driver chip is divided into high-side circuit and low-side circuit. Among them, the input of the high-side gate drive circuit adopts dual-channel narrow pulse drive to reduce the power consumption at the high-voltage tube. The dual-channel narrow pulse is restored by the RS flip-flop after being passed through the level conversion circuit and filter circuit, and the restored signal is used as the output power. tube drive signal. The signal transmission delay of the low-side circuit matches the signal transmission delay of the high-side circuit, and the outputs on both sides simultaneously serve as the input control signals of the power tube of the external half-bridge structure topology. When the floating ground low-side power transistor is turned off and the high-side power transistor is turned on, VS is raised by the external high-voltage power supply. The bootstrap circuit maintains VS at the high-voltage level. VB is always higher than VS15V, which is the power supply voltage value. Since the LMOS device that plays the role of level conversion in the high-side circuit has parasitic capacitance, when the VS level rises rapidly, the resulting displacement current will charge the parasitic capacitance and generate a voltage on the resistance between the LDMOS drain and the power supply. drop, resulting in the generation of interference signals, that is, dV S /dt noise. This interference signal can be transmitted to the subsequent circuit, causing the RS flip-flop to produce an unexpected reset output, thus affecting the final output result. Traditional solutions generally use pulse filtering circuits, but this solution needs to ensure that the two-way narrow pulses as effective signals are not filtered out, so the filtering capability is limited and the delay is large. It is difficult to significantly improve the chip's anti-dV S /dt noise capability using this solution.

发明内容Contents of the invention

本发明的目的是针对背景技术中提出的问题，提出一种可抗dVS/dt噪声的高侧栅极驱动电路。The purpose of the present invention is to propose a high-side gate drive circuit that is resistant to dV S /dt noise in view of the problems raised in the background art.

本发明解决其的技术问题所采用的技术方案如下：The technical solutions adopted by the present invention to solve the technical problems are as follows:

本发明电路包括高压电平移位电路，电流源电路，RS触发器电路，与非门、反相器和传输门电路、输出驱动级电路。The circuit of the invention includes a high-voltage level shift circuit, a current source circuit, an RS flip-flop circuit, a NAND gate, an inverter and a transmission gate circuit, and an output driver circuit.

如图1所示高压电平移位电路的输入来源于低侧脉冲边缘获取电路(对应于图1中的Pluse Generator电路)产生的双路窄脉冲，其输出作为电流源电路的输入，控制电流源电路是否工作。电流源电路的两路输出信号一方面作为RS触发器的输入，另一方面两路信号经过与非门和非门的逻辑转换后，产生传输门的控制信号。传输门的输入信号为RS触发器的输出信号，其输出信号为后级驱动电路的输入信号，反相器为后级驱动电路的一部分，现有的输出驱动级电路(对应图2中的Driver)通过输出驱动信号控制外部功率管的开启与关断。抗dVS/dt噪声电路包括PMOS管MP1，PMOS管MP2，PMOS管MP3，PMOS管MP4，NMOS管MN1，NMOS管MN2，NMOS管MN3，NMOS管MN4，RS触发器，与非门NAND1，反相器INV1，NMOS管MN5，PMOS管MP5，反相器INV2，反相器INV3。As shown in Figure 1, the input of the high-voltage level shift circuit comes from the dual-channel narrow pulses generated by the low-side pulse edge acquisition circuit (corresponding to the Plus Generator circuit in Figure 1), and its output is used as the input of the current source circuit to control the current. Does the source circuit work? On the one hand, the two output signals of the current source circuit serve as the input of the RS flip-flop. On the other hand, the two signals are converted by the logic of the NAND gate and the NOT gate to generate the control signal of the transmission gate. The input signal of the transmission gate is the output signal of the RS flip-flop, and its output signal is the input signal of the subsequent driver circuit. The inverter is part of the subsequent driver circuit. The existing output driver circuit (corresponding to the Driver in Figure 2 ) controls the turning on and off of the external power tube by outputting the driving signal. The anti-dV S /dt noise circuit includes PMOS tube MP1, PMOS tube MP2, PMOS tube MP3, PMOS tube MP4, NMOS tube MN1, NMOS tube MN2, NMOS tube MN3, NMOS tube MN4, RS flip-flop, NAND gate NAND1, inverter Phaser INV1, NMOS tube MN5, PMOS tube MP5, inverter INV2, inverter INV3.

本发明相较于传统的技术方案，其抗共模噪声能力更强，且在电源电压稳定时，本发明不影响电路的正常工作状况。因为本发明中无需加入额外的滤波电路，电路传输延时大大降低，有效提高信号的传输效率。Compared with traditional technical solutions, the present invention has stronger resistance to common mode noise, and when the power supply voltage is stable, the present invention does not affect the normal working conditions of the circuit. Because there is no need to add additional filter circuits in the present invention, the circuit transmission delay is greatly reduced and the signal transmission efficiency is effectively improved.

附图说明Description of the drawings

图1是高压栅极驱动芯片用作半桥驱动的典型应用示意图。Figure 1 is a schematic diagram of a typical application of a high-voltage gate driver chip used as a half-bridge driver.

图2是本发明可抗dVS/dt噪声的高侧栅极驱动电路的具体结构。Figure 2 is the specific structure of the high-side gate drive circuit that can withstand dV S /dt noise according to the present invention.

图3是本发明没有噪声干扰时的波形图。Figure 3 is a waveform diagram of the present invention without noise interference.

图4是本发明有噪声干扰时的波形图。Figure 4 is a waveform diagram of the present invention when there is noise interference.

图5是传统的高侧栅极驱动电路未滤除噪声干扰时的波形图。Figure 5 is a waveform diagram of a traditional high-side gate drive circuit without filtering out noise interference.

图6是本发明在dVS/dt噪声为85V/ns时的仿真图。Figure 6 is a simulation diagram of the present invention when the dV S /dt noise is 85V/ns.

图7是传统的高侧栅极驱动电路在dVS/dt噪声为50V/ns时的仿真图。Figure 7 is a simulation diagram of a traditional high-side gate drive circuit when the dV S /dt noise is 50V/ns.

具体实施方式Detailed ways

下面结合附图和实施例对本发明作进一步说明。The present invention will be further described below in conjunction with the accompanying drawings and examples.

图1描述了高压栅极驱动芯片用作半桥驱动的典型应用。其中HighSide Region为本发明在高压栅极驱动芯片所处位置，其内部电路如图2所示。本发明电路包括高压电平移位电路，电流源电路，RS触发器电路，与非门、反相器和传输门电路，输出驱动级电路。电流源电路，RS触发器电路，与非门、反相器和传输门电路共同构成本发明的抗干扰作用电路主体，其具体描述如下：Figure 1 depicts a typical application of a high-voltage gate driver chip used as a half-bridge driver. The HighSide Region is the location of the high-voltage gate driver chip of the present invention, and its internal circuit is shown in Figure 2. The circuit of the invention includes a high-voltage level shift circuit, a current source circuit, an RS flip-flop circuit, a NAND gate, an inverter and a transmission gate circuit, and an output driver circuit. The current source circuit, RS flip-flop circuit, NAND gate, inverter and transmission gate circuit together constitute the main body of the anti-interference circuit of the present invention, and its specific description is as follows:

本发明抗dVS/dt噪声的高侧栅极驱动电路，包括第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3、第四PMOS管MP4、第一NMOS管MN1、第二NMOS管MN2、第三NMOS管MN3、第四NMOS管MN4、RS触发器、与非门NAND1、第一反相器INV1、第五NMOS管MN5、第五PMOS管MP5、第二反相器INV2和第三反相器INV3组成；第一PMOS管MP1的栅极接第二PMOS管MP2的栅极，同时接第一LDMOS管LD1的漏极，并且接第一电阻R1的下端和第一齐纳二极管D1的阳极，第一PMOS管MP1的源极接高侧电压电源VB，第一PMOS管MP1的漏极接第一NMOS管MN1的漏极，同时接RS触发器的复位端R，并且接与非门NAND1的其中一个输入端，第二PMOS管MP2的源极接高侧电压电源VB，第二PMOS管MP2的漏极接第三NMOS管MN3的漏极，同时接第三NMOS管MN3的栅极和第四NMOS管MN4的栅极，第三PMOS管MP3的栅极接第四PMOS管MP4的栅极，同时接第二LDMOS管LD2的漏极，并且接第二电阻R2的下端和第二齐纳二极管D2的阳极，第三PMOS管MP3的源极接高侧电压电源VB，第三PMOS管MP3的漏极接第二NMOS管MN2的漏极，同时接第二NMOS管MN2的栅极和第一NMOS管MN1的栅极，第四PMOS管MP4的源极接高侧电压电源VB，第四PMOS管MP4的漏极接第四NMOS管MN4的漏极，同时接RS触发器的置位端S，并且接与非门NAND1的其中一个输入端，第一NMOS管MN1的源极接高侧参考地VS，第二NMOS管MN2的源极接高侧参考地VS，第三NMOS管MN3的源极接高侧参考地VS，第四NMOS管MN4的源极接高侧参考地VS，RS触发器的输出接第五NMOS管MN5的漏极和第五PMOS管MP5的源极，与非门NAND1的输出接第一反相器INV1的输入，同时接第五NMOS管MN5的栅极，第一反相器INV1的输出接第五PMOS管MP5的栅极，第五NMOS管MN5的源极接第五PMOS管MP5的漏极，同时接第二反相器INV2和第三反相器INV3的输入，第二反相器INV2和第三反相器INV3的输出接驱动电路的输入。The high-side gate drive circuit resistant to dV S /dt noise of the present invention includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, and a second NMOS transistor. tube MN2, the third NMOS tube MN3, the fourth NMOS tube MN4, RS flip-flop, NAND gate NAND1, first inverter INV1, fifth NMOS tube MN5, fifth PMOS tube MP5, second inverter INV2 and The third inverter INV3 is composed of: the gate of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2, and is connected to the drain of the first LDMOS tube LD1, and is connected to the lower end of the first resistor R1 and the first zener The anode of the diode D1, the source of the first PMOS transistor MP1 are connected to the high-side voltage power supply VB, the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, and the reset terminal R of the RS flip-flop is connected at the same time. One of the input terminals of the NAND gate NAND1, the source of the second PMOS transistor MP2 is connected to the high-side voltage power supply VB, the drain of the second PMOS transistor MP2 is connected to the drain of the third NMOS transistor MN3, and the third NMOS transistor MN3 is connected at the same time. The gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4, the drain of the second LDMOS transistor LD2, and the lower end of the second resistor R2. and the anode of the second Zener diode D2, the source of the third PMOS transistor MP3 is connected to the high-side voltage power supply VB, the drain of the third PMOS transistor MP3 is connected to the drain of the second NMOS transistor MN2, and at the same time, the second NMOS transistor MN2 is connected. The gate of the first NMOS transistor MN1, the source of the fourth PMOS transistor MP4 is connected to the high-side voltage power supply VB, the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, and the RS trigger is connected at the same time. The set terminal S of the device is connected to one of the input terminals of the NAND gate NAND1. The source of the first NMOS transistor MN1 is connected to the high-side reference ground VS. The source of the second NMOS transistor MN2 is connected to the high-side reference ground VS. The source of the third NMOS transistor MN3 is connected to the high-side reference ground VS, the source of the fourth NMOS transistor MN4 is connected to the high-side reference ground VS, and the output of the RS flip-flop is connected to the drain of the fifth NMOS transistor MN5 and the fifth PMOS transistor MP5. Source, the output of the NAND gate NAND1 is connected to the input of the first inverter INV1, and at the same time connected to the gate of the fifth NMOS transistor MN5. The output of the first inverter INV1 is connected to the gate of the fifth PMOS transistor MP5. The source of the NMOS transistor MN5 is connected to the drain of the fifth PMOS transistor MP5, and is connected to the inputs of the second inverter INV2 and the third inverter INV3. The outputs of the second inverter INV2 and the third inverter INV3 are connected. input to the driver circuit.

图3和图4分别展示了本发明没有噪声干扰时和有噪声干扰时的波形示意图。当高侧信号通过图1中脉冲产生电路后，输出如图3所示的FIN和RIN脉冲信号，两路脉冲信号作为现有高压电平移位电路的输入接到第一LDMOS管LD1和第二LDMOS管LD2的栅极。电路中大部分的动态功耗来源于第一LDMOS管LD1和第二LDMOS管LD2进行高压电瓶转换的过程，脉冲作为输入可有效降低电路功耗。FIN和RIN经第一LDMOS管LD1和第二LDMOS管LD2转换后作为第一PMOS管MP1到第四PMOS管MP4的栅极控制信号，只有在脉冲来临时第一PMOS管MP1到第四PMOS管MP4才会开启，电流镜开始工作，将脉冲信号送到RS触发器和与与非门NAND1输入。与非门NAND1的输出信号本身以及经过第一反相器INV1反相后的信号分别作为第五NMOS管MN5和第五PMOS管MP5的栅极和控制信号。第五NMOS管MN5和第五PMOS管MP5构成传输门电路。电路正常工作时，传输门开启，输出信号HO正常。噪声来临时传输门受与非门的控制将关闭一段时间，使干扰信号大幅衰减，衰减后的干扰信号被第二反相器INV2和第三INV3滤除，输出信号HO正常。Figures 3 and 4 show schematic waveform diagrams of the present invention when there is no noise interference and when there is noise interference respectively. When the high-side signal passes through the pulse generation circuit in Figure 1, the FIN and RIN pulse signals shown in Figure 3 are output. The two pulse signals are connected to the first LDMOS tube LD1 and the first LDMOS tube LD1 as the input of the existing high-voltage level shift circuit. The gate of the second LDMOS transistor LD2. Most of the dynamic power consumption in the circuit comes from the high-voltage battery conversion process of the first LDMOS transistor LD1 and the second LDMOS transistor LD2. Using pulses as input can effectively reduce circuit power consumption. FIN and RIN are converted by the first LDMOS tube LD1 and the second LDMOS tube LD2 as the gate control signals of the first PMOS tube MP1 to the fourth PMOS tube MP4. Only when the pulse comes, the first PMOS tube MP1 to the fourth PMOS tube MP4 will be turned on, the current mirror will start to work, and the pulse signal will be sent to the RS flip-flop and the NAND1 input of the NAND gate. The output signal of the NAND gate NAND1 itself and the signal inverted by the first inverter INV1 serve as the gate and control signals of the fifth NMOS transistor MN5 and the fifth PMOS transistor MP5 respectively. The fifth NMOS transistor MN5 and the fifth PMOS transistor MP5 constitute a transmission gate circuit. When the circuit is working normally, the transmission gate is open and the output signal HO is normal. When noise comes, the transmission gate is controlled by the NAND gate and will be closed for a period of time, which greatly attenuates the interference signal. The attenuated interference signal is filtered out by the second inverter INV2 and the third INV3, and the output signal HO is normal.

图6和图7分别展示了本发明在dVS/dt噪声为85V/ns时的仿真图和传统的高侧栅极驱动电路在dVS/dt噪声为50V/ns时的仿真图。从图中可以看出，传统的高侧栅极驱动电路在dVS/dt噪声为50V/ns时已超出其抗干扰能力，若要进一步提升抗噪声能力，需加大内部滤波器的滤波能力，这将大大增加信号的传输延时。而本发明在dVS/dt噪声高达85V/ns扔可保证输出信号HO正常，且内部无额外滤波器，传输延时较传统方案而言大大降低。Figures 6 and 7 respectively show the simulation diagram of the present invention when the dV S /dt noise is 85V/ns and the simulation diagram of the traditional high-side gate drive circuit when the dV S /dt noise is 50V/ns. It can be seen from the figure that the traditional high-side gate drive circuit has exceeded its anti-interference capability when the dV S /dt noise is 50V/ns. To further improve the anti-noise capability, the filtering capability of the internal filter needs to be increased. , which will greatly increase the signal transmission delay. However, the present invention can ensure that the output signal HO is normal when the dV S /dt noise is as high as 85V/ns, and there is no additional internal filter, so the transmission delay is greatly reduced compared with the traditional solution.

Claims (3)

1.一种可抗dVS/dt噪声的高侧栅极驱动电路，其特征在于，包括高压电平移位电路，电流源电路，RS触发器电路，与非门、反相器和传输门电路、输出驱动级电路；1. A high-side gate drive circuit that is resistant to dV S /dt noise, characterized by including a high-voltage level shift circuit, a current source circuit, an RS flip-flop circuit, a NAND gate, an inverter and a transmission gate Circuit, output driver stage circuit; 高压电平移位电路的输入来源于低侧脉冲边缘获取电路产生的双路窄脉冲，其输出作为电流源电路的输入，控制电流源电路是否工作；电流源电路的两路输出信号一方面作为RS触发器的输入，另一方面两路信号经过与非门和非门的逻辑转换后，产生传输门的控制信号；传输门的输入信号为RS触发器电路的输出信号，其输出信号为输出驱动电路的输入信号，反相器为输出驱动电路的一部分，输出驱动级电路通过输出驱动信号控制外部功率管的开启与关断。The input of the high-voltage level shift circuit comes from the dual narrow pulses generated by the low-side pulse edge acquisition circuit, and its output is used as the input of the current source circuit to control whether the current source circuit works; on the one hand, the two output signals of the current source circuit serve as The input of the RS flip-flop, on the other hand, after the two signals are logically converted by the NAND gate and the NOT gate, the control signal of the transmission gate is generated; the input signal of the transmission gate is the output signal of the RS flip-flop circuit, and its output signal is the output The input signal of the drive circuit, the inverter is part of the output drive circuit, and the output drive stage circuit controls the opening and closing of the external power tube through the output drive signal. 2.根据权利要求1所述的一种可抗dVS/dt噪声的高侧栅极驱动电路，其特征在于，该包括第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3、第四PMOS管MP4、第一NMOS管MN1、第二NMOS管MN2、第三NMOS管MN3、第四NMOS管MN4、RS触发器、与非门NAND1、第一反相器INV1、第五NMOS管MN5、第五PMOS管MP5、第二反相器INV2和第三反相器INV3组成；第一PMOS管MP1的栅极接第二PMOS管MP2的栅极，同时接第一LDMOS管LD1的漏极，并且接第一电阻R1的下端和第一齐纳二极管D1的阳极，第一PMOS管MP1的源极接高侧电压电源VB，第一PMOS管MP1的漏极接第一NMOS管MN1的漏极，同时接RS触发器的复位端R，并且接与非门NAND1的其中一个输入端，第二PMOS管MP2的源极接高侧电压电源VB，第二PMOS管MP2的漏极接第三NMOS管MN3的漏极，同时接第三NMOS管MN3的栅极和第四NMOS管MN4的栅极，第三PMOS管MP3的栅极接第四PMOS管MP4的栅极，同时接第二LDMOS管LD2的漏极，并且接第二电阻R2的下端和第二齐纳二极管D2的阳极，第三PMOS管MP3的源极接高侧电压电源VB，第三PMOS管MP3的漏极接第二NMOS管MN2的漏极，同时接第二NMOS管MN2的栅极和第一NMOS管MN1的栅极，第四PMOS管MP4的源极接高侧电压电源VB，第四PMOS管MP4的漏极接第四NMOS管MN4的漏极，同时接RS触发器的置位端S，并且接与非门NAND1的其中一个输入端，第一NMOS管MN1的源极接高侧参考地VS，第二NMOS管MN2的源极接高侧参考地VS，第三NMOS管MN3的源极接高侧参考地VS，第四NMOS管MN4的源极接高侧参考地VS，RS触发器的输出接第五NMOS管MN5的漏极和第五PMOS管MP5的源极，与非门NAND1的输出接第一反相器INV1的输入，同时接第五NMOS管MN5的栅极，第一反相器INV1的输出接第五PMOS管MP5的栅极，第五NMOS管MN5的源极接第五PMOS管MP5的漏极，同时接第二反相器INV2和第三反相器INV3的输入，第二反相器INV2和第三反相器INV3的输出接驱动电路的输入。2. A high-side gate drive circuit capable of resisting dV S /dt noise according to claim 1, characterized in that it includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, The fourth PMOS tube MP4, the first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3, the fourth NMOS tube MN4, the RS flip-flop, the NAND gate NAND1, the first inverter INV1, the fifth NMOS tube MN5, the fifth PMOS tube MP5, the second inverter INV2 and the third inverter INV3; the gate of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2, and at the same time connected to the drain of the first LDMOS tube LD1 pole, and is connected to the lower end of the first resistor R1 and the anode of the first Zener diode D1, the source of the first PMOS transistor MP1 is connected to the high-side voltage power supply VB, and the drain of the first PMOS transistor MP1 is connected to the first NMOS transistor MN1 The drain is connected to the reset terminal R of the RS flip-flop and one of the input terminals of the NAND gate NAND1. The source of the second PMOS tube MP2 is connected to the high-side voltage power supply VB. The drain of the second PMOS tube MP2 is connected to the third The drains of the three NMOS transistors MN3 are connected to the gate of the third NMOS transistor MN3 and the gate of the fourth NMOS transistor MN4 at the same time. The gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4 and is connected to the gate of the second NMOS transistor MP4. The drain of the LDMOS transistor LD2 is connected to the lower end of the second resistor R2 and the anode of the second Zener diode D2. The source of the third PMOS transistor MP3 is connected to the high-side voltage power supply VB. The drain of the third PMOS transistor MP3 is connected to the third PMOS transistor MP3. The drain of the second NMOS transistor MN2 is connected to the gate of the second NMOS transistor MN2 and the gate of the first NMOS transistor MN1 at the same time. The source of the fourth PMOS transistor MP4 is connected to the high-side voltage power supply VB. The drain of the fourth PMOS transistor MP4 The drain of the fourth NMOS transistor MN4 is connected to the set terminal S of the RS flip-flop and one of the input terminals of the NAND gate NAND1. The source of the first NMOS transistor MN1 is connected to the high-side reference ground VS. The source of the second NMOS transistor MN2 is connected to the high-side reference ground VS, the source of the third NMOS transistor MN3 is connected to the high-side reference ground VS, the source of the fourth NMOS transistor MN4 is connected to the high-side reference ground VS, and the output of the RS flip-flop is connected to the high-side reference ground VS. The drain of the fifth NMOS transistor MN5 and the source of the fifth PMOS transistor MP5, the output of the NAND gate NAND1 is connected to the input of the first inverter INV1, and at the same time connected to the gate of the fifth NMOS transistor MN5, the first inverter The output of INV1 is connected to the gate of the fifth PMOS transistor MP5, the source of the fifth NMOS transistor MN5 is connected to the drain of the fifth PMOS transistor MP5, and simultaneously connected to the inputs of the second inverter INV2 and the third inverter INV3. The outputs of the second inverter INV2 and the third inverter INV3 are connected to the input of the driving circuit. 3.根据权利要求2所述的一种可抗dVS/dt噪声的高侧栅极驱动电路，其特征在于，该高侧信号通过脉冲产生电路后，输出FIN和RIN脉冲信号，两路脉冲信号作为高压电平移位电路的输入接到第一LDMOS管LD1和第二LDMOS管LD2的栅极；FIN和RIN经第一LDMOS管LD1和第二LDMOS管LD2转换后作为第一PMOS管MP1到第四PMOS管MP4的栅极控制信号，只有在脉冲来临时第一PMOS管MP1到第四PMOS管MP4才会开启，电流镜开始工作，将脉冲信号送到RS触发器和与非门NAND1输入；与非门NAND1的输出信号本身以及经过第一反相器INV1反相后的信号分别作为第五NMOS管MN5和第五PMOS管MP5的栅极和控制信号；第五NMOS管MN5和第五PMOS管MP5构成传输门电路，电路正常工作时，传输门开启，输出信号HO正常；噪声来临时传输门受与非门的控制将关闭一段时间，使干扰信号大幅衰减，衰减后的干扰信号被第二反相器INV2和第三INV3滤除，输出信号HO正常。3. A high-side gate drive circuit capable of resisting dV S /dt noise according to claim 2, characterized in that after the high-side signal passes through the pulse generation circuit, it outputs FIN and RIN pulse signals, two-way pulses. The signal is connected to the gates of the first LDMOS transistor LD1 and the second LDMOS transistor LD2 as the input of the high-voltage level shift circuit; FIN and RIN are converted into the first PMOS transistor MP1 after being converted by the first LDMOS transistor LD1 and the second LDMOS transistor LD2. To the gate control signal of the fourth PMOS transistor MP4, only when the pulse comes, the first PMOS transistor MP1 to the fourth PMOS transistor MP4 will be turned on, the current mirror starts to work, and the pulse signal is sent to the RS flip-flop and the NAND gate NAND1 Input; the output signal of the NAND gate NAND1 itself and the signal inverted by the first inverter INV1 serve as the gate and control signals of the fifth NMOS transistor MN5 and the fifth PMOS transistor MP5 respectively; the fifth NMOS transistor MN5 and the fifth PMOS transistor MP5 Five PMOS tubes MP5 form a transmission gate circuit. When the circuit is working normally, the transmission gate is open and the output signal HO is normal. When noise comes, the transmission gate is controlled by the NAND gate and will be closed for a period of time, which greatly attenuates the interference signal. The attenuated interference signal It is filtered out by the second inverter INV2 and the third INV3, and the output signal HO is normal.

CN202310866262.5A 2023-07-14 2023-07-14 A high-side gate drive circuit that is immune to dVS/dt noise Pending CN116827097A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118539903A (en) * 2024-07-24 2024-08-23 上海海栎创科技股份有限公司 Low-delay and driving force controllable input/output circuit and method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118539903A (en) * 2024-07-24 2024-08-23 上海海栎创科技股份有限公司 Low-delay and driving force controllable input/output circuit and method

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