CN117194297A - Interface adaptation circuit, device and method - Google Patents

Detailed Description

The present application has been described in terms of several embodiments, but the description is illustrative and not restrictive, and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the described embodiments. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features and elements of the present application may also be combined with any conventional features or elements to form a unique inventive arrangement as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. It is therefore to be understood that any of the features shown and/or discussed in the present application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

In order to solve the technical problems, the application provides a self-adaptive interface adaptation scheme which automatically matches with an external connection interface according to signals output by the external connection interface, judges that the external connection interface is currently used as a serial port or an Ethernet port, does not need to make any change to the internal serial port or the Ethernet port, and has high formation speed of a corresponding communication channel.

Before the description, for the sake of understanding, the ethernet port and the serial port are described first, and fig. 2 shows a schematic diagram of external pin connection of the ethernet port, where: (a) Fig. 3 shows a schematic diagram of external pin connection of a serial port (typically, an RS232 serial port) in 1000M network port and (b) 10/100M network port, and the external pin connection is an RJ45 interface, but the electrical properties of the external pin connection are different, and the levels of different signals are also different. Specific:

an Ethernet port: (a) The 8 pins of the 1000M network port are connected with 4 pairs of differential signal wires (1/2, 3/6,4/5, 7/8), and are connected to a Physical (PHY) chip after passing through a network transformer, and the signal level on each pin is not more than 1.5V; (b) 2 pairs of differential signal wires (1/2, 3/6) are connected to 8 pins of a 10/100M network port, are connected to a PHY chip after passing through a network transformer, the signal level on each pin is not more than 1.5V, and the pins are suspended 4/5/7/8;

pins 3 and 6 of the serial port are used for transmitting and receiving respectively, pins 4 and 5 are used for grounding signals, the pins 3 and 6 use RS232 level, and the signal level range is-15V to-3V or 3V to 15V.

As can be seen from fig. 2 and 3, the electrical properties of the external leads of the network port and the serial port are not identical, and based on this, the present application proposes an interface adaptation circuit 10, as shown in fig. 4, comprising:

an interface adaptation circuit 10 is connected with an external connection interface 20, wherein the external connection interface 20 can be used as an ethernet port and a serial port, and two distinguishing pins are arranged in a pin structure 21 of the external connection interface 20, and a first voltage range between the two distinguishing pins of the external connection interface 20 as the ethernet port and a second voltage range between the two distinguishing pins of the external connection interface 20 as the serial port are not overlapped; wherein the circuit 10 comprises:

the voltage detection circuit 11 is connected with the two distinguishing pins and is used for detecting a voltage value between the two distinguishing pins and outputting a control signal, wherein the control signal is used for indicating the external connection interface 20 to be used as an Ethernet port or a serial port currently;

specifically, if the voltage value is in the first voltage range, the control signal is used to instruct the external connection interface 20 to be currently used as an ethernet port; if the voltage value is within the second voltage range, the control signal is used to indicate that the external connection interface 20 is currently used as a serial port.

The channel switching circuit 12 is connected with the pin structure 21 and the voltage detection circuit 11 and is used for controlling one of an external network port connection circuit and an external serial port connection circuit to be in a conducting state with the pin structure 21 according to the control signal;

specifically, if the control signal indicates that the external connection interface 20 is currently used as a serial port, the channel switching circuit 12 controls the pin structure to be in a conducting state with an external serial port connection circuit; if the control signal indicates that the external connection interface 20 is currently used as an ethernet port, the channel switching circuit 12 controls the pin structure to be in a conductive state with an external network port connection circuit.

According to the circuit provided by the embodiment of the application, the circuit is automatically matched with the external connection interface 20 according to the voltage value between two different pins in the external connection interface 20, the external connection interface 20 is judged to be currently used as a serial port or an Ethernet port, and the external connection interface and a corresponding external circuit are controlled to be in a conducting state according to the judging result, so that any change on the internal serial port or the Ethernet port is not required.

It should be noted that the pair of external connection interfaces may be any interface that satisfies signal transmission conditions of the serial port and the ethernet port and has the above-mentioned differential pins. The type of the interface is not limited, and the number of pins may be less than 8 or more than 8 according to the type of the interface.

The following describes a circuit provided by an embodiment of the present application:

when the external connection interface 20 is used as a serial port, one of the two differential pins is grounded, and the other differential pin is used for signal transmission of a communication protocol of the serial port;

in the external connection interface 20, as an ethernet port, one of the two differential pins is used for signal transmission, and the other differential pin is suspended or used for signal transmission of a communication protocol of the ethernet port.

Because of the difference in signal levels between the serial port and the ethernet interface, the first voltage range between the two differential pins of the external connection interface 20 that is the ethernet port does not overlap with the second voltage range between the two differential pins of the external connection interface 20 that is the serial port.

Fig. 5 is a schematic diagram of the circuit 10 shown in fig. 4 applied to an RJ45 interface. As shown in fig. 5, the external connection interface 20 is an RJ45 interface, and the two different pins are the 5 th pin and the 6 th pin of the RJ45 interface. The type of signal currently accessed by the RJ45 interface is determined by the voltage between pin5 and pin6 of the RJ45 interface. Specifically, when the RJ45 interface is connected with a serial port, because the PIN5 is grounded and the PIN6 uses the RS232 level, the signal level range between the PIN5 and the PIN6 is-15V to-3V or 3V to 15V; when the RJ45 interface is connected to a serial port, the signals between the PIN5 and the PIN6 are not in the same differential signal pair, so the signals between the two are essentially invalid signals, and the highest signal level does not exceed 1.5V for each PIN, so the voltage difference between the PIN5 and the PIN6 does not exceed 3V at maximum. Therefore, when the voltage between the PIN5 and the PIN6 is more than 3V, the type of the signal which is accessed by the RJ45 interface at present is determined to be a serial port; otherwise, it is considered as an Ethernet port.

Fig. 6 is a schematic diagram of the structure of the voltage detection circuit 11 in the circuit 10 shown in fig. 4. As shown in fig. 6, the voltage detection circuit 11 includes a bidirectional diode D1, an optocoupler U1, and a first pull-up resistor R1, where:

the negative electrode of the bidirectional diode D1 is connected with a distinguishing pin, and the positive electrode of the bidirectional diode D1 is connected with the positive input end of the optocoupler U1;

the negative input end of the optocoupler U1 is connected with another distinguishing pin, the positive output end is the output end of the voltage detection circuit 11, the negative input end is connected with a first power supply V1 through a first pull-up resistor R1, the output control signal is connected with the control end of the channel switching circuit 12, the negative output end is connected with the ground GND,

the turn-on voltage of the bidirectional diode D1 is greater than the maximum value in the first voltage range and less than or equal to the minimum value in the second voltage range.

Specifically, when the external connection interface 20 is used as a serial port, since the voltage value between the two differential pins is greater than or equal to the turn-on voltage of the bidirectional diode D1, the light emitting diode of the optocoupler U1 emits light, the output end is turned on, the positive output end is grounded, and a low-level control signal is output, and the control signal indicates that the external connection interface 20 is currently used as the serial port;

when the external connection interface 20 is used as a network port, since the voltage value between the two differential pins is smaller than the turning voltage of the bidirectional diode D1, at this time, the light emitting diode of the optocoupler U1 does not emit light, the output end is disconnected, the pin 4 of the optocoupler U1 is at a high level, i.e. outputs a control signal at a high level, and the control signal indicates that the external connection interface 20 is currently used as an ethernet port.

When the external connection interface 20 is an RJ45 interface, the breakover voltage of the bidirectional diode D1 is 3V, wherein the negative electrode of the bidirectional diode D1 is connected with the 6 th pin of the RJ45 interface, and the negative input end of the optocoupler U1 is connected with the 5 th pin of the RJ45 interface.

The operating principle of the voltage detection circuit 11 is as follows:

when the RJ45 interface is used as a serial port, because the PIN5 is grounded and the PIN6 uses the RS232 level, the signal level range between the PIN5 and the PIN6 is-15V to-3V or 3V to 15V and is necessarily larger than the turning voltage of the bidirectional diode D1, so that the light-emitting diode of the optical coupler U1 emits light, the output end is conducted, the positive output end is grounded and outputs a low-level control signal, and at the moment, the interface connection unit A1 and the serial port connection unit B2 form electric connection;

when the RJ45 interface is used as an ethernet port, since the PIN5 and the PIN6 belong to different differential signal pairs, the signals between the two are essentially invalid interference signals, and since for each PIN, the highest signal level does not exceed 1.5V, therefore, the voltage difference between the PIN5 and the PIN6 does not exceed 3V at maximum, the voltage is smaller than the turning voltage of the bidirectional diode D1, at this time, the light emitting diode of the optocoupler U1 does not emit light, the output end is disconnected, and the PIN 4 is at a high level, namely: and outputting a high-level control signal, wherein at the moment, an electric connection is formed between the interface connection unit A1 and the network port connection unit B1.

Therefore, the voltage detection circuit 11 designed by the specific circuit can directly utilize the external interface signal to realize the connection of different channels inside the channel switching circuit 12 through hardware judgment, thereby completing the automatic side detection and judgment when different types of interfaces are accessed and realizing the automatic access.

Fig. 7 is a schematic diagram of the channel switching circuit 12 in the circuit 10 shown in fig. 4. As shown in fig. 7, the channel switching circuit 12 includes an interface connection unit, a serial port connection unit, and a network port connection unit; wherein:

the interface connection unit A1 is provided with a first connection end, a second connection end and a control end, wherein the first connection end is connected with the pin structure, the second connection end is switchably connected with the serial port connection unit and the network port connection unit, and the control end is used for receiving the control signal, and the interface connection unit A1 is used for controlling one of the serial port connection unit and the network port connection unit to be in a conducting state with the second connection end according to the control signal;

the serial port connection unit B1 is configured to connect with an external serial port connection circuit, which may be a serial port driving chip, for example, an RS232 driving chip;

the network port connection unit B2 is configured to be connected to an external network port connection circuit, which is typically electrically connected to the PHY network transformer, so as to be used as a network port.

The network port connection circuit is connected with the channel switching circuit 12 according to the external connection line sequence of the network port in the prior art, the serial port connection circuit is connected with the channel switching circuit 12 according to the external connection line sequence of the serial port in the prior art, and the channel switching circuit 12 is respectively connected with the network port connection circuit and the external connection line sequence of the serial port connection circuit, wherein the connection ends of the external connection line sequence and the serial port connection circuit are corresponding port types.

In other words, for the network port connection circuit and the serial port connection circuit, the channel switching circuit 12 corresponds to an external connection structure of the external connection interface, which is consistent with the connection line sequence of the channel switching circuit 12 and the connection line sequence of the corresponding external connection interface type (network port or serial port), and the channel switching circuit 12 is also provided with a network port connection unit B1 and a serial port connection unit B1 connected with the two connection circuits, respectively, and in addition, the channel switching circuit 12 is also provided with an interface connection unit A1 corresponding to the line sequence of the pin end of the external connection interface 20.

Fig. 8 is another schematic diagram of the circuit 10 shown in fig. 4. As shown in fig. 8, the circuit 10 further includes:

one end of the delay circuit 13 is connected with the voltage detection circuit 11, the other end of the delay circuit is connected with the channel switching circuit and is used for self-receiving the control signal for timing, and outputting a switching signal corresponding to the control signal after the timing reaches a preset duration, wherein the switching signal is used for indicating switching between a serial port and an Ethernet port;

the channel switching circuit 12 is configured to control, according to the switching signal, when one of the external network port connection circuit and the external serial port connection circuit is in a conductive state with the pin structure, the other of the external network port connection circuit and the external serial port connection circuit to be in a conductive state with the pin structure.

After the delay circuit 13 is added, when the external signal connected with the external connection interface 20 is replaced by the network port and the serial port, the channel switching with the current interface connection circuit is not immediately performed, a period of delay is needed, the channel switching is not immediately performed even if the switching control signal received by the channel switching circuit 12 is changed in the delay process, the situation that the external interface of the RJ45 connector is changed due to the change of the pin level caused by external interference and the like can be avoided, the error switching of the internal connection circuit is triggered by the channel switching circuit 12 due to the misjudgment of the change of the interface type, and even the frequent error switching is ensured, so that the accuracy and the stability of signal receiving are ensured.

Fig. 9 is a schematic diagram of the delay circuit 13 in the circuit 10 shown in fig. 8. As shown in fig. 9, the delay circuit 13 includes a second diode D2, a second resistor R2, a capacitor C1, a third resistor R3, a fourth resistor R4, and a field effect transistor Q1, wherein:

the cathode of the second diode D2 is connected with the output end of the voltage detection circuit, the anode of the second diode D2 is connected with the grid G of the field effect transistor Q1 through a second resistor R2, and the grid G of the field effect transistor Q1 is also connected with the ground through the capacitor C1 and is connected with a second power supply V2 through a fourth resistor R4; the drain D of the fet Q1 is an output end of the delay circuit 13, and is connected to the second power source V2 through a third resistor R3, and the source S of the fet Q1 is connected to the ground GND.

The channel switching circuit 12 performs the operation according to the output signal of the voltage detection circuit 11 as follows:

(1) In the initial state, when the external connection interface 20 is used as a serial port, since the control signal output by the voltage detection circuit 11 is at a high level, the second diode D2 is turned off reversely, at this time, the second power supply V2 charges the capacitor C1, the gate G of the field effect transistor Q1 is at a high level, and the gate G and the source S are turned on, so that the drain D and the source S are turned on, and at this time, the drain D outputs a low level signal, that is, the output signal of the delay circuit 13 is a low level signal;

(2) In the initial state, when the external connection interface 20 is used as an ethernet port, since the control signal output by the voltage detection circuit 11 is at a low level, the gate G of the field effect transistor Q1 is at a low level, and the gate G and the source S are disconnected, so that the drain D and the source S are not connected, and at this time, the drain D outputs a high level signal, that is, the output signal of the delay circuit 13 is a high level signal;

(3) When the interface connected with the RJ45 interface is switched from the serial port to the Ethernet port, although the control signal output by the voltage detection circuit 11 is changed from high level to low level, the capacitor C1 is discharged outwards at the moment, so that the grid G of the field effect tube can also maintain high level for a period of time, and the current serial port connection state can also be maintained in a delayed manner; that is, before the capacitor C1 is discharged, the interface connection unit A1 and the serial port connection unit B2 still maintain electrical connection;

(4) When the interface connected with the RJ45 interface is switched from the Ethernet interface to the serial port, although the control signal output by the voltage detection circuit 11 is changed from low level to high level, the capacitor C1 is required to be charged at the moment, and in the process, the delay circuit 13 still outputs a low level signal until the charging is completed, so that the current network port connection state can be maintained in a delayed manner; that is, before the capacitor C1 is charged, the interface connection unit A1 and the network port connection unit B1 remain electrically connected;

the charging and discharging time of the capacitor C1 mentioned in the above operation is determined by a person skilled in the art selecting the capacitor C1 and the fourth resistor R4 with different values according to the system setting requirements, and in general, the charging time of the capacitor C1 is longer than the discharging time in the same RC delay circuit 13.

Therefore, after the delay circuit 13 is added, when the external connection interface 20 is replaced by the network port and the serial port, the channel switching is not immediately performed, and a period of delay is required, and even if the control signal received by the channel switching circuit 12 is changed in the delay process, the channel switching is not immediately performed, so that the error operation switching and frequent error operation switching which are possibly caused by the external interference to the external connection interface 20 are avoided, and the accuracy and the stability of signal receiving are ensured.

Fig. 10 is a schematic structural diagram of an interface adapting device 100 according to an embodiment of the present application. As shown in fig. 10, the interface adaptation device 100 includes an interface adaptation circuit 10 and an external connection port 20.

According to the device provided by the embodiment of the application, the device is automatically matched with the external connection interface 20 according to the voltage value between two different pins in the external connection interface 20, the external connection interface 20 is judged to be currently used as a serial port or an Ethernet port, and the external connection interface and a corresponding external circuit are controlled to be in a conducting state according to the judging result, so that any change on the internal serial port or the Ethernet port is not required.

Fig. 11 is a schematic flow chart of an interface adaptation method according to an embodiment of the present application. As shown in fig. 11, the method includes:

step 1101, detecting a voltage value between two different pins in a pin structure of an external connection interface, wherein the external connection interface can be used as an ethernet port and a serial port, and a first voltage range between the two different pins of the external connection interface serving as the ethernet port is not overlapped with a second voltage range between the two different pins in the external connection interface serving as the serial port;

step 1102, outputting a control signal according to the obtained voltage value, wherein the control signal is used for indicating that the external connection interface is currently used as an Ethernet port or a serial port;

and step 1103, controlling one of an external network port connection circuit and an external serial port connection circuit to be in a conducting state with the pin structure according to the control signal.

In an exemplary embodiment, the outputting a control signal according to the obtained voltage value includes:

if the voltage value is in the first voltage range, the control signal is used for indicating that the external connection interface is currently used as an Ethernet port;

and if the voltage value is in the second voltage range, the control signal is used for indicating that the external connection interface is currently used as a serial port.

In an exemplary embodiment, the controlling, according to the control signal, a connection state between one of an external network port connection circuit and an external serial port connection circuit and the pin structure includes:

after receiving the control signal, starting timing operation;

outputting a switching signal corresponding to the control signal after the time length obtained by timing operation reaches a preset time length, wherein the switching signal is used for indicating to switch between a serial port and an Ethernet port;

when one of the external Ethernet port connection circuit and the external serial port connection circuit is in a conducting state with the pin structure, the other of the external network port connection circuit and the external serial port connection circuit is controlled to be in a conducting state with the pin structure according to the switching signal.

According to the method provided by the embodiment of the application, the external connection interface is automatically matched with the external connection interface according to the voltage value between the two different pins in the external connection interface, the external connection interface is judged to be currently used as a serial port or an Ethernet port, and the external connection interface is controlled to be in a conducting state with a corresponding external circuit according to the judging result, so that any change is not required to be made to the internal serial port or the Ethernet port.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.