CN117310273A - Power consumption data acquisition method for AI (advanced technology attachment) accelerator card and data acquisition card - Google Patents

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

Example 1

FIG. 1 is a flow chart of a power consumption data collection method in an embodiment, referring to FIG. 1, the method includes:

s101, identifying a communication differential voltage signal end, a communication differential current signal end, a functional differential voltage signal end, a functional differential current signal end, a bus differential current signal end and a core power differential voltage signal end.

In this embodiment, the communication differential voltage signal terminal, the communication differential current signal terminal, the functional differential voltage signal terminal, the functional differential current signal terminal, the bus differential current signal terminal, and the core power differential voltage signal terminal are manually set.

In this embodiment, each signal terminal may include multiple differential signal terminal pairs, and for each signal terminal, when data acquisition is performed on one AI accelerator card, one or more differential signal terminal pairs are used by the AI accelerator card, and when data acquisition is performed on different AI accelerator cards, the number of differential signal terminal pairs used by different AI accelerator cards may be different.

In this embodiment, the signal collection interface is configured with the communication differential voltage signal terminal, the communication differential current signal terminal, the functional differential voltage signal terminal, the functional differential current signal terminal, the bus differential current signal terminal, and the core power differential voltage signal terminal.

In this embodiment, for each signal terminal, the number of differential signal terminal pairs correspondingly included is related to the total number of pins included in the signal acquisition interface and the proposed AI acceleration card adapted to the signal acquisition interface.

For example, taking a core power supply differential voltage signal end as an example, if the first AI acceleration card outputs two paths of core power supply differential voltage signals on the premise that the number of pins of the signal acquisition interface is sufficient, the second AI acceleration card outputs one path of core power supply differential voltage signals;

the core supply differential voltage signal terminals may include VDD1_vsns_ P, VDD1_vsns_ N, VDD2_vsns_ P, VDD2_vsns_n;

wherein VDD1 VSNS P, VDD VSNS N is one set of core power differential signal terminal pairs and VDD2 VSNS P, VDD VSNS N is another core power differential signal terminal pair.

In this embodiment, the signal acquisition interface is configured to be connected to the AI acceleration card to be tested, and when it is identified that data acquisition is performed on the first AI acceleration card, the two core power supply differential signal terminal pairs may be both placed in a use state;

Upon identifying the data acquisition for the second AI accelerator card, the one set of core power differential signal terminal pairs may be placed in an active state and the other set placed in an inactive state.

In the scheme, at least the communication part power consumption data, the chip function part power consumption data and the power supply part power consumption data of the AI accelerator card are acquired;

correspondingly, the set signal acquisition interface at least comprises a communication differential voltage signal end, a communication differential current signal end, a functional differential voltage signal end, a functional differential current signal end, a bus differential current signal end and a core power supply differential voltage signal end.

In this embodiment, the number of signal terminal pairs included in each signal terminal may be determined according to the number of voltage domains or power domains divided by the AI-accelerator card, for example;

for example, the number of terminal pairs included in the communication differential voltage signal terminal or the communication differential current signal terminal may be set to be the same as the number of first power domains, and the number of terminal pairs included in the core power differential voltage signal terminal may be set to be the same as the number of first voltage domains.

S102, acquiring a communication differential voltage signal, a functional differential voltage signal and a core power supply differential voltage signal through a communication differential voltage signal end, a functional differential voltage signal end and a core power supply differential voltage signal end respectively.

S103, obtaining a communication differential current signal, a function differential current signal and a bus differential current signal through the communication differential current signal end, the function differential current signal end and the bus differential current signal end respectively.

S104, carrying out first-class signal processing on the communication differential voltage signal and the communication differential current signal, and classifying the result into a low-voltage differential signal group.

In the embodiment, the first type of signal processing is respectively carried out on the communication differential voltage signal and the communication differential current signal to obtain a Low-voltage differential signal (LVDS, low-Voltage Differential Signaling);

the low voltage differential signal is stored in a low voltage differential signal group.

S105, performing second-class signal processing on the functional differential voltage signal, the core power supply differential voltage signal, the functional differential current signal and the bus differential current signal, and classifying the result into a digital differential signal group.

In the embodiment, the second type of signal processing is respectively carried out on the functional differential voltage signal, the core power differential voltage signal, the functional differential current signal and the bus differential current signal to obtain a digital signal;

The digital signals are stored in a digital differential signal set.

In this embodiment, different signal processing methods are used for different differential signals based on different requirements for sampling rate, resolution, output data rate and power consumption when different differential signals are used.

In combination with step S104 and step S105, in this embodiment, different data processing chips may be used to implement the above-mentioned first type signal processing and second type signal processing, respectively;

for example, LTC2145 may be used to implement a first type of signal processing (output LVDS signals) on the communication differential voltage signals, communication differential current signals;

and performing second-type signal processing (outputting digital IO signals) on the functional differential voltage signal, the core power supply differential voltage signal, the functional differential current signal and the bus differential current signal by adopting the AD 7768.

S106, storing and transmitting signals in the low-voltage differential signal group and the digital differential signal group.

For example, in this embodiment, signals in the low voltage differential signal group and the digital differential signal group may be sent to a data processing terminal (for example, cloud, web GUI, etc.).

In this embodiment, the data processing terminal is configured to analyze signals in the low-voltage differential signal group and/or the digital differential signal group, so as to determine power consumption of the AI accelerator card to be tested.

The embodiment provides a data acquisition method for an AI board, in the method, a differential voltage signal end and a differential current signal end are defined and are respectively used for acquiring differential voltage signals and differential current signals, the power consumption data acquisition of various AI acceleration boards can be realized based on a set of signal end definition modes by the flexible definition modes of the differential voltage signal end and the differential current signal end, the design cost when the various AI acceleration boards need to be tested is remarkably reduced, the expandability and the compatibility of the test method are strong, in addition, the corresponding differential signals are processed by adopting a proper signal processing mode aiming at each acquired differential signal, the test process can be optimized, the subsequent data display, the storage and the like are facilitated, and meanwhile, the data acquisition of long-time dimension can be supported.

Based on the scheme shown in fig. 1, in one possible embodiment, after obtaining the communication differential voltage signal, the functional differential voltage signal, and the core power differential voltage signal, the method further includes:

and carrying out signal preprocessing on the communication differential voltage signal, the functional differential voltage signal and the core power supply differential voltage signal, and respectively recording the preprocessed signals as a first signal, a second signal and a third signal.

The method further comprises the steps of after obtaining the communication differential current signal, the function differential current signal and the bus differential current signal:

and carrying out signal preprocessing on the communication differential current signal, the functional differential current signal and the bus differential current signal, and respectively marking the preprocessed signals as a fourth signal, a fifth signal and a sixth signal.

In this scheme, the preprocessing modes of the voltage differential signal and the current differential signal may be the same or different, and the preprocessing may be a signal method, anti-aliasing, and the like.

In the scheme, first analog-to-digital conversion is carried out on the first signal and the fourth signal, and the result is classified into a low-voltage differential signal group;

and performing second-type analog-to-digital conversion on the second signal, the third signal, the fifth signal and the sixth signal, and classifying the result into a digital differential signal group.

In this scheme, different data processing chips may be used to perform corresponding signal preprocessing on the voltage differential signal and the current differential signal respectively;

for example, LTC6373 may be used to perform signal preprocessing on the communication differential voltage signal, the functional differential voltage signal, and the core power differential voltage signal;

the communication differential current signal, the functional differential current signal, and the bus differential current signal may be signal-preprocessed using ADA4807 and/or AD 8421.

In addition to the scheme of preprocessing the communication differential current signal, the functional differential current signal and the bus differential current signal, the preprocessing of the differential current signal further comprises the following steps:

dividing the communication differential current signal, the functional differential current signal and the bus differential current signal into a first signal group or a second signal group according to the signal voltage;

and respectively preprocessing signals in the first signal group and the second signal group.

Illustratively, in this scheme, the grouping of the differential current signals described above may be implemented using a Multiplexer (MUX);

correspondingly, at least two data processing chips for preprocessing the differential current signals are configured;

for example, ADA4807 may be configured to implement preprocessing of differential current signals in the first signal group, and AD8421 may be configured to implement preprocessing of differential current signals in the second signal group.

In this embodiment, the specific strategy for dividing the specified signal into the first signal group or the second signal group is not limited, and may be freely set according to the design requirement, for example, the above-mentioned dividing strategy may be determined according to the voltage of the collected signal.

On the basis of the scheme of carrying out signal preprocessing on the differential voltage signal and the differential current signal, in one embodiment, the method comprises the following steps:

differential mode suppression, common mode suppression and full-scale input range matching are performed on the communication differential voltage signal, the functional differential voltage signal, the core power differential voltage signal, the communication differential current signal, the functional differential current signal and the bus differential current signal.

In this embodiment, the specific implementation manner of the differential mode suppression and the common mode suppression is not limited, and for example, the differential mode suppression and the common mode suppression may be implemented by a differential mode suppression circuit, a common mode suppression circuit, or the like, or the differential mode and the common mode may be implemented based on a differential mode and common mode suppression function of a chip such as an instrumentation amplifier.

In this embodiment, full-scale input range matching specifically refers to determining a full-scale input range of a specified ADC chip (e.g., LTC2145, AD 7768) when the adopted reference voltages are different;

the manner of determining the full-scale input range is the same as that of the prior art, and the specific details are not described in detail.

On the basis of carrying out a signal preprocessing scheme on the differential voltage signals and the differential current signals, in one implementation scheme, a pair of communication differential voltage signals, functional differential voltage signals and core power supply differential voltage signals are sequentially selected for carrying out signal preprocessing;

And sequentially selecting one pair of communication differential current signals, functional differential current signals and bus differential current signals for signal preprocessing.

For example, in the present solution, the preprocessing of sequentially selecting a pair of differential voltage signals may be implemented based on a multiplexer, and the preprocessing of sequentially selecting a pair of differential current signals may be implemented based on a multiplexer.

Based on the scheme shown in fig. 1, in one possible embodiment, transmitting the low voltage differential signal group, the digital differential signal group includes:

identifying a first communication link and a second communication link;

the low voltage differential signal group, the digital differential signal group are transmitted over a first communication link, and the low voltage differential signal group, the digital differential signal group are transmitted over a second communication link.

In the scheme, two communication links are adopted to transmit signals in a low-voltage differential signal and a digital differential signal group;

wherein the communication principles corresponding to the first communication link and the second communication link are different, for example, the first communication link may be based on bus communication, and the second communication link may be based on ethernet communication.

Further, when the low voltage differential signal group and the digital differential signal group are transmitted over the first communication link and the second communication link, in one embodiment, the first communication link includes: a serial communication link; the second communication link includes: a network communication link.

Illustratively, in this scenario, the serial communication link may be a USB-based communication link, etc., and the network communication link may be an ethernet-based communication link.

Based on the scheme shown in fig. 1, in one possible embodiment, the functional differential voltage signal terminal includes: the chip differential voltage signal end, the auxiliary power differential voltage signal end and the data processing differential voltage signal end;

the functional differential current signal terminal comprises: the chip differential current signal end, the auxiliary power differential current signal end and the data processing differential current signal end.

The specific types of the functional differential voltage signal end and the functional differential current signal end can be determined according to the types of differential signals which can be output by the AI accelerator card to be tested;

the chip differential voltage signal terminals are used for collecting differential voltage signals of the VDD_SOC voltage domains of the AI accelerator card, wherein a plurality of groups of chip differential voltage signal terminals can be configured, and a group of chip differential voltage signal terminals are configured for collecting differential voltage signals of a designated VDD_SOC voltage domain;

the chip differential current signal terminals are used for collecting differential current signals of the VDD_SOC voltage domains of the AI accelerator card, wherein a plurality of groups of signal differential current signal terminals can be configured, and a group of chip differential current signal terminals are configured for collecting differential current signals of a designated VDD_SOC voltage domain;

The auxiliary power supply differential voltage signal terminals are used for collecting differential voltage signals of the VDD_1V8 voltage domains of the AI accelerator card, wherein a plurality of groups of auxiliary differential voltage signal terminals can be configured, and a group of auxiliary differential voltage signal terminals are configured for collecting differential voltage signals of one VDD_1V8 voltage domain;

the auxiliary power supply differential current signal end is used for collecting differential current signals of a VDD_1V8voltage domain of the AI accelerator card, wherein a plurality of groups of auxiliary differential current signal ends can be configured, and a group of auxiliary differential current signal ends are configured for collecting differential current signals of a designated VDD_1V8voltage domain;

the data processing differential voltage signal terminals are used for acquiring differential voltage signals of COREs (COREs) of the AI accelerator card, wherein a plurality of groups of data processing differential voltage signal terminals can be configured, and a group of data processing differential voltage signal terminals are configured for acquiring differential voltage signals of a designated CORE;

the data processing differential current signal terminals are used for collecting differential current signals of cores of the AI accelerator card, wherein a plurality of groups of data processing differential current signal terminals can be configured, and a group of data processing differential current signal terminals are configured for collecting differential current signals of a designated core.

In this embodiment, the schemes corresponding to any one of the foregoing power consumption data collection methods may be freely arranged and combined, and fig. 2 is a flowchart of another power consumption data collection method in this embodiment, and referring to fig. 2, for example, in one possible implementation, the power consumption data collection method includes:

S201, identifying a communication differential voltage signal end, a communication differential current signal end, a functional differential voltage signal end, a functional differential current signal end, a bus differential current signal end and a core power differential voltage signal end.

Fig. 3 is a schematic diagram of a power consumption data flow in an embodiment, referring to fig. 3, in this embodiment, a signal acquisition interface is set to be connected with an AI accelerator card (to be tested), and designated differential pin pairs configured to manually configure the signal acquisition interface are a communication differential voltage signal end, a communication differential current signal end, a functional differential voltage signal end, a functional differential current signal end, a bus differential current signal end, and a core power differential voltage signal end.

In the scheme, after the FGPA recognizes that the signal acquisition interface is connected with the AI acceleration card, the FPGA finishes recognition of each signal end through definition of a preset pin.

For example, in the present solution, for one AI accelerator card, different functional areas inside the AI accelerator card may be divided into different power domains;

for example, the communication bus may be divided into a power domain, each core may be divided into a power domain, a cache tile may be divided into a power domain, etc.

In this scheme, set up function difference voltage signal end specifically includes: the chip differential voltage signal end, the auxiliary power differential voltage signal end and the data processing differential voltage signal end;

The set function differential current signal end comprises: the chip differential current signal end, the auxiliary power differential current signal end and the data processing differential current signal end.

In the scheme, a communication differential voltage signal end and a communication differential current signal end are set and used for correspondingly acquiring differential voltage signals and differential current signals of a first power domain;

the chip differential voltage signal end and the chip differential current signal end are used for correspondingly acquiring differential voltage signals and differential current signals of the second power domain;

the auxiliary power supply differential voltage signal end and the auxiliary power supply differential current signal end are used for correspondingly acquiring differential voltage signals and differential current signals of the third power supply domain;

the data processing differential voltage signal end and the data processing differential current signal end are used for correspondingly acquiring differential voltage signals and differential current signals of the fourth power domain;

the bus differential current signal end is used for correspondingly acquiring differential voltage signals and differential current signals of a fifth power domain;

the core power supply differential voltage signal end is used for correspondingly acquiring differential voltage signals and differential current signals of the sixth power supply domain.

In this solution, an AI accelerator card may include a plurality of power domains of the same type, and correspondingly, at least a plurality of groups of differential power signal terminals and/or differential circuit signal terminals with the same number of the power domains of the same type are configured on the signal acquisition interface.

S202, acquiring a communication differential voltage signal, a functional differential voltage signal and a core power supply differential voltage signal through a communication differential voltage signal end, a functional differential voltage signal end and a core power supply differential voltage signal end respectively.

S203, acquiring a communication differential current signal, a function differential current signal and a bus differential current signal through the communication differential current signal end, the function differential current signal end and the bus differential current signal end respectively.

Referring to fig. 3, in the present embodiment, differential mode suppression and/or common mode suppression is performed on the differential voltage signal and the differential current signal in S202 and S203, respectively, after the differential voltage signal and the differential current signal are acquired.

S204, carrying out signal preprocessing on the communication differential voltage signal, the functional differential voltage signal and the core power supply differential voltage signal, and respectively marking the preprocessed signals as a first signal, a second signal and a third signal.

In this scheme, carry out signal preprocessing to communication differential voltage signal, function differential voltage signal and core power differential voltage signal and include: and carrying out operational amplification on each differential voltage signal.

S205, dividing the communication differential current signals, the functional differential current signals and the bus differential current signals into a first signal group or a second signal group according to the signal voltage.

In this embodiment, the signal voltages in the communication differential current signal, the functional differential current signal, and the bus differential current signal are divided into the first signal group or the second signal group according to the magnitude of the signal voltage (amplitude), and the rest is divided into the rest of the other signal groups.

S206, respectively preprocessing signals in the first signal group and the second signal group, and respectively marking the preprocessed signals as a fourth signal, a fifth signal and a sixth signal.

In this scheme, carry out signal preprocessing to the signal in first signal group, the second signal group includes: and carrying out operational amplification on each differential current signal.

In this embodiment, according to the magnitude of the amplitude of the signal included in the first signal group, an operational amplifier with matched performance is selected to amplify the signal, for example, an instrument operational amplifier is used to amplify the signal corresponding to the signal;

and according to the amplitude of the signals contained in the second signal group, selecting the operational amplifier with the performance to amplify the signals, for example, adopting a rail-to-rail operational amplifier to amplify the signals of the corresponding signals.

In this embodiment, a signal generated by performing operational amplification on the communication differential current signal is set as a fourth signal.

S207, performing first-class analog-to-digital conversion on the first signal and the fourth signal, and classifying the result into a low-voltage differential signal group.

S208, performing second-type analog-to-digital conversion on the second signal, the third signal, the fifth signal and the sixth signal, and classifying the result into a digital differential signal group.

In this scheme, the analog-to-digital conversion is divided into a first analog-to-digital conversion type and a second analog-to-digital conversion type according to the different types of the output results in combination with steps S207 to S208.

In the scheme, the type of a result of performing first-type analog-to-digital conversion on the first signal and the fourth signal is set as a Low Voltage Differential Signal (LVDS);

the type of the result of the second type analog-to-digital conversion output of the second signal, the third signal, the fifth signal and the sixth signal is set to be a 1.8V digital I/O signal.

In the scheme, the first type analog-to-digital conversion and the second type analog-to-digital conversion of the corresponding signals are realized by adopting the corresponding type ADC chips.

S209, transmitting the low-voltage differential signal group and the digital differential signal group through a serial port communication link, and transmitting the low-voltage differential signal group and the digital differential signal group through a network communication link.

In the scheme, signals in the low-voltage differential signal group and the digital differential signal group are finally sent to the cloud for storage or analysis, so that the power consumption of the AI board card is determined.

Example two

Fig. 4 is a block diagram of a data acquisition card in an embodiment, and referring to fig. 4, the data acquisition card includes a signal acquisition interface 100 and a control unit;

the signal acquisition interface 100 is configured and compatible with at least one group of communication differential voltage signal terminals, communication differential current signal terminals, functional differential voltage signal terminals, functional differential current signal terminals, bus differential current signal terminals and core power differential voltage signal terminals;

the control unit comprises a first acquisition module 201, a second acquisition module 202, a control module 203, a storage module 204 and a communication module 205.

In this embodiment, the specific form of the signal acquisition interface 100 is not limited, and it may be designed or a feasible interface in the prior art according to the needs, where the signal acquisition interface 100 should at least meet the following requirements:

the signal acquisition interface is a high-speed differential connector, so that the loss is small, the extra attenuation of the acquired voltage and current (differential) signals on a transmission channel is avoided, the problems of signal integrity and the like are avoided, and larger errors are generated in the transient parameter sampling test result;

the number of the high-speed differential (pin) pairs is enough to cover the total voltage and current acquisition pin number requirements of SKU products with different forms as much as possible, and a certain number of redundant pins are reserved at the same time, and a small number of sideband (sideband) signals are used for necessary control and management of the test process;

The volume of the signal acquisition interface should be as small as possible, so that the layout circuit of the Debug circuit occupies more PCB space when the signal acquisition interface is integrated on a PCB, and the layout wiring of the functional module of the AI acceleration card product is further influenced.

In this embodiment, the signal acquisition interface 100 is used to connect with an AI acceleration card to be tested;

the first acquisition module 201 and the second acquisition module 202 are used for performing signal acquisition on the communication differential voltage signal, the functional differential voltage signal, the core power supply differential voltage signal, the communication differential current signal, the functional differential current signal and the bus differential current signal which are received through the signal acquisition interface 100;

the first acquisition module 201 is further configured to perform first-type signal processing on the communication differential voltage signal and the communication differential current signal;

configuring a second acquisition module 202 to perform second-class signal processing on the functional differential voltage signal, the core power differential voltage signal, the functional differential current signal and the bus differential current signal;

the control module 203 is configured to control the working modes of the first acquisition module 201 and the second acquisition module 202, and perform data processing on the received differential data sent by the first acquisition module 201 and the second acquisition module 202;

The control module 203 is further configured to store the received differential data into the storage module 204;

the control module 203 is further configured to implement configuration of the communication module 205, and send the received differential data to the outside through the communication module 205;

the control module 203 is further configured to implement user-defined functions, such as an IO trigger function, etc.

In this embodiment, the control module 203 may be an FPGA, where the model of the selected FPGA is not limited, for example, the selected model may be K7325T.

In this embodiment, the first acquisition module 201, the second acquisition module 202 and the control module 203 may be configured to be connected through a board-to-board connector, and the control module 203 and the communication module 205 may be configured to be connected through a board-to-board connector.

Fig. 5 is a block diagram of an acquisition module in an embodiment, referring to fig. 5, based on the scheme shown in fig. 4, the first acquisition module includes a first multiplexer 2011, a first ADC driver 2012, and a first ADC 2013;

the first multiplexer 2011 is connected to the first ADC 2013 through the first ADC driver 2012, and the first ADC 2013 is connected to the control module 203;

the second acquisition module includes a second multiplexer 2021, a second ADC driver 2022, a second ADC 2023;

The second multiplexer 2021 is connected to a second ADC 2023 through a second ADC driver 2022, and the second ADC 2023 is connected to the control module 203.

In this scheme, the first ADC 2013 and the second ADC 2023 are set to collect signals of the communication differential voltage signal, the functional differential voltage signal, the core power differential voltage signal, the communication differential current signal, the functional differential current signal, and the bus differential current signal.

Specifically, in this embodiment, the first multiplexer 2011 is configured to send the differential voltage signal in the signal to be collected to the first ADC driver 2012 for signal preprocessing;

the second multiplexer 2021 is configured to send the differential current signal in the signal to be collected to the second ADC driver 2022 for signal preprocessing.

Illustratively, in this embodiment, the first ADC driver 2012 may include an ADC driving chip according to a usage requirement, for example, the type of the ADC driving chip may be LTC6373;

when the first ADC driver 2012 includes an ADC driving chip, the ADC driving chip is used to sequentially select a pair of communication differential current signals, functional differential current signals, and bus differential current signals for signal preprocessing.

Illustratively, in this aspect, the second ADC driver 2022 may include a plurality of ADC driver chips, which may be the same or different, depending on the usage requirements, for example, it may include two ADC driver chips, ADA4807 and AD 8421.

Illustratively, in this embodiment, when the second ADC driver 2022 includes two ADC driving chips, the second multiplexer 2021 is specifically configured to divide the communication differential current signal, the functional differential current signal, and the bus differential current signal into the first signal group or the second signal group;

one signal group is processed with one ADC driving chip, respectively, for example, the configuration is configured to process the first signal group (the signal in) with ADA4807, and the second signal group with AD 8421.

For example, in this embodiment, the first ADC 2013 may include an ADC chip according to a usage requirement, for example, the type of the ADC chip may be LTC2145.

Illustratively, in this embodiment, the second ADC 2023 may include a plurality of ADC chips, which may be the same or different, for example, may include a plurality of AD7768 chips, and one AD7768 chip is configured for collecting a differential current signal, according to the usage requirement.

Illustratively, in this approach, preprocessing of the differential voltage signal based on the first ADC driver 2012 generates a first signal, a second signal, and a third signal;

Generating a fourth signal, a fifth signal, and a sixth signal based on the second ADC driver 2022 implementing preprocessing of the differential current signal;

performing first-type analog-to-digital conversion on the first signal and the fourth signal by adopting a first ADC 2013, and classifying the result into a low-voltage differential signal group by the control module 203;

the second ADC 2023 is used to perform a second digital-to-analog conversion on the second signal, the third signal, the fifth signal, and the sixth signal, and the control module 203 classifies the result into a digital differential signal group.

Based on the scheme shown in fig. 4, in one embodiment, the communication module 205 may include a variety of communication links.

For example, the communication module 205 may include a first communication link and a second communication link, where the first communication link and the second communication link may be configured to send data in the low voltage differential signal group and data in the digital differential signal group to the same or different terminals or cloud devices.

For example, a first communication link may be configured to send data in the low voltage differential signal group and the digital differential signal group to a cloud storage device and a Web GUI (terminal visualization interface);

and setting a second communication link to send the data in the low-voltage differential signal group and the digital differential signal group to the cloud storage device and the Web GUI (terminal visual interface).

The communication means of the first communication link and the second communication link may be the same or different, for example, in one embodiment, the first communication link is configured as a serial communication link and the second communication link is configured as a network communication link.

Specifically, in this scheme, serial communication is set based on USB 3.0 (including a hardware interface and a communication protocol), and network communication is set based on ethernet (including a hardware interface and a communication protocol).

Fig. 6 is a schematic diagram of another data acquisition card structure in an example, referring to fig. 6, in one possible embodiment, the data acquisition card includes:

the signal acquisition interface 100, the first multiplexer 2011, the second multiplexer 2021, the first operational amplifier 11, the second operational amplifier 12, the third operational amplifier 13, the ADCs (1-4), the programmable controller 21, the storage module 204, the USB communication module 31 and the Ethernet communication module 32;

the signal acquisition interface 100 is connected to the first operational amplifier 11 through the first multiplexer 2011;

the signal acquisition interface 100 is connected with the second operational amplifier 12 and the third operational amplifier 13 through the second multiplexer 2021;

The output ends of the first operational amplifier 11, the second operational amplifier 12 and the third operational amplifier 13 are connected with the appointed input ends of the ADCs (1-4), and the output ends of the ADCs (1-4) are connected with the signal end of the programmable controller 21;

the programmable controller 21 is further connected to the storage module 204, the USB communication module 31, and the ethernet communication module 32, respectively.

In this scheme, the signal acquisition interface 100 is set to support at least 30 differential signal acquisition;

wherein, the first multiplexer 2011 and the first operational amplifier 11 are set for realizing signal preprocessing (amplification) of the differential voltage signal;

the second multiplexer 2021, the second operational amplifier 12, and the third operational amplifier 13 are set for implementing signal preprocessing (amplification) of the differential current signal;

setting an ADC-1 for realizing the analog-to-digital conversion of communication differential voltage signals and communication differential current signals, and setting an ADC-2, an ADC-3 and an ADC-4 for realizing the analog-to-digital conversion of other differential signals except the communication differential voltage signals and the communication differential current signals;

the programmable controller 21 is configured to control the operation mode of the ADCs (1 to 4), store the data converted by the ADCs (1 to 4) in the storage module 204, and send the data converted by the ADCs (1 to 4) to the cloud through the USB communication module 31 and the ethernet communication module 32.

In this embodiment, the first multiplexer 2011 is set to be LTC6373, the second operational amplifier 12 is set to be ADA4807, the ADC-1 is set to be LTC2145, the ADCs (2-4) are set to be AD7768, and the programmable controller 21 is set to be K7325T.

The data acquisition card of this scheme with low costs, small (120 mm is 150 mm), utilize this data acquisition card easily to build the power consumption test system to AI acceleration card, only need be connected to AI acceleration card that awaits measuring through the signal acquisition interface, be connected to public network through a net twine, test environment builds efficiency and greatly improves, can realize batch environment and build and concurrent test, in addition, the channel quantity of data acquisition that data acquisition card can support is many, the signal acquisition of the 48 channels of maximum supportable.

On the basis of the scheme shown in fig. 6, in an alternative embodiment, signal processing circuits may be further arranged at the input end and the output end sides of the first operational amplifier 11, the second operational amplifier 12 and/or the third operational amplifier 13, respectively, when required;

the signal processing circuit may include one or more of a differential mode rejection circuit, a common mode rejection circuit, and an anti-aliasing circuit.

Preferably, in this embodiment, the MXM interface is adopted as the signal acquisition interface based on any one of the schemes corresponding to the data acquisition cards.

In this embodiment, when different types of signal acquisition interfaces are adopted, the configuration modes of the pins of the signal acquisition interfaces are the same, and the following description uses the MXM interface as an example.

The (differential pin pairs of the) MXM interface are defined as differential voltage signal ends and differential current signal ends according to customized contents, and meanwhile, some differential signal ends are defined in a redundant mode, so that the test requirement that the MXM interface can be compatible with a multi-generation AI acceleration card is met.

Specifically, in this embodiment, each differential pin pair of the MXM interface is redefined according to the customized content, so as to meet the test requirement of the specified AI acceleration card;

FIG. 7 is a schematic diagram of a partial pin definition of an MXM interface according to an embodiment, referring to FIG. 7, the initial definition of pins 85 and 87 of the MXM interface is PCIE_RX9_ P, PCIE _RX9_N, respectively, and after redefining pins 85 and 87, the definition of pins are VDD_SOC1_VSNS_ P, VDD _SOC1_VSNS_N, respectively;

after the redefinition of the hardware level of the MXM interface is completed, the FPGA data processing code part modifies the input differential signal pair into consistent naming, and therefore consistency of signal name definition of the software and hardware level is achieved;

when in use, the pins 85 and 87 are connected to the differential voltage signal output end of the first voltage domain of the AI accelerator card, so that the differential voltage signal acquisition of the chip of the first voltage domain is realized through the differential pair (at this time, the pins 85 and 87 are a pair of differential voltage signal ends of the chip).

For example, one AI accelerator card may have multiple voltage domains, and accordingly, the number of voltage domains contained by different AI accelerator cards may be different;

in order to make an MXM interface compatible with the test requirement of a multi-generation (version) AI accelerator card, taking a chip differential voltage signal end definition as an example, on the premise of supporting the number of differential pin pairs of the MXM interface, the chip differential voltage signal end is defined by the upper limit value of the number of voltage domains;

for example, if the maximum number of voltage domains of a certain type correspondingly included in different types of AI accelerator cards is two for a series of AI accelerator cards, two groups of chip differential voltage signal terminals can be defined when the hardware level definition of the MXM interface is performed;

for example, vdd_soc1_vsns_ P, VDD _soc1_vsns_n in fig. 7 is one set of chip differential voltage signal terminals, vdd_soc2_vsns_ P, VDD _soc2_vsns_n is another set of chip differential voltage signal terminals;

when data acquisition is carried out, if the number of certain type of voltage domains correspondingly contained in the tested AI accelerator card is two, the two groups of chip differential power supply signal terminals are both set to be in an enable (active) state, so that the MXM interface can normally acquire differential voltage signals of the two voltage domains;

if the number of voltage domains correspondingly contained in the tested AI accelerator card is one, one group of the two groups of chip differential power signal terminals is set to be in an enable (active) state, and the other group of the two groups of chip differential power signal terminals is set to be in a disable state, so that the MXM interface can normally acquire differential voltage signals of one voltage domain;

Based on the above, the variety and the number of the voltage domains cannot be infinitely increased due to the constraint of the area of the PCB (AI accelerator card), so that only the number of the voltage domains supporting the maximum number is considered when the compatibility is considered;

in the actual test process, only the needed differential signal end is needed to be correspondingly activated for differential signal acquisition according to the actual test requirement, so that the data acquisition of AI acceleration card products with different generations and different forms can be realized by adopting an MXM interface.

In this embodiment, the separation of the control board card and the signal acquisition board card may be realized by adopting a primary-secondary card manner;

the control board card can comprise a control module (FPGA) and a storage module (DDR 3), and is configured to realize processing storage of acquired differential data, control signal acquisition board card work, control communication module work, user-defined function and the like;

the signal acquisition board card can comprise a first acquisition module, a second acquisition module and a communication module shown in fig. 4 and/or 5;

or the first multiplexer 2011, the second multiplexer 2021, the first operational amplifier 11, the second operational amplifier 12, the third operational amplifier 13, the ADCs (1 to 4), the USB communication module 31, and the ethernet communication module 32 shown in fig. 6;

The configuration signal acquisition board card is used for acquiring, conditioning and outputting post-processing data (of the acquired differential data by the FPGA) of analog front-end signals (differential voltage signals and differential current signals) so as to realize real-time acquisition and processing quantification of power consumption information such as voltage and current of the AI accelerator card to be tested.

When the control board card and the signal acquisition board card are designed to be separated in a primary-secondary card mode, the board-to-board connector is adopted to realize connection among the signal acquisition interface, the signal acquisition board card and the control board card, and the data acquisition card has expansibility, compatibility and hardware module reusability;

the hardware module reusability means that when a test scene changes and the current signal acquisition board card cannot be used for realizing data acquisition, the data acquisition board card is replaced, and the control board card is reused.

In this embodiment, the structures of different data acquisition cards may be the same or different under different test scenarios;

taking the scheme shown in fig. 5 as an example, when the test precision of the tested AI accelerator card is seriously inconsistent with the performance parameters of the ADC driver and the ADC adopted by the current data acquisition card, the data acquisition card with the same structure as the current data acquisition card and the ADC driver and the ADC matching with the test precision of the tested AI accelerator card can be selected for data acquisition;

When the morphology of the tested AI accelerator card is changed fundamentally, including the type, the number, the electrical characteristics and the like of the voltage domain are completely inconsistent with the prior tested AI accelerator card, the data acquisition card can be redesigned according to the voltage domain characteristics of the current tested AI accelerator card.

For example, the number of pins and pin definition for connecting the board-to-board connectors between the mother and son cards may be set according to the requirements;

for example, for some different test scenarios, the board-to-board connector may be designed as a standard, i.e. the control board card and the board-to-board connector are reused when the data acquisition board card is replaced, and the pin definitions of the board-to-board connector and the related pins of the control board card are redefined if necessary.

Based on the scheme that the design data acquisition card is separated from the control card, the standardized board-to-board connector is designed, and the MXM interface is adopted as a signal acquisition interface, the power consumption test requirements of different generations of AI acceleration cards can be met by redefining the MXM interface, defining the board-to-board connector, replacing the data acquisition card and multiplexing the control card.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.