CN118041330B - Band gap-based power-on reset circuit - Google Patents

The invention discloses a band gap-based power-on reset circuit, which belongs to the field of integrated circuits and comprises a band gap circuit, a current mirror and a current comparator. The band gap circuit generates stable and accurate reset signals, and overcomes the defect that the reset signals cannot be generated correctly when the traditional power-on reset circuit is powered on for a long time and is powered off rapidly. The clamp switch and the RC low-pass filter are added, so that an error reset signal is not generated when the circuit is interfered. The whole structure can generate a reliable reset signal by using the most basic band gap circuit, the current comparator and the inverter, and the circuit structure is simple and practical.

Band gap-based power-on reset circuit

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a band gap-based power-on reset circuit.

Background

The POR (Power on reset) circuit is used to provide a power on reset signal to the chip. Before the power supply is powered on stably, the POR outputs a reset signal to enable the chip to be in a reset state. After the power supply is stable, the reset signal is released, and the chip can enter a normal working mode. Band gap (Bandgap) circuits are one of the most basic circuit blocks, and most chips integrate the band gap circuits, which can provide a stable reference voltage independent of the supply voltage for the chip.

The conventional POR circuit samples the change of the power supply voltage by using a capacitor, but when the power supply rises for a long time, a reset pulse may not be generated, and when the power supply is powered down rapidly, the charge stored on the capacitor cannot be released rapidly, which will cause a reset failure, so that the circuit cannot work normally. Therefore, it is necessary to design a reliable POR circuit to enable the chip to enter a correct operation state.

Disclosure of Invention

The invention aims to provide a band gap-based power-on reset circuit to solve the problems in the background technology.

In order to solve the technical problems, the present invention provides a band gap-based power-on reset circuit, comprising:

the band gap circuit provides stable reference voltage irrelevant to the power supply voltage for the chip;

a current mirror for mirror-duplicating an input reference current, the magnitude of the output current being proportional to the input reference current;

a current comparator for comparing the magnitudes of the two input currents and outputting a logic high level or a logic low level; wherein,

The band gap circuit comprises a first triode, a second triode, a third triode, a first resistor, a second resistor, an operational amplifier, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first resistor and a second resistor;

The source end of the first PMOS tube, the source end of the second PMOS tube and the source end of the third PMOS tube are connected with the power supply voltage VDD, and the gate ends of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with each other;

The drain end of the first PMOS tube is connected with the negative input end of the operational amplifier, the drain end of the second PMOS tube is connected with the positive input end of the operational amplifier, and the output end of the operational amplifier is simultaneously connected with the gate end of the first PMOS tube and the gate end of the second PMOS tube;

An emitter of the first triode is connected with a drain end of the first PMOS tube, and an emitter of the second triode is connected with a drain end of the second PMOS tube through a first resistor; the base electrode and the collector electrode of the first triode are grounded, and the base electrode and the collector electrode of the second triode are grounded; the emitter of the third triode is connected with the drain end of the third PMOS tube through the second resistor, and the base electrode and the collector electrode of the third triode are grounded.

In one embodiment, the current mirror includes a fourth PMOS transistor, a sixth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;

the gate end of the fourth PMOS tube is connected with the gate end of the third PMOS tube, the source end is connected with the power supply voltage VDD, and the drain end is connected with the source end of the sixth PMOS tube; the drain end of the sixth PMOS tube is connected with the drain end of the seventh NMOS tube, the source end of the seventh NMOS tube is connected with the drain end of the eighth NMOS tube, and the source end of the eighth NMOS tube is grounded;

the gate end of the sixth PMOS tube is interconnected with the gate end of the seventh NMOS tube.

In one embodiment, the current comparator includes a fifth PMOS transistor, a ninth NMOS transistor, and an inverter;

The gate end of the fifth PMOS tube is connected with the gate end of the fourth PMOS tube, the source end is connected with the power supply voltage VDD, and the drain end is simultaneously connected with the input end of the inverter and the drain end of the ninth NMOS tube;

The gate end of the ninth NMOS tube is connected with the gate end and the drain end of the eighth NMOS tube at the same time, and the source end of the ninth NMOS tube is grounded.

In one embodiment, the bandgap-based power-on reset circuit further comprises a low-pass filter composed of a zeroth resistor and a zeroth capacitor; the first end of the zeroth resistor is connected with the drain end of the third PMOS tube, and the first end of the zeroth capacitor is grounded; the second end of the zeroth resistor and the second end of the zeroth capacitor are connected with the gate end of the sixth PMOS tube and the gate end of the seventh NMOS tube together.

In one embodiment, the current mirror has a clamping function, and the sixth PMOS transistor and the seventh NMOS transistor are clamping switches.

In one embodiment, the fourth PMOS transistor and the fifth PMOS transistor have the same width-to-length ratio, and the ninth NMOS transistor and the eighth NMOS transistor have a width-to-length ratio greater than 1.

The band gap circuit generates stable and accurate reset signals, and overcomes the defect that the traditional power-on reset circuit cannot accurately generate reset signals when being powered on for a long time and being powered off rapidly. The clamp switch and the RC low-pass filter are added, so that an error reset signal is not generated when the circuit is interfered. The whole structure can generate a reliable reset signal by using the most basic band gap circuit, the current comparator and the inverter, and the circuit structure is simple and practical.

Drawings

Fig. 1 is a schematic diagram of a band gap based power-on reset circuit according to the present invention.

Fig. 2 is a power-on-reset circuit power-on simulation diagram based on a bandgap circuit.

Detailed Description

The following describes a band gap based power-on reset circuit in further detail with reference to the drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The invention provides a band gap based power-on reset circuit, the structure of which is shown in figure 1, wherein triodes Q1, Q2, Q3, resistors R1, R2, an operational amplifier A1, a PMOS tube M2 and a PMOS tube M3 form a band gap circuit, and the generated reference voltage is as follows:

（1）

V _BE1、V_BE2、V_BE3 is the base-collector voltage of transistors Q1, Q2, Q3, respectively, where |V _BE1-V_BE2 | The temperature coefficient of reference voltage V _BG is approximately zero by adjusting the value of R2/R1 with the temperature coefficient of V _BE3 being positive and the temperature coefficient of V _BE3 being negative. The voltage of V _BG is about 1.2V when using a silicon material CMOS process.

The PMOS tube M4, the PMOS tube M6, the NMOS tube M7 and the NMOS tube M8 are current mirrors with clamping functions, and the PMOS tube M6 and the NMOS tube M7 are clamping switches. The PMOS transistor M5, the NMOS transistor M9, and the inverter I1 form a current comparator, and the inverter I1 may also be a schmitt trigger. The width-to-length ratio of the PMOS tube M4 and the PMOS tube M5 is the same, and the ratio k of the width-to-length ratio of the NMOS tube M9 and the NMOS tube M8 is more than 1.

When the power supply voltage VDD is powered on, the process of the power-on reset circuit generating the reset signal is as shown in fig. 2:

the specific working process is as follows:

When V _BG < Vgs7+ Vgs8, where Vgs7 and Vgs8 are the gate-source voltage of NMOS transistor M7 and the gate-source voltage of NMOS transistor M8, respectively; the NMOS tube M7 is closed, the NMOS tube M8 and the NMOS tube M9 have no current, the voltage at the point A is pulled up by the PMOS tube M5, and the output of the current comparator is low;

When VDD is less than V _BG +VGs6, wherein V _BG -1.2V, vgs6 is the source gate voltage of the PMOS tube M6; the PMOS tube M6 is closed, the NMOS tube M8 and the NMOS tube M9 have no current, the voltage at the point A is pulled up by the PMOS tube M5, and the output of the current comparator is low;

When V _BG > Vgs7+Vs8 and VDD > V _BG +Vs6, wherein V _BG -1.2V, vgs7 and Vgs8 are the gate-source voltage of the NMOS tube M7 and the gate-source voltage of the NMOS tube M8 respectively, and Vgs6 is the source-gate voltage of the PMOS tube M6; the clamp switch PMOS tube M6 and the NMOS tube M7 are conducted, and the NMOS tube M8 and the NMOS tube M9 have conducting currents. If the current I (M5) =i flowing through the PMOS transistor M5, the current I (M9) > I flowing through the NMOS transistor M9, the voltage at point a is pulled down by the NMOS transistor M9, and the current comparator output is high.

Wherein, the resistor R0 and the capacitor C0 form a first-order low-pass filter, V

_BG0

The band gap reference voltage before low-pass filtering is V after low-pass filtering

_BG

. The first-order low-pass filter can stabilize the reference voltage and can generate certain delay to ensure that the reference voltage V

_BG0

After a period of settling, the power-on reset circuit output goes high.

The band gap-based power-on reset circuit provided by the invention can generate a stable and accurate reset signal reference level which is irrelevant to power supply voltage by using the band gap, and the whole circuit is stable and reliable. The clamp switch NMOS tube M7 ensures that the output of the power-on reset circuit is always low when the reference voltage does not reach the normal state. The clamp switch PMOS tube M6 ensures that the output of the power-on reset circuit is always low when the power-on speed of the power supply is too slow or the power supply voltage is too low. The low-pass filter composed of the resistor R0 and the capacitor C0 can stabilize the reference voltage and can also generate delay, so that the output of the power-on reset circuit becomes high after the reference voltage is stabilized for a period of time, the stability and the reliability of the power-on reset circuit are improved, and the whole circuit can be ensured to generate a reset signal correctly.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.