CN118363901B - PCIe device, electronic component and electronic device - Google Patents

The present disclosure provides a PCIe device, an electronic component, and an electronic device adapted to handle data from a host to the device over a PCIe bus. The host judges the data quantity of each data block to be assembled into a linked list data structure, and if the data quantity is smaller than the preset data quantity, the linked list corresponding to the data block is stored into the equipment storage space. A DMA command is generated, bound to the data processing task command and notified to the device through the doorbell. The device receives the doorbell notification, checks if there is a new data processing task command, if so, executes, and checks if the new data processing task command is associated with a DMA command, if so, sends the DMA command to the DMA. And the DMA judges whether the DMA command is a DMA command of a linked list type, if so, the DMA acquires and analyzes the linked list from the address corresponding to the storage space of the equipment, and compared with directly accessing the linked list existing in the storage space of the host, the DMA can save certain delay expenditure.

PCIe device, electronic component and electronic device

Technical Field

The disclosure relates to the technical field of data processing, and in particular relates to PCIe equipment, an electronic component and electronic equipment.

Background

Direct memory access (Direct Memory Access, DMA) is commonly used for inter-memory data handling, a typical data handling scenario is to handle data from Host (Host side) to Device (Device side) over the PCIe bus. The traditional carrying process is as follows: the Host creates a linked list of data to be transmitted and a DMA command in a local storage space, and the Device receives the DMA command and carries out data handling according to the DMA command. Specifically, the Device reads the data block corresponding to one node in the linked list from the storage space of the Host every time, completes the carrying of one data block and carries out the carrying of the next data block. When the data volume of the data block corresponding to one node in the linked list is smaller, intermittent transmission of data occurs, so that the transmission bandwidth of the whole link is affected.

Disclosure of Invention

The invention aims to provide PCIe equipment, an electronic component and electronic equipment so as to improve the link transmission bandwidth.

According to one aspect of the present disclosure, there is provided an electronic component including a memory storing a computer program and a processor executing the computer program stored in the memory to perform the following processing procedure: judging whether the data quantity of each data block to be assembled into a linked list data structure exceeds a preset data quantity or not; storing linked lists corresponding to the data blocks into a storage space of a PCIe device side under the condition that the data volume of the data blocks does not exceed the preset data volume; generating a DMA command, wherein the DMA command carries command type information and a storage address of the linked list at the PCIe equipment end, and the command type information is used for indicating whether the command type of the DMA command is a linked list command type or not; associating the DMA command to a data processing task command; and writing the data processing task command into a ring buffer area of the PCIe equipment end, and sending a command notification to the PCIe equipment through a doorbell mechanism.

Optionally, before generating the DMA command, the processor executes a computer program stored in the memory to implement the following processing steps: judging whether the linked list length of the linked list corresponding to each data block exceeds the preset linked list length. Storing the linked list corresponding to each data block to a storage space of a PCIe device side under the condition that the data amount of each data block does not exceed a preset data amount, including: under the condition that the data quantity of each data block does not exceed the preset data quantity and the linked list length does not exceed the preset linked list length, establishing a linked list in a storage space of the PCIe equipment end; and under the condition that the data quantity of each data block does not exceed the preset data quantity but the linked list length exceeds the preset linked list length, establishing the linked list in the storage space of the local end, and copying the linked list to the storage space of the PCIe equipment end through the synchronous DMA of the local end.

Optionally, the preset data size is 1K, and the preset linked list length is 16 nodes.

Optionally, in the case that the data amount of each data block does not exceed the preset data amount, the processor executes the computer program stored in the memory to implement the following processing steps: and embedding each data block into a corresponding node in the linked list.

According to another aspect of the present disclosure, there is provided a PCIe device including a memory storing a computer program, a processor executing the computer program stored in the memory, and a DMA to implement the following: after receiving the command notification sent by the doorbell mechanism, searching whether a new data processing task command exists in the ring buffer; if a new data processing task command is found, judging whether the data processing task command is associated with a DMA command or not; if a DMA command is associated, the DMA command is sent to the DMA; the DMA is configured to: judging whether the command type of the DMA command is a linked list command type according to the command type information carried in the DMA command; if the command type of the DMA command is a linked list command type, acquiring the linked list according to a storage address of the linked list carried by the DMA command at a PCIe device end, and acquiring and assembling each data block of a linked list data structure according to the linked list.

Optionally, to obtain each data block assembled into a linked list data structure according to the linked list, the DMA is configured to: and acquiring each data block assembled into a linked list data structure from each node of the linked list.

Optionally, the data amount of each data block does not exceed the preset data amount, and the linked list length of the linked list does not exceed the preset linked list length.

Optionally, the preset data size is 1K, and the preset linked list length is 16 nodes.

According to another aspect of the present disclosure, there is provided an electronic component comprising a PCIe device according to any one of the above embodiments.

According to another aspect of the present disclosure, there is provided an electronic device including the electronic assembly according to any one of the above embodiments.

Drawings

Fig. 1 is a schematic diagram of a data transmission process according to an embodiment of the present disclosure.

Detailed Description

Before describing embodiments of the present disclosure, it should be noted that:

Some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.

The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.

It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

It is an object of the present disclosure to provide a data handling scheme suitable for handling data from Host to Device over a PCIe bus, aimed at improving the transmission bandwidth of the link. Specifically, the Host determines the data amount of each data block to be assembled into the linked list data structure in the process of assembling the linked list (LinkList), and if the data amount of each data block is smaller than the predetermined data amount, the linked list corresponding to the data block is stored in the storage space of the Device. A DMA command is generated, bound to the data processing task command and notified to the Device through a doorbell (Doorbell). The Device receives the notification from the Host doorbell, checks if there is a new data processing task command, if so, executes the new data processing task command, and checks if the new data processing task command is associated with a DMA command, if so, sends the DMA command to the DMA. The DMA judges whether the DMA command is a linked list type DMA command, if yes, the DMA directly obtains and analyzes the linked list from the address corresponding to the memory space of the Device, and compared with directly accessing the linked list existing in the memory space of the Host, the DMA command can save a certain delay (LATTERNCY) overhead.

The embodiment of the disclosure provides an electronic component, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program stored in the memory to realize the following processing procedures: judging whether the data quantity of each data block to be assembled into a linked list data structure exceeds a preset data quantity or not; storing linked lists corresponding to the data blocks into a storage space of the PCIe equipment end under the condition that the data quantity of the data blocks does not exceed the preset data quantity; generating a DMA command, wherein the DMA command carries command type information and a storage address of a linked list at a PCIe device end, and the command type information is used for indicating whether the command type of the DMA command is a linked list command type or not; associating the DMA command to a data processing task command; writing the data processing task command into a ring buffer area of the PCIe device side, and sending a command notification to the PCIe device through a doorbell mechanism.

In the embodiments of the present disclosure, there are various implementations of associating a DMA command with a data processing task command, for example, the DMA command may be carried in the data processing task command and may also be embedded in the data processing task command.

In the embodiment of the disclosure, various implementations for storing the linked list in the storage space of the PCIe device end are also available. In one possible implementation, a linked list is created in the local side's memory space and then copied to the PCIe device side's memory space. In another possible implementation, a linked list is created in the storage space of the local end, and then the synchronous DMA of the local end is called to copy the linked list to the storage space of the PCIe device end. In another possible implementation, a linked list is created in the memory space of the PCIe device side. In another possible implementation manner, before generating the DMA command, determining whether the linked list length of the linked list corresponding to each data block exceeds a preset linked list length; under the condition that the data quantity of each data block does not exceed the preset data quantity and the linked list length does not exceed the preset linked list length, establishing a linked list in a storage space of the PCIe equipment end; and under the condition that the data quantity of each data block does not exceed the preset data quantity but the linked list length exceeds the preset linked list length, establishing a linked list in the storage space of the local end, and copying the linked list to the storage space of the PCIe equipment end through the synchronous DMA of the local end. In another possible implementation manner, before generating the DMA command, determining whether the linked list length of the linked list corresponding to each data block exceeds a preset linked list length; under the condition that the data quantity of each data block does not exceed the preset data quantity and the linked list length does not exceed the preset linked list length, establishing a linked list in a storage space of a local end, and copying the linked list to the storage space of a PCIe device end; and under the condition that the data quantity of each data block does not exceed the preset data quantity but the linked list length exceeds the preset linked list length, establishing a linked list in the storage space of the local end, and copying the linked list to the storage space of the PCIe equipment end through the synchronous DMA of the local end.

The local storage space may be, but is not limited to, a memory. The storage space on the PCIe device side may refer to, but is not limited to, storage space on the PCIe device, which is not required to be accessed by the PCIe device through the PCIe bus, and thus the system latency is small.

The embodiment of the disclosure does not limit the specific value of the preset data quantity or the specific value of the preset linked list length, and can be determined according to actual conditions and requirements in practical application. By way of example and not limitation, the predetermined amount of data is 1K and the predetermined linked list length is 16 nodes.

Under the condition that the data volume of each data block does not exceed the preset data volume, the data blocks can be carried in the linked list, so that all the data blocks are stored in the storage space of the PCIe equipment at one time, and the system delay is further reduced. I.e. each data block is embedded in a corresponding node in the linked list.

The electronic component, that is, host, provided in the above embodiment of the present disclosure may have a product form, but is not limited to, a motherboard including a CPU and a memory.

Accordingly, the present disclosure provides a PCIe device comprising a memory, a processor, and a DMA, the memory storing a computer program, the processor executing the computer program stored in the memory to implement the following: after receiving the command notification sent by the doorbell mechanism, searching whether a new data processing task command exists in the ring buffer; if a new data processing task command is found, judging whether the data processing task command is associated with a DMA command or not; if the DMA command is associated, the DMA command is sent to the DMA; the DMA is configured to: judging whether the command type of the DMA command is a linked list command type according to command type information carried in the DMA command; if the command type of the DMA command is a linked list command type, acquiring the linked list according to a storage address of the linked list carried by the DMA command at a PCIe device end, and acquiring and assembling each data block of a linked list data structure according to the linked list.

The data quantity of each data block does not exceed the preset data quantity, and the linked list length of the linked list does not exceed the preset linked list length.

As described above, if the individual data blocks are carried in the linked list, the DMA retrieves the individual data blocks assembled into the linked list data structure from the individual nodes of the linked list.

By way of example and not limitation, the predetermined amount of data is 1K and the predetermined linked list length is 16 nodes.

The PCIe Device is the Device.

The embodiment of the disclosure also provides an electronic component, which comprises the PCIe device according to any one of the embodiments. The product form of the electronic assembly may be, but is not limited to, a graphics card.

Embodiments of the present disclosure also provide an electronic Device that may include an electronic component as a Host in one implementation, and a PCIe Device (or an electronic component including the Device) as a Device in another implementation. In yet another implementation, the electronic Device includes both Host-side electronic components and PCIe devices (or electronic components including the devices) as Device-side.

According to the technical scheme provided by the embodiment of the disclosure, the linked list is stored to the storage space of the Device end at one time by using the synchronous DMA or the Host CPU, so that the longer latterncy overhead caused by direct access of the DMA to the linked list on the storage space of the Host end is saved, and the efficiency is improved.

The following describes in detail the technical solution provided in the embodiments of the present disclosure, taking data handling in the graphics processing process as an example.

The specific implementation process is shown in fig. 1, and comprises the following steps:

In step S101, a client driver (CLIENT DRIVER) at the Host generates source data such as Render/calculate and sends the source data to the KM layer.

In this embodiment, KM layer KERNEL DRIVER (kernel driven).

Step S102, after receiving source data, the KM layer at the Host end judges whether the data quantity of each data block in the source data exceeds 1K and whether the length of a linked list to be generated exceeds 16 nodes.

The length of the linked list can be determined according to the number of data blocks of the source data, and if the source data comprises 10 data blocks, the linked list length is 10 nodes, and each node corresponds to one data block.

The linked list is composed of a plurality of linked list nodes, each linked list node corresponds to one data block, the linked list nodes comprise descriptors corresponding to the data blocks, and index information of the next node.

If the data size of each data block is smaller than 1K and the linked list length is not more than 16 nodes, executing step S103, and establishing a linked list in the storage space of the Device by the KM layer at the Host end.

If the data size of each data block is smaller than 1K and the linked list length is larger than 16 nodes, executing step S104, establishing a linked list in the storage space of the Host end by the KM layer of the Host end, and copying the linked list to the storage space of the Device end through synchronous DMA.

The present disclosure does not limit the process of creating the linked list and may be implemented with reference to existing implementations. In the embodiment of the disclosure, in the case that the data volume of each data block is smaller than 1K, optionally, the data blocks may be embedded in the linked list. I.e. the descriptors of the data blocks of each node, i.e. the data blocks themselves.

Step S105, the KM layer at the Host end generates a DMA command, and embeds the DMA command into a corresponding graphic rendering command, wherein the DMA command carries a storage address of a linked list at the Device end and a DMA command type.

And step S106, after the KM layer at the Host end completes the assembly of the graphic rendering command, writing the graphic rendering command into a ring buffer at the Device end, and informing a CPU at the Device end through Doorbell commands.

Step S107, after the Device CPU receives the doorbell command of the graphics rendering command, it checks whether a new command exists in the ring buffer.

In this embodiment, the read pointer and the write pointer may be compared to determine whether a new command exists.

If the data quantity of the data block is not less than 1K, a linked list is built in the storage space of the Host end by the KM layer of the Host end. The subsequent processing procedure is the same as the prior art, and will not be described here again.

If there is a new command to be processed, the CPU at the Device side executes step S108 to read the new command for processing, and if a DMA command is embedded in the command, the DMA command is sent to the DMA at the Device side.

Step S109, the DMA of the Device side judges that the DMA command is a DMA command of a linked list type according to the command type in the DMA command, and reads a node of a linked list from a storage space of the Device side according to a linked list storage address carried in the DMA command, analyzes and processes the node and then reads the next node of the linked list until the processing of all the nodes of the linked list is completed.

The processing of the node may include: and reading the corresponding data block according to the descriptor.

When the command of one ring buffer is processed, the CPU at the Device end informs that a new command needs to be processed through the KICK GPU. In addition, the CPU at the Device end will loop to determine whether there is a new command in the ring buffer to be processed until all the commands in the ring buffer are processed.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.